JPH0447850B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the configuration of a multiplier with an accumulation function.

Conventional Structure and Problems When the input signal is a binary signal expressed in two's complement, a multiplication circuit for the multiplicand X and the multiplier Y can be realized with the structure shown in FIG.

In multiplication in two's complement representation, the multiplicand X and multiplier Y of the input signal are expressed by equations (1) and (2), and the product P is expressed as (3)
It becomes like the formula.

X=-2 ^n-1・X _s + _o-1 〓 ⁱ⁼¹ 2 ^i-1 X _i ...(1) Y=-2 ^m-1・Y _s + _n-1 〓 ^j=1 2 ^{j- 1} Y _j ……(2) P=X・Y=2 ^n+m-2・X _s・Y _s + _o-1 〓 ⁱ⁼¹ _n-1 〓 ^j=1 (X _i・Y _j )2 ^{i +j-2} −X _s・_n-1 〓 ^j=1 2 ^j-1・Y _j・2 ^n-1 −Y _s・_o-1 〓 ⁱ⁼¹ 2 ^i-1・X _i・2 ^m-1 ...(3) Here, n is the bit word length of the multiplicand X, m is the bit word length of the multiplier Y, X _s and Y _s are the sign bits, and X _i
and Y _j represent each numerical bit.

In the calculation shown in equation (3), the second term can be calculated using an array method, but the first, third, and fourth terms must be corrected, making the circuit configuration complicated. Therefore, a proposal has been made to simplify the circuit configuration by transforming equation (3) as shown below.

P=(X _s・Y _s −X _s −Y _s )・2 ^n+m-2 + _o-1 〓 ⁱ⁼¹ _n-1 〓 ^j=1 (X _i・Y _j ) ・2 ^{i+j- 2} + (X _s・_n-1 〓 ^j=1・2 ^j-1・_j ) 2 ^n-1 + (Y _s・_o-1 〓 ⁱ⁼¹・2 ^i-1・_i )・2 ^n-1 X _s・2 ^n-1 +Y _s・2 ^m-1 ...(4) In equation (4), the first term (X _s・Y _s −X _s −Y _s )
is determined by the OR operation between X _s and Y _s , so the multiplication process of equation (4) is shown below.

Here, X _s + Y _s indicates the OR operation of X _s and Y _s ,
_Ps indicates the sign bit of the product output. this
FIG. 1 shows the circuit configuration for performing the multiplication of equation (4).

For the addition of partial products, a carry-save method is used, which maintains regularity in the circuit configuration and allows high-speed calculations.

In the figure, X ₁ to _{X s} are input terminals for each bit of the multiplicand X, Y ₁ to _{Y s} are input terminals for each bit of the multiplier Y, and P ₁ to P _s are output terminals for each bit of the product P. . However, X _s , Y _s , and P _s are sign bits of X, Y, and P, respectively, and X ₁ to X ₃ , Y ₁ to _{Y 3} , and P ₁ to _{P 6} are numerical bits of X, Y, and P, respectively. It is. 101
〜106 is the AND gate shown in FIG. 2, and 107 is the AND gate shown in FIG.
It is an OR gate. 108 to 110 are blocks composed of an AND gate 301 and a half adder 302 shown in FIG. 3, and 111 to 116 are shown in FIG. 4.
Blocks 117 to 120 consisting of an AND gate 401 and a full adder 402 are full adders.
121 to 126 are inverters, which input the sign bit _Xs of the multiplicand X and the numerical value bits (Y ₁ to Y ₃ ) of the multiplier Y.
If you want to generate a partial product with , invert Y ₁ ~ _{Y 3} and
When generating a partial product between the sign bit Y _s of the multiplier Y and the numerical bits ₍ X ₁ to X ₃ ) of _the multiplicand X,
By inverting , adding X _s and Y _s to the digit corresponding to P ₄ , and adding the OR output of X _s and Y _s to the digit corresponding to P _s , the 2 The multiplicand and multiplier can be multiplied in complement representation. Here, the carry signal 127 of the adder 120 that calculates the sign bit does not affect the product outputs P ₁ to P _s and is therefore regarded as an invalid signal.

When adding an accumulation function to such a two's complement multiplier, it can be realized by adding one stage of an adder to the multiplier circuit shown in FIG. 1, as shown in FIG. In Fig. 5, 501 is 2 shown in Fig. 1.
This is a complement multiplication circuit. Full adders 502 to 511 and latch circuits 512 to 521 perform accumulation operations. '' 512 to 521 are latch circuits constituting means for storing cumulative multiplication results, and are provided with means for inputting the previous operation results held in the latch circuits 512 to 521 to the adders 502 to 511. As a result, the multiplication output of the multiplication circuit 501 and the previous calculation result are added to the adders 502 to 5.
11 and performs an accumulation operation. Here, adders 509 to 511 are used to expand the bit width for cumulative addition. Furthermore, the reason why the output of adder 120 is added to adders 508 to 511 is to match the bit widths of the two's complement signals. P ₁ -P _s are the output signals, and P _s is the sign bit.

Cumulative addition is performed by adding one stage of adder to the output of the multiplier circuit, but if the calculation is to be performed even faster, CLA (Carry Look
Ahead) circuit is used.

This CLA circuit is used in the part where it takes the longest time to propagate the carry signal, and in the multiplication circuit, it is used in the part where the carry signal is transferred in the horizontal direction, and in FIG. ~
120 and adders 502 to 5
If CLA is used in the addition stage composed of 11, calculations can be performed at high speed.

However, CLA has a large circuit scale, and adding this CLA to two adder stages complicates the circuit and increases power consumption, which is not preferable for integrated circuit implementation.

OBJECTS OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide a multiplier with a simple circuit configuration and an accumulation function suitable for high-speed calculations.

Structure of the Invention According to the present invention, by providing an adder stage for cumulative addition in the middle of an adder stage for multiplication, high-speed calculation is possible by simply adding one stage of CLA.

DESCRIPTION OF THE EMBODIMENT FIG. 6 shows an embodiment of the present invention, and for ease of explanation, the numbers of the components common to those in FIG. 1 are the same as in FIG. 1.

X ₁ to _{X s} are input terminals for each bit of multiplicand X, Y ₁
~ _Ys is the input terminal for each bit of the multiplier Y, and _Xs ,
Y _s is a sign bit, and X ₁ -X ₃ and Y ₁ -Y ₃ are each numerical bits.

101 to 106 are AND gates, and 107 is an OR gate. 108 to 110 are blocks composed of AND gates and half adders, and 111 to 116 are blocks composed of AND gates and half adders.
A block consisting of an AND gate and a full adder,
Full adders 117 to 120 and inverters 121 to 126 have the same configuration as in FIG. 1. 60
2 to 611 are full adders for cumulative addition. As shown in the figure, it is inserted between the addition stage composed of full adders 117 to 120 and the addition stage composed of full adders 114 to 116, and held in latch circuits 615 to 624 (means for storing cumulative multiplication results). The cumulative calculation is performed by providing means for inputting the result of the previous calculation.

With such a configuration, the carry signal of the adder for calculating the sign bit, which was considered to be an invalid signal as explained in FIG. 1, is added to the upper digits. Therefore, in the present invention, this invalid signal is compensated for as follows. The invalid signal is input as a carry signal from the lower 7th bit to the 8th bit. Therefore, compensation can be achieved by adding the following compensation signal.

On the other hand, in the case of addition of two's complement signals, the sign bit must be expanded in order to match the bit width. This extended signal is 8 to 8 when the multiplication result is negative.
This is a signal in which the 10th bit is "1", and is the same as the above-mentioned compensation signal.

Therefore, when an invalid signal is generated and when extending a negative sign bit, it is sufficient to add signals whose 8th to 10th bits are "1".

An invalid signal occurs when the two signals of the multiplicand X and the multiplier Y of the multiplier are both negative, when X is negative and Y is zero, and when X is zero and Y is negative. Therefore, the control signal C of the compensation signal is: C= _Xs・_Ys + _Xs・( ₁ + ₂ + ₃ )+ _Ys
・( ₁ + ₂ + ₃ ).

Furthermore, if the multiplication result is negative, "1" must be expanded as a sign bit. The multiplication result is negative when one of the two input signals is negative and the other is positive except for zero, and the signal S that controls the extension of the sign bit is S=X _s Y _s .

Here, as mentioned above, the compensation of the invalid signal and the extension of the sign bit can be performed in the same process, so the control signal CT for this process is CT=C+S=X _s・Y _s +X _s・( ₁ + _{2 ＋3} ）＋ _Ys・
( ₁ + ₂ + ₃ ) +X _s Y _s =X _s・Y _s +X _s・_s + _s・Y _s +X _s・( ₁ + ₂ +
₃ ) + _Ys・( ₁ + ₂ + ₃ )= _Xs + _Ys + _Xs・( ₁ + ₂ + ₃ )+ _Ys・( _1+
2 + ₃ ) = X _s + Y _s .

X _{s +} Y _s is determined by the R operation of the sign bits of the multiplicand X and the multiplier Y _, and as shown in FIG.
By adding 5 to an 8-10 bit adder expanded to perform cumulative addition, invalid signal compensation and sign bit expansion can be achieved.

When CLA is used for speeding up by having the configuration shown in FIG.
If applied to only one stage consisting of and 612 to 614, high-speed calculation can be performed.

Effects of the Invention According to the present invention, in a multiplier having an accumulation function, by providing an adder for performing an accumulation operation in the middle of the multiplication adder, the addition stage to which a carry signal is transferred in the horizontal direction is Only one stage available, CLA
High-speed calculation can be performed by using only one stage of circuit. Therefore, when realizing a high-speed accumulation multiplication circuit, it can be done with a simple circuit configuration, consumes less power, and can be easily implemented as an LSI.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a multiplier, Figures 2 to 4 are circuit explanatory diagrams of the multiplier in Figure 1, Figure 5 is a block diagram of a conventional accumulator, and Figure 6 is an accumulator according to the present invention. FIG. 2 is a circuit configuration diagram of an embodiment of a multiplier. 602-611...Full adder for cumulative operation, 61
5-624...Latch circuit.

Claims (1)

[Scope of Claims] 1. A plurality of addition stages for multiplication that performs addition of partial products; an addition stage for cumulative addition having an extension bit located between the plurality of addition stages for multiplication;
A cumulative multiplier comprising: storage means for holding cumulative addition results; and means for inputting all bit outputs of the storage means including extended bits to the addition stage for cumulative addition. 2 Find the logical sum of the sign bit of the multiplicand and the multiplier
2. An accumulation multiplier according to claim 1, comprising an OR gate and means for adding the output of the OR gate to expanded bits for performing an accumulation operation.