JPS6349835A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To obtain a high-speed arithmetic processor that can be easily packaged into an LSI chip by preventing the carry transmission in an internal addition/subtraction mode and at the same time simplifying a circuit constitution. CONSTITUTION:A means which obtains a signal pi121 showing whether the i-th rows xi and yi of an augend and an addend are non-negative or not consists of a NAND circuit. A means which obtains a signal vi showing the intermediate carry of the i-th row consists of a circuit including NOR circuits 112 and 113, an exclusive OR circuit 114 and a composite gate 131. A means which obtains a signal ui showing an intermediate sum of the i-th row consists of a circuit including exclusive OR circuits 114 and 132. Then a means which decides the final sums <s>161 and <a>162 of the i-th digit from the signal ui and a signal vi-1 showing the intermediate carry from a place lower by a digit consists of a circuit including a NAND circuit 151 and a NOR circuit 152.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic processing device, and more particularly to a high-speed arithmetic processing device that includes addition and subtraction in internal operations and is suitable for LSI implementation.

Conventional technology Conventionally, for example, regarding high-speed adders, see the Journal of the 1986 IEICE General Conference, p. 2-187, and regarding high-speed multipliers, see the Transactions of the Institute of Electronics and Communication Engineers, Vol. J 6.
6 D, A6 (1983) pp. 683-6
It is discussed on page 90, and high-speed dividers are also discussed in IEICE Transactions, Vol.

J 67 D, & 4 (1984) pp. 450-467. These are arithmetic units that use a redundant binary representation (a type of signed digit representation) in which each digit is expressed as an element (-1, 0, 1) to perform addition, multiplication, or division using a combinational circuit. Therefore, it is superior to other arithmetic units in terms of calculation processing time and regular array structure.

Problems to be Solved by the Invention The above-mentioned conventional technology utilizes the feature of the ECL logic element that can perform NOR and OR at the same time regarding high-speed arithmetic units to perform multiplication or division, or perform exclusive OR of 0MO8 or transfer gate. A method has been proposed in which the addition is implemented as a combinational circuit using a redundant binary addition cell, but compared to about 30 transistors for a binary addition cell, a redundant binary addition cell has about 60 transistors. many. Therefore, there are problems such as (1) the number of elements becomes enormous when the number of digits to be calculated becomes large, and (2) the number of stages of individual addition cells is large.

An object of the present invention is to improve such conventional problems, to realize an arithmetic processing unit as a combinational circuit with a regular circuit structure and a small number of elements, to prevent carry propagation in internal addition/subtraction, and to improve the circuit configuration. The object of the present invention is to provide a high-speed arithmetic processing device that can be easily mounted on an LSI chip by simplifying the process.

Means for solving the problem The above purpose is to increase (subtract) the internal calculations of the processing unit.
The arithmetic step includes calculating the intermediate carry C in the first digit and the intermediate sum S in the first digit from the addition (subtraction) number and the liquid addition (subtraction) number, and the intermediate sum S of each one digit and the one digit. When performing the operation in two steps, including the step of calculating the sum s+k of the intermediate carry k from the 1st-1st digit of the lower digits, for each digit of addition (subtraction), 1 digit and i-1 of the summand
It has a first means for obtaining a binary signal p representing the combination state of each digit, and the first digit of the addend, the first digit of the summand, and the signal p are input, and the signal p and the intermediate signal p are input. A second means for obtaining a binary signal U determined by the difference p-s from the sum S (or sum p+S); 2 determined by the sum p+k (or difference p-k) of the signal p and the intermediate carry k by inputting the output signal of the first means provided at the 1st and 2nd digits.
a third means for obtaining the value signal V; and (2) a fourth means for obtaining the sum of the intermediate sum S of the first digit and the intermediate carry k from the i-1st digit by inputting only the signals u and v. This is achieved by providing

For example, in internal operations, each digit is represented by an element of 0, a positive integer, or a negative integer corresponding to the positive integer.
D (Signed Digit) representation, ie, signed digit representation, is used to represent the internal operation number. In other words, each digit is (-1, o, 1), (-2°-1, o,
1.2) Or (-N,..., -1゜o, 1....
, N), etc., to provide redundancy so that one number can be expressed in several ways. In addition (or subtraction), even if there is a carry (or borrow) from the lower digit, the intermediate sum (or difference) of that digit is the same as the carry (or borrow) from the lower digit. To ensure that the sum (or difference) is within one digit, carry (or borrow) the middle digit of that digit and add the middle sum (or difference).
can be determined respectively. This prevents propagation of carry (or borrow) during addition (or subtraction), and allows parallel addition (or subtraction) by combinational circuits to be performed in a fixed time regardless of the number of digits in the operation number. For example, the SD expression (-1, o, 1) represents each digit (
In other words, in redundant binary representation), a carry (or borrow) can be made to propagate by at most one digit during addition (or subtraction). Regarding this,
Journal of the Institute of Electronics and Communication Engineers, 'io1. J67-D.

A4 (1984), pp. 460 to 467, or Transactions of the Institute of Electronics and Communication Engineers, Vow, J e 6-D.

A 6 (1983), pages 683 to 690 provide an explanation.

In the following, an adder in which both the summand and the addend are redundant binary numbers will be described.

Table 1 shows an example of an addition rule in which a carry propagates by at most one digit in redundant binary representation.

(Leaving space below) Table 1 The addition rules as shown in Table 1 are determined so that the sum of the intermediate sum Si in the first digit and the intermediate carry number C knee 1 from the lowest digit will never be carried. . Therefore, the intermediate sum g
Between i and the intermediate carry number C knee from the lowest digit,
A relationship is always established in which one is non-negative and the other is non-pressure. That is, either Si is non-negative and 'i-+ is non-pressure, or conversely, Si is non-pressure and 'i-+ is non-negative. Therefore, the intermediate sum S
Both i and intermediate carry C knee can be converted into binary signals of 0 or 1.

In the present invention, when both the i-1st digit of the addend and the 1-1st digit of the summand are non-negative, the first means outputs the signal 4-1 to O.
and when at least one of them is negative, the signal pnee1 is set to 1, then by the third means, I'i-++Ci-+
A binary signal 11, represented by the addition value of or the logical negation thereof, is determined by the second means, and the binary signal 11, represented by the subtraction value of p, -8, or the logical negation thereof, is determined by the second means.
i, and further by a fourth means, the binary signal v
Intermediate carry C from i-1st digit only from i-+ and ui
Since the final sum of the knee and the intermediate sum Si at the first digit can be determined, the circuit configuration of the adder can be simplified.

Note that the first means is defined as pi-1-1 when both the i-1st digit of the addend and the 1-1st digit of the summand are non-negative, p-ni when at least one is negative, and 20. When the change is made so that
The means determines a binary sign ui representing the addition value of p□-, +sd or its logical negation.

Also, either the summand or the addend is a redundant binary number in which all digits are non-negative (or non-pressure), that is, 2
If it is a base number, the signal p can be omitted and the first
means determine a binary signal V indicating the value of Ci-+ (or 1-0 knee) or its logical negation;
The means determines a binary number ui indicating the value of -5i (or 1+s) or its logical negation.

Therefore, since the number of elements in each adder can be reduced and unnecessary signal lines can be omitted, the circuit configuration of each adder can be simplified, and high-speed arithmetic processing devices can be easily converted into LSZ.

Example Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment will be explained with reference to FIG.

Table 1 shows an example of an addition rule in which a carry in redundant binary representation propagates only one camellia. When performing redundant addition using such an addition rule, as described above, the intermediate sum and intermediate carry of the redundant binary representation are converted into binary representation using the following method.

The addition rules in Table 1 differ depending on the combination status of each lower digit in the addend and the summand. Therefore, first, the signal p representing the combination state of the addition and the value of the first digit of the summand
i, and when both the addend and the first digit of the summand are non-negative (that is, the intermediate carry of the first digit is non-negative, and the i-th
(If the intermediate carry in the +1 digit is non-positive) p = 0, and at least one is negative (that is, if the intermediate carry in the 1st digit is non-positive and the intermediate sum in the 1+1 digit is non-negative) ) Pi=1. Further, let the intermediate carry of the first digit be Ci, and let the intermediate sum of the first digit be Si. Next, the intermediate sum S□ and the intermediate carry Ci−+ are expressed as “ ” pi−+ −Si vi−+ = pi−+ ” 'i−+,
Convert to binary numbers U and V knee 1, respectively. However, S engineering and C knee 1 are redundant binary digits, that is, (-1,
o, is a number that takes any element of 1), and is a number that takes any element of U., v,
, p, is a second-order number, L:L-11-j, that is, a number that takes any element of (o, 1). Also, the subscript i-1 is the digit one lower than the first digit, that is, the i-th digit.
- indicates one digit. Hereinafter, for the sake of simplicity, ui will be referred to as a signal representing the intermediate sum of the first digit, and V will be referred to as a signal representing the intermediate carry from the i-1st digit.

At this time, the addition rule for ui and V is determined from Table 1 as follows. pi□1-0, split addend yi-
1. Me 1. When the summand X and knee are both non-negative, the ui is determined according to the rules shown in Table 2, and the V-k is determined according to the rules shown in Table 3. Also, p = 1, that is, the addend y
, knee 1 of summand xi-+
1-1 If at least one of them is negative, the U-work is determined according to the rules shown in Table 4, and the V-work is determined according to the rules shown in Table 5. However, pi is the first
When both the digit addend yi and the summand x1 are non-negative, pi
=○, when either xi or yi is negative, p = 1
becomes.

Table 2 Table 3 (blank below) Table 4 Table 5 In addition, pi is the logical negation of pi (if Dp = 0 then T
'i ''' * pi '''' If 1, it means p4=o).

Next, in one embodiment of the present invention, the redundant binary numbers, the summand Xi, the addend y, and the addend 2 are coded in binary as follows.

The first digit of the redundant binary number is
Bit signals x, x, , y, y, and Z f
It is expressed as 1 12, and -1 is expressed as 01, 0 as 10, and 1 as 11 as a 2-bit signal. For example, as shown in Table 6, the X operation is expressed as a 2-bit binary signal x, x. However, xi is a signal meaning the sign part of X-factor, and X-factor is the magnitude (absolute value) of X-factor.

Table 6 When binary encoding of G/ζ redundant binary numbers is performed as shown in Table 6, the absolute value S of the state signal pis intermediate sum of the summand and addend is
The signal ui representing the intermediate sum and the signal V representing the intermediate carry are p1 = 8 + y = 8, respectively. ■? E E I U engineering = Si ■ pi - + v, = (si - p yo one,) - (xi ten yi) ・(x
, +y・ ). 1, the final sum zi is z, =
2-bit signal expressed by the logical formula u, +7゜z l 1-1 z, -u, ■vi-+ 2. 2. given by
1. In the above logical formula, ・ is the logical product (AND
), + stands for logical sum (OR), and ■ stands for exclusive disjunction (EX
-OR), x, , y: and S-p, respectively.
It is a logical negation of p knee 1.

FIG. 1 is a schematic circuit diagram showing one embodiment of the present invention.

In the figure, gates 111 and 151 are NAND circuits, gate 1
12 and 113 are OR circuits, 114 and 132 are exclusive OR circuits, gate 162 is an exclusive NOR circuit, gate 133 is an inverter circuit, gate 131 is AND-N
It is an OR compound gate.

Furthermore, the signals X, 101 and X, 102 are 2-bit signals representing the first digit Xi of the redundant binary number which is the summand, 7.10
3 and y, 104 are redundant 2-factors that are addends.
2 representing the i-th digit y of the decimal number
A bit signal, 1-bit signal 121 represents a combination state signal p of the value in the first digit of the addend and summand, and a 1-bit signal 123 represents the value in the 1-1 digit of the addend and summand. represents the combined state signal pi-+ of 1 pit signal 12
2 is a signal S representing the absolute value of the intermediate sum in the first digit. A signal 141 is a logical negation signal vl of the signal vi representing the intermediate carry in the first digit, and a signal 143 is a logical negation signal vl of the signal vi representing the intermediate carry in the first digit.
The intermediate carry V from the -1 digit is the logical negation signal V knee1, and the signal 142 is the signal U representing the intermediate sum in the first digit. Output signals Z, 1θ1 and z, 162 are two-pit signals representing the first digit Zi of the final sum.

In Figure 1, the summand and the first digit of the addend.

The means for obtaining the signal p 121 representing whether both yi are non-negative is realized by a NAND circuit, and the means for obtaining the signal V representing an intermediate carry in the first digit is a NOR circuit.
It is realized by a circuit composed of circuits 112 and 113, an exclusive OR circuit 114, and a composite gate 131, and the means for obtaining the signal U representing the intermediate sum in the first digit is an exclusive OR circuit.
This is realized by a circuit composed of R circuits 114 and 132. In particular, the exclusive OR circuit 114 determines the absolute upper value S 122 of the intermediate sum from the magnitude of the first digit of the addend (that is, the absolute value) X, 102 and the magnitude of the first digit of the addend, 7.104, The exclusive OR circuit 132 determines pi−+=Q according to the state of the one lower digit in the addend and the summand.
When, ui=o■s.

In other words, ui=s When p knee 1 = 1, U work = 1 ■ S work -a In other words, ui=s 工 works like this. However, 0■S,=S,.

1 ■s, = s, can be easily inferred. Also, intermediate 1
The final sum in the first digit is 2□161 from the signal U representing the process and the signal vi-+ representing the intermediate carry from the lowest digit.
and z, 162 is determined by the NAND circuit 15.
1 and an exclusive NOR circuit 152. In addition, signals 121, 122, 123
, 141, 142 and 143 are all 1-pit binary signals.

Moreover, the above vi can also be determined by the following logical formula.

vi=snee p, + (x, +y,)・x,・y
.

Next, a second embodiment will be explained with reference to FIG.

The second embodiment differs from the first embodiment in that one of the summands or addends is a redundant binary number, and the other is a redundant binary number in which each digit is non-negative (that is, it can be considered as a binary number). This is an example of a case where the number is a binary number (hereinafter referred to simply as a binary number).

In particular, in this example, the summand is redundant binary, and the addend is binary. Toe 9, X-factor takes any element of (-1, o, 1), and yl takes any element of (o, 1). Therefore, it is possible to always make the intermediate carry of each digit non-negative and the intermediate sum always non-positive, so in the first embodiment, pi may always be set to ◯.

In other words, for the intermediate sum S of the 1st digit and the intermediate carry C1-1 of the 1-1st digit (i = 1.2..., n), by the formula -5i, the above Define signal U and vi-+. In this case, S is a non-positive redundant binary number, 'i-+ is a non-negative redundant 2
It is a base number.

Also, since the addition rule for U and vi is always pi = ○ for all hosts, as can be seen from Tables 2 and 3, the ui is determined according to the rules shown in Table 7, and the mi is Determine according to the rules shown in Table 8. However, Table 7
1 Table 8 is a part of Tables 2 and 3, respectively, where pi=Q.

Table 7 Table 8 Furthermore, when the redundant binary numbers are binary coded as shown in Table 6, the signal U representing the intermediate sum and the signal Vi representing the intermediate carry become simple, and U = 51 vl=xio(xi+yi). Further, the signal Si representing the absolute value of the intermediate sum and the 2-bit signal azz representing the final sum zi are determined in the same manner as in the first embodiment.

FIG. 2 is a schematic circuit diagram showing an embodiment of redundant binary and binary addition according to the present invention. In the figure, gate 21
1 is an OR-MANE) compound gate.

Gate 212 is an exclusive OR circuit, gate 231 is a HAN
D circuit, gate 232 is an exclusive NOR circuit.

Also, the signal X, 201, ! , 202 , V.
221.

ui 222, 7±, 223, Z engineering 241
and Z, 242 are respectively the signal X1 in FIG.

Engineering 101,) c, 10
2, Ti 141, ui142°V knee, 143. Z
, 161 and Z, 162, and signal 104 is a 1-bit signal representing the first digit yl of the addend, which is binary.

In FIG. 2, the means for obtaining (the logical negation of) the signal vi representing the intermediate carry in the first digit is realized by a composite gate 211, and the means for obtaining the signal U representing the intermediate sum in the first method is an exclusive OR This is realized by circuit 212. In addition, the final sum zi241 at the first digit is obtained from the signal U representing the intermediate sum and the signal vi-+ representing the intermediate carry from the one lower digit.
and zi242 is determined by the HAND circuit 23.
1 and an exclusive NOR circuit 232.

In addition, in FIG. 2, pi=0″p is identical in FIG.
Mini 0″p knee i:○・yi = y, fixed, unnecessary game) 111, 132 and composite gate signal p knee,
123 is removed and the gate 113 is connected to the signal
, 101 as inputs, and by combining the inverter circuit 133, a NOR circuit in place of the gate 132, and the NOR circuit 112 and an inverter circuit in place of the gate 113 to form an 0R-HAND composite gate.

Further, in the second embodiment, redundant addition between binary numbers is performed identically to X, :1. This can be done by setting X1=X1. In other words, the binary numbers are X.

The redundant addition of y4 can be realized by a circuit in FIG. 2 in which the 0R-NAND composite gate 211 is replaced with a NOR circuit that receives signals 202 and 204 as inputs.

In the above embodiment, the state signal pl of the summand and the summand is set to p = 0 when both the summand and the first digit of the summand are non-negative, and 1) i = 1, and the redundant binary numbers are coded as shown in Table 6.
It can also be easily realized by changing these. In addition, the exclusive OR circuit in the figure can be replaced with an exclusive NOR circuit by combining it with an inverter in various ways, a NAND circuit can be replaced with a NOR circuit by combining it with an inverter, and a composite gate or exclusive OR circuit can be replaced with a NAND circuit, It can be configured with a combination of NOR circuits or inverters, or
It is known that the reverse can easily be done.

For example, contrary to the first embodiment, the combination state signal pi of the first digit value of the addend and the summand is
If both of the digits are non-negative, then pi = 11, and if at least one of them is negative, then p = 1, then the intermediate carry Ci-+ and the intermediate sum S are respectively expressed in binary form vi-+ by the following equations.
and can be converted to ui.

ui: pi, +S-work"i-+ = pi-+'i-1 At this time, the addition rule for ui and V-work can be easily determined from Table 1 in the same manner as in the first embodiment.

In addition, Table 9 shows the binary coding of the redundant binary numbers Xi, 7 earth, and Z engineering.
As shown in , -1 is changed to 11. Express o as 00.1 as 01.

Table 9 At this time, the combination state signal of the value in the first digit of the summand and the addend 1) 4, the absolute value Si of the intermediate sum in the first digit
, a signal U representing an intermediate sum, and a signal V representing an intermediate carry.
The soil is respectively 1) 1 = xi + yi s, = x ■y 1 1 k u4 = s k p, -1 vl- (si + pl-, ).

(x, -y, +x, +y, )1 1
It can be determined using the logical formula of 1. The final sum Zi is still zi=u 工■
V knee.

It is given by 2-bit signals z and z expressed by the logical formula. The circuit diagram of this example can be constructed as shown in FIG.

FIG. 3 is a schematic circuit diagram showing another embodiment of the invention. In the figure, gate 311 is a NOR circuit, gate 312,
351 is a NAND circuit, gate 313 is an exclusive OR circuit, gate 332 is an exclusive NOR circuit, gate 352 is an inverter circuit, gate 331 is an AND-NOR composite gate, and gate 352 is an 0R-NAND composite gate.

Also, signals 301.302.303.304.

321.322, 323, 341.342.343゜3
81 and 362 are the signals xi101 and X in FIG.
,102.7,103.71104゜1
Engineering p.121, S, 122. p, 123. Vi14
Logical negation of 1, logical negation of U engineering 142, 74-. 143
Logical negation of 1, corresponding to z 161 and z 162
I do it.

In the circuit diagrams of the embodiments shown in FIGS. 1 and 3 above, when using a 6-transistor exclusive OR circuit and an exclusive NOR circuit, the number of transistors is 44 transistors and 42 transistors, respectively, and the number of gate stages in the critical path is 4. It becomes the first step.

In the above embodiment, redundant addition of redundant binary numbers, redundant
Although the redundant addition between a base number and a redundant binary number in which each digit is non-negative has been described, it can be inferred that the present invention can be easily applied to redundant addition or subtraction between a redundant binary number and a redundant binary number in which each digit is non-negative. can.

Furthermore, although this embodiment is realized using binary logic with CMOS circuit in mind, other technologies (for example, NMO3, ]!
(CL, TTL, IIL, etc.) Alui can be easily realized using multivalued logic.

According to this embodiment, the delay required to perform addition between redundant binary numbers is 4 gate stages regardless of the number of digits of the operation number, and is about 1 to 2 steps per addition operation compared to the conventional method. The gate stage is shortened. In addition, since the circuit corresponding to one digit of the addition operation can be configured with approximately 42 transistors, the number of elements in the redundant adder can be reduced by approximately 20-30% compared to the conventional one, and the circuit configuration is simplified. There are effects such as being able to do it.

Effects of the Invention According to the present invention, when using a signed digit representation number in which each digit can take a positive, ○, or negative value for addition/subtraction that occurs in the internal calculations of an arithmetic processing device, Since the cell can be realized with a simple circuit and addition and subtraction can be processed in a fixed time regardless of the number of digits, (1) the number of elements in the arithmetic processing unit can be reduced; ) The speed of the arithmetic processing device can be increased, (3) the circuit configuration can be relatively simplified, and (4) the arithmetic processing device can be easily and economically implemented as an LSI.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram showing a first embodiment of the present invention;
The figure is a schematic circuit diagram showing a second embodiment of the invention, and FIG. 3 is a schematic circuit diagram showing a third embodiment of the invention. 111.161.231.312,361...
NAND circuit, 112, 113, 311...N
OR circuit, 133.353... river/inverter circuit, 1
14゜132, 212, 313...exclusive OR
Circuit, 152.232.332...Exclusive NO
R circuit, 131.331-...AND-NOR composite circuit, 211.352...0R-NAND composite circuit. Name of agent: Patent attorney Toshio Nakao and one other name
11] χ゛ χa y″ YcLFigure 2χjxa: γ( Figure 3

Claims (2)

[Claims] (1) Addition (subtraction) and addend (subtraction) for each i digit of addition (subtraction)
an arithmetic step of calculating an intermediate sum (intermediate difference) s and an intermediate carry (intermediate borrow) c at the i-th digit from the number; In an arithmetic processing device consisting of two steps, including an arithmetic step for calculating the sum s+k of intermediate carry (intermediate digit borrow) k from a digit, for each i digit of addition (subtraction), the i-1st digit of the addend is and a binary signal p representing the combination state of each value of the i-1st digit of the summand
and the difference p between the signal p and the intermediate sum (intermediate difference) s at the i-th digit by inputting the i-th digit of the addend, the i-th digit of the summand, and the signal p. -s, the sum p+s, or their logical negation, a second means for obtaining a binary signal u, and
The output signal q of the first means provided at the 1st digit and the i-1st digit and the i-2nd digit of the summand is input, and the signal p is
and the intermediate carry (borrow) k from the i-4th digit, a sum p+k or a difference p-k, or a binary signal v determined by their logical negation; A fourth means for obtaining a sum s+k of an intermediate sum (intermediate difference) s at the i-th digit and an intermediate carry (middle digit borrow) k from the i-1 digit by inputting only u and the signal v. An arithmetic processing device comprising: (2) For each digit of at least one of the addition (subtraction) number or the addend (subtraction) number, specifying a 1-bit binary signal representing the sign part of the digit and the magnitude of the absolute value of the digit. 2. The arithmetic processing device according to claim 1, wherein the arithmetic processing device is expressed by a 2-bit signal consisting of a bit binary signal.