JPS6349836A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To obtain a high-speed division processor that can be easily packaged into an LSI by forming a divider as a combination circuit of an array structure having a small number of elements and preventing the propagation of a digit carrying value. CONSTITUTION:The blocks 102-173 serve as redundant addition/subtraction cells between the SD expression number (redundant binary number) of a cardinal number 2. The partial residue deciding circuits consist of blocks 102-108 and blocks 111-118 respectively. While the blocks 81-88 serves as quotient deciding cells and decide the numerical values down to the 91st-98th decimal places of the quotient shown in the form of a redundant binary number with the output of each partial residue deciding circuit set at a higher stage used as the input. Then a block 90 supplies the digits 91-98 of the quotient Q shown in a redundant binary number and outputs rows z0-zn of the quotient shown in a binary number respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to high-speed arithmetic operations, and particularly to an arithmetic processing device suitable for increasing the speed of a divider having a cell array structure and implementing it into an LSI.

Conventional technology Conventionally, regarding high-speed dividers, the Journal of the Institute of Electronics and Communication Engineers,
Vol, J67-D, N0, 4 (1984)
As discussed on pages 460 to 457, E C
L (Emitter-Coupled-Logic
) is realized as a combinational circuit using four NOR10R elements. This divider circuit is superior to other dividers in terms of computation time and regular array structure, but there are some problems in terms of practical application, such as reduction in the number of elements and area, and implementation in other circuit systems (e.g., CMOS). was not taken into account.

Furthermore, dividers that have been put to practical use in the past have been realized as sequential circuits consisting of subtracters (adders) and chics, and are widely used. However, it is well known that these methods require an enormous amount of calculation time when the number of digits in the number of operations becomes large. On the other hand, in large-scale computers with high-speed multipliers, a multiplication-type division method is often used in which division is performed by repeating multiplication.

However, implementing this multiplication-type division method as a combinational circuit requires a huge amount of hardware, making it difficult to put it into practical use.

Problems to be Solved by the Invention Regarding high-speed dividers, the above-mentioned prior art proposes a method of realizing a subtraction-shift type divider as a combinational circuit by taking advantage of the feature of an ECL logic element that can perform NOR and OR at the same time. , reduction in number of tables.

There is no consideration given to practical implementation, such as implementation using MO8 circuits, etc. (1) As the number of digits in the number of operations increases, the number of elements becomes enormous, making it difficult to implement with a single LSI chip. (2) MO3 that cannot take NOR and OR at the same time
When realized with a circuit, OR is a NOR and an inverter.
There were problems such as a reduction in high-speed performance because the number of stages of the division circuit increased accordingly.

The purpose of the present invention is to improve these conventional problems, to realize a divider as a combinational circuit with an array structure and a small number of elements, to prevent the propagation of carry values, and to make the circuit configuration relatively simple. The object of the present invention is to provide a high-speed division processing device that is easy to implement in a large scale LSI.

Means for Solving the Problem The above purpose is to represent each intermediate remainder obtained by subtracting the divisor from the dividend in a subtraction-shift type divider as a signed digit representation number, and for each intermediate remainder X, A means for calculating the corresponding digit q of a signed digit representation number representing a quotient from an intermediate remainder A conversion means for converting to either a signed digit representation number (or binary number) or 0, and ■ Addition (subtraction) of a signed digit representation number and a signed digit representation number (or binary number) in which each digit is non-negative. ) by determining the intermediate remainder after determining the quotient digit q by inputting the intermediate remainder X and the output of the conversion means into the addition (subtraction) means; achieved.

action The subtractive shift type division method is generally expressed by the following recurrence formula.

R(j”)-rXR(])-qj partial dividend of,
H(j++) is the partial remainder (intermediate remainder) after determining qj. Therefore, for each index j of the recurrence formula, a quotient determination cell for determining the quotient qj and a partial remainder determination circuit for subtracting or not subtracting D from r x RCf) are provided according to the value of qj, and the combination is performed. It can be realized as a circuit. Furthermore, in internal calculations, each digit is represented by an element of ○, a positive integer, or a negative integer corresponding to the positive integer.
(signed digit representation) is used to represent the internal operation number.

Sum υ, each digit is (-1, 0, 1), (-2, -1).

0.1.2) or (-N,..., -1,0,1゜...,N), etc., and redundancy so that one number can be expressed in several ways. to hold.

As a result, it is possible to prevent propagation of borrow (carry) during subtraction (addition), and the parallel area (
Addition) can be performed in a fixed amount of time regardless of the number of digits in the operation number. For example, in the SD representation in which each digit is expressed as an element (-1, 0, 1), a carry (borrow) can be made to propagate only one digit at most during addition (subtraction). Regarding this matter, see Journal of the Institute of Electronics and Communication Engineers, Mo1. J67-D, N0
, 4 (1984), pages 450 to 467.

As described above, by using SD representation for internal calculations, a high-speed divider can be realized. At that time, for example,
Using a base-2 sn representation (i.e. redundant binary representation),
The floating point mantissa, that is, the unsigned binary number X with 1 bit integer part and n bits in decimal part, is expressed as
Each digit X is an element of (-1, 0, 1). in this case,
In the above recurrence formula, the divisor and each partial remainder R(li
) in radix-2 SD representation, depending on the value of q3,
When qj = 1, H (after shifting jl by one digit to the left, D
When qj=00, R6) is shifted one digit to the left, and when q]=1, Rfi) is shifted one digit to the left, and then D needs to be subtracted.

In the present invention, the conversion means uses a control signal determined from the quotient ql to convert the divisor or the divisor to either a 30-expressed number in which each digit other than the most significant digit is non-negative or 0, that is, the divisor is inverted. Dd determined as
), and the partial remainder is determined by the adding means as R(j+1)=2×R(j)+DO).

Therefore, by adding a simple circuit (that is, the conversion means) used for addition/subtraction or digit shift used to determine the partial remainder in division, an addition circuit for adding and subtracting or digit-shifting an sn-expressed number and a binary number or a 30-expressed number in which each digit is non-negative can be added. (that is, the addition means), it is possible to greatly reduce the amount of node hardware and simplify the circuit configuration in high-speed division processing of array structures.

Example An embodiment of the present invention will be described below with reference to the drawings.

In particular, in this embodiment, a subtraction-shift type divider for a normalized one-digit unsigned binary decimal point number will be described. however,
Hereinafter, binary means binary in two's complement representation.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 1 is a block diagram especially when n=s.

In the figure, the dividend [○, XlX2. ...Xn)z2o are signals X, 21, X222, . ...
, Xfi2B, the divisor [○, y1y2...yn
] 240 is the signal corresponding to the value of the first digit, second digit, ..., nth digit after the decimal point, respectively"!141+ 72421
..., 7n 48 is input to the divider, and the quotient CZa -21...Zn)z50 is the first integer digit, the first digit after the decimal point, ..., the value of the nth digit is the corresponding signal ZQ 60. It is output in the form of Z, 61 +”'Zn 6s.

Block 102. . . , 1 and 3 are cells for redundant addition and subtraction between a base 2 30 representation number (hereinafter referred to as a redundant binary number) and a binary number. Blocks 102,..., 1o
8, a circuit constituted by block 111.8. ...,
118, blocks 120, 12
1. ....

128, block 13Q.

131, . . . , 138.
The circuits constituted by blocks 170, 171, 172, and 173 are partial remainder determination circuits, and each calculates the output R(j) and the quotient of the partial remainder determination circuit of the upper stage (e.g., stage 2). After determining the first digit of the quotient from the one-digit value q3, the partial remainder H(j++) is determined.

Blocks 81, 82, 83. 87.88 are cells for determining the quotient, and the partial remainders Rg are the outputs of the partial remainder determining circuits in the upper stage (for example, the second stage).
As input, the third decimal point of the quotient expressed in redundant binary
Determine the value of the digit q, which is 991°92, 93, . . . 9, 98.

The block 90 is a redundant binary/binary converter, and each digit 91, 92°93, . . . , 9 of the quotient q expressed in redundant binary
Enter 7.98 and write each digit of the quotient in binary ZQ60. Z
161. ..., zn ea This redundant binary/binary converter 90 outputs the quotient Q from the unsigned binary number Q+ in which only the digits that are 1 in the redundant binary representation quotient Q are set to 1. Unsigned binary number Q- with only the digits that are -1 set to 1
This is a circuit that performs the subtraction of , and can be easily realized using an ordinary sequential carry adder or carry lookahead adder.

Note that in Figure 1, n/2<
This is an example in which, for an integer j in the range of j≦n−1, redundant addition/subtraction cells after 2x(n−j+1) digits below the decimal point are omitted in the C-th partial remainder determination circuit. Also, the partial remainder determination circuit 1o2 at the top stage. . . , 107 and 108 are circuits for determining redundant binary numbers whose digits correspond to subtracted values for each digit in subtraction between binary numbers.

Next, redundant addition/subtraction cells 111, 112, 113°・
..., 173 will be explained.

Now, j digits below the decimal point qj of the quotient and partial remainder Rd)
has already been determined, the partial remainder after determining qj is determined by the following recurrence formula.

1(j+1):2 X Ret)+ω) However, (0
, 7+7z...yn] It takes advantage of the fact that the sign of 2 can be inverted by taking two's complement.

In the recurrence formula, 2 x Rc)) is found by shifting Ro) by one digit to the left. When qj=1, H
a), 7) Decimal cylinder i + 1 digit r (++ and 71
When qj=O, redundant addition between 'L+ and O. When qj=1, redundant addition between rj and 7i is performed for each digit i, υ, R(j+1 ) = (r 1 rj, ++ , j, '+l
, , ・rj ++ )5.2 is found. however,
The redundant binary number is written as []5D2.

In addition, in order to realize the addition in which the carry propagates only one digit in the redundant addition between the redundant binary numbers and the binary numbers, the intermediate sum is determined according to the rules shown in Table 1, and the intermediate carry is determined according to the rules shown in Table 2. You can decide accordingly. Hereinafter, addition of redundant binary numbers and binary numbers is performed according to this addition rule.

Table 1 Table 2 Further, in this embodiment, redundant binary numbers are converted into binary signals as follows.

1 digit r3 of the redundant binary number representing the remainder number is 2 bits rj
rj, -1 is 11, 0 is 10.1 is
It is expressed as a 2-bit binary signal of 1aol. Furthermore, the one-digit qJ of the redundant binary number representing the quotient is represented by a two-bit (2-bit) q'q leap, and -1 is expressed as 01, 0 as 00, and 1 as a 2-bit binary signal of 10.

At this time, the i-th digit d of the second term Dd) of the recurrence formula,, intermediate sum S! and intermediate carry are each 1
Engineering d, = q+・′; i+9 yen・ye.

s4=13. (It can be determined by the logical formula pdj 1 1+la l. Also, the final sum, j−z, is rj+1
=S-! +Cj 1S 1 1+1rj” = S
It is given as a 2-bit signal expressed as 1+1. However, i is from 1 to n-1
is an integer up to . Also, r3+1 and decimal point cylinder n
The intermediate carry C in the digits is given by the following logical expressions: *L=q=i+7n r6v=(q4+q ahead)*7n Cj=ql. Furthermore, Sj, r−I+1 is
Sl = rjlae) q"j-rj+':
It is given by the logical formula 3j @ oj Oa 0 1. In the above logical formula, ・ is the logical product (AND
), + stands for logical sum (OR), and ■ stands for exclusive disjunction (EX
-OR) is the logical negation of .

FIG. 2 shows redundant addition/subtraction cells 111, . . ., fist, 117, 121, . . ., 12a, 131, . -..., 137, 171゜172, 173
FIG. 2 is a circuit diagram showing an example of the configuration.

In the figure, gate 211 is an inverter circuit, gate 212 is an AND-NOR composite gate, and gate 231 is an 0R-HA
ND composite gate, gates 232°252 are exclusive NOR
The circuit and gate 251 are N-person ND circuits. Moreover, the signals q'201 and +q ahead 202 are the first decimal place q of the quotient in FIG.
2-pit signal representing j 91, 92. ....

Or either 97. rj, 203
engineering+18 and r 204 is the quotient below the decimal point j-11÷
1a Decimal column 1 of partial remainder after digit qj-1 is determined
+1 is a 2-bit signal representing digit r, +I, and 7i
206 is a 1-bit signal 4 representing the first digit below the decimal point of the divisor
1,42. ..., any of 47, y1206
is a signal representing its logical negation. Signal a''4221 is a 1-bit signal representing the first decimal place of the addend Dd), C-1241 is a 1-bit signal representing an intermediate carry in the first decimal place, and 5i242 is an intermediate sum in the first decimal place. 1 via) signal, Cj,
243 is a 1-bit signal representing an intermediate carry from the decimal column i, +1 digit to co+1. Also, output signals -5r, 261 and r4+1262 are quotients.
This is a 2-bit signal representing the first decimal place ri+1 of the partial remainder after determining the first decimal place qj of j−z is La.

In FIG. 2, the redundant binary number and the binary number addition circuit include an inverter circuit 211, an exclusive NOR circuit 232.0R-
It is composed of a NAND composite gate 231, a NAND circuit 251, and an exclusive N0F1 circuit. In particular, the intermediate carry Cj is determined by the OR-NAND composite gate 231, and the logical negation ij of the intermediate sum S:i is determined by exclusive NO.
The R circuit 232 and the inverter circuit 211 determine the final sum 2-bit signal rj+1261 from the signal Si 242 representing the intermediate sum and the intermediate carry Cj 243 from the lower digits.
The circuit that outputs a, r-, "262 is composed of a NANDa circuit 261 and an exclusive NOR circuit 262. Also, the first decimal place Yi of the divisor is determined by the value of the first decimal place of the quotient. The means for converting yi, 0°7i is realized by a composite gate 212 that executes AND-NO!'.However, i is limited to the range from 1 to n-1.

FIG. 3 shows each redundant addition/subtraction cell 120, 130 . . . of the most significant digit in FIG. ---. 170 is a circuit diagram illustrating an example of the configuration of 170. FIG. In the figure, gates 311, 312 and 313 are inverter circuits, gate 352 is an exclusive N0F1 circuit,
Gate 361 is a HAND circuit, gate 332 is an exclusive O
This is an R circuit. Also, an n-channel transistor 321
and p-channel transistor 322, and n-channel transistor 323 and p-channel transistor 32.
4 respectively constitute a transfer gate.

Signal q'201 is the same signal as in FIG. r' 301 is a 1-pit signal representing the sign part of the S2 focus signal representing the most significant digit r-inclusion of the partial remainder;
rj 302 is 1 representing the magnitude of the 2 pit signals representing the 1 digit rj of the decimal point cylinder a of the partial remainder.
This is a bit signal, and r-1303 is a 1-bit signal representing the sign part of the 2-bit signal representing the second decimal place r32 of the remainder of the partial sequence 2S. Also, Cj343
is a 1-bit signal representing the intermediate carry from the first digit after the decimal point. This is a 2-pit signal representing digits rj and -z.

In Figure 3, since yo is always 0, the addend Do)
The most significant digit of is d3=qj, and the intermediate sum is 0.
+ Determined by the exclusive OR circuit 332 and the inverter circuit, the magnitude of the most significant digit; '362 is the exclusive N of FIG.
Similar to the OR circuit 252, the determination is made using an exclusive NOR circuit.

Further, the sign part 'o;' of the most significant digit needs to be determined so that the second integer part rj++ of the partial remainder after determining ql is always 0.

Therefore, the highest digit sign part rj+1 is determined by the NOR circuit 351. as shown in FIG. 3S. Inverter circuits 311 and 312. ) A circuit consisting of transfer gates 321 and 322 and transfer gates 323 and 324 generates partial remainder RL before qj determination: J)
It is determined from the upper three digits of υ, j, j, 0' 1 and rj, and the fifth digit after the decimal point of the quotient, qD.

FIG. 4 is a circuit diagram showing a configuration example of each of the redundant addition/subtraction cells 118, 128, and 138 of the least significant digit in FIG. In the figure, gates 412 and 452 are NOR circuits, and gate 451 is a NAND circuit, which is the same as the one in FIG.
It is a pit signal, yn401 is a 1-bit signal 48 representing the first digit below the decimal point of the divisor in FIG. 1, and yy
1402 is a signal representing its logical negation. output signal r
j−z461 and rj+”462 are the lowest digit rj−+ of the partial remainder after determining the ja digit qj below the decimal point of the quotient.
This is a 2-bit signal representing -+.

In Figure 4, the size rj++ of the least significant digit rj+1 of the partial remainder after determining the fifth digit qj after the decimal point of the quotient.
n na 462 is determined by the NOR circuits 412 and 452, and the sign part r4;'461 of the least significant digit r-1'' is determined by the NAND circuit 451. Also, the intermediate carry C from the least significant digit -I is the least significant digit 7n of the divisor
is equal to q4201 regardless of . If there is a sign inversion of the divisor, the chain becomes C, Ll, and in other cases, the chain becomes 0.

Next, the quotient determination cell 81, 82, 83° in Fig. 1...
, 87.88 will be explained.

Each digit q) of the quotient is the upper three digits (rj, rj
It is determined by the values of rj and 1so2. In other words, H(
If the top three digits of j) are negative, then q・-1, and if Q, then q:l=0
, if both are positive, it is determined that q,=1. Therefore, the above redundancy 2
When binary encoding is used, the first digit after the decimal point of the quotient is q
can be determined by the logical formula: (r'-J-r'+r)0Δ+2L28.

FIG. 5 shows each quotient determination cell 81, 82, . . . in FIG. 1.
83. ..., 87.88 is a circuit diagram showing an example of the configuration. In the figure, gate 511 is an inverter circuit, gate) 51
2, 513, 514 and 532 are NOR circuits, and gate 531 is an 0R-NAND composite gate. Also signal r
j 501 and 604 are the first decimal place r3 of HCi), and the second decimal place rj of 2-pi R(li).
A 2-bit signal representing the quotient, which is a redundant binary number, is a 2-bit signal representing the third digit after the decimal point, and the signal in FIG. . Also, q4201 is the third digit after the decimal point of the quotient q
q'L202 indicates whether j is 1 or not, and q'L202 indicates whether qj is -1.

Note that the exclusive OR circuit in the figure of this embodiment can be replaced with an exclusive NOR circuit by combining it with an inverter in various ways, NAND can be replaced with NOH by combining it with an inverter, the composite gate can be replaced with N[) or NOH. It is known that a switching circuit such as the composite gate 212 of FIG. 2 can be easily constructed with a transfer gate as shown in FIG. 3, or vice versa.

Further, the redundant addition/subtraction cell shown in FIG. 2 requires 32 transistors when exclusive NOR of 6 transistors is used, and the number of gate stages of the critical bus becomes 3 gate stages. Further, the quotient determination cell in FIG. 6 has 38 transistors, and the number of gate stages of the critical bus is 2 gate stages.

In the above embodiment, in particular, the subtraction shift type divider is CMOS
Although the circuit was realized using binary logic, the present invention is also applicable to other technologies (for example, NMO3).

This can be easily realized using EOL, TTL, IIL, etc.) or multi-value logic.

According to this embodiment, by configuring the divider with a 0M03 circuit, the delay required for the calculation of a single digit quotient is about 6 gates, and the basic cell is composed of about 30 transistors. Since it can be realized as a combinational circuit with a regular arrangement structure of about 50 transistors for quotient determination cells, compared to a conventional subtraction-shift type divider using sequential carry adders, the number of transistors reduces the calculation time (gates). When dividing by 32 bits, the number of stages is approximately 12.
1.64 bits is approximately 1/24, and the number of transistors is approximately half that of a conventional subtraction/shift type divider using redundant binary adders/subtractors.

Therefore, it is effective in reducing the number of circuit elements of the divider, making it easier to implement into an LSI, and increasing the speed.

Effects of the Invention According to the present invention, a redundant addition circuit between a signed digit representation number and a binary number (two's complement representation) that allows a negative value for each digit can be used for addition/subtraction or digit shift that occurs in the internal operation of division. It is possible to realize a combinational circuit using only one of the redundant subtraction circuits, and it is possible to ensure that the carry or borrow of each digit in addition and subtraction is propagated to at most one digit. (1) The number of elements in the arithmetic processing unit (2) Additions and subtractions can be processed at high speed in a fixed amount of time regardless of the number of digits, so the speed of the arithmetic processing device can be increased, (3) The circuit configuration can be relatively simplified, and (4) There are effects such as the ability to easily and economically convert the processing device into an LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the middle digit redundant addition/subtraction cell in FIG. 1, and FIG. 4 is a circuit diagram showing an example of the configuration of the redundant addition/subtraction cell for the most significant digit. FIG. 5 is a circuit diagram showing an example of the configuration of the redundant addition/subtraction cell for the lowest digit in FIG. 1. FIG. 2 is a circuit diagram showing an example of a configuration of a decision cell. 90...Redundant binary/binary converter, 81-88.
...Cell for quotient determination, 102-173...Cell for redundant addition and subtraction, 2o...Dividend, 21-28.
... Dividend digit, 40 ... Divisor, 41 to 4
8...divisor digit, 5Q...quotient, 6Q~6
8... Quotient digit, 91-98... Quotient digit in redundant binary representation. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 pJ iJ 7-J OS direct 2s Figure 4 r, r 2' Figure 5

Claims (2)

[Claims] (1) In a subtraction-shift type division processing device that uses a signed digit representation number in which each digit is a positive, 0, or negative value for internal calculations, each intermediate remainder obtained by subtracting the divisor from the dividend is Expressed as a signed digit representation number, each digit q of the quotient of the signed digit representation from each intermediate remainder X
and a means for determining the divisor Y by the value of each digit q of the quotient.
is either a signed digit representation number with the same value and each digit is non-negative (non-positive), or a signed digit representation number with the value -Y and each digit is non-negative (non-positive), or 0. and a means for adding (subtracting) a signed digit representation number and a signed digit representation number in which each digit is non-negative (non-positive), An arithmetic processing device characterized in that each intermediate remainder after determining each digit q of the quotient is determined by inputting the output to the addition (subtraction) means. (2) The arithmetic processing device according to claim 1, wherein the signed digit representation in which each digit is non-negative is expressed as a binary representation.