JPH061436B2 - Processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic operation processing device, and more particularly to a high-speed operation processing device that includes addition / subtraction or positive / negative sign inversion for internal operation and is suitable for LSI implementation.

2. Description of the Related Art Conventionally, for example, with regard to high-speed multipliers, the Institute of Electronics and Communication Engineers, Vol. J66-D, No. 6 (1983) No. 68
Pp. 3 to 690, and the high-speed divider is described in The Institute of Electronics and Communication Engineers, Vol. J67-
D, No. 4 (1984) pp. 450-457. These are the digits {-1, 0,
Redundant binary expression represented by 1} element (a kind of extended SD expression)
Is an arithmetic unit that executes multiplication or division by a combinational circuit using the. Therefore, although it is superior to other arithmetic units in terms of arithmetic processing time and regular array structure, no consideration was given to practical use such as reduction of the number of elements and area.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the above-mentioned conventional technology, there has been proposed a method for realizing a combination circuit such as multiplication or division by taking advantage of the features of an ECL logic element capable of simultaneously taking NOR and OR. Practical aspects such as reduction of the number of elements and realization by other circuit systems are not considered so much. (1) When the number of digits of the number of operations increases, the number of elements becomes enormous,
It is difficult to realize with one LSI chip.

(2) When realizing a NOR circuit and a MOS circuit that cannot take an OR at the same time, it is necessary to configure the OR with two stages of elements, NOR and an inverter, which increases the number of stages of the arithmetic circuit. Time increases.

There are problems such as.

An object of the present invention is to improve such conventional problems, to realize an arithmetic processing device as a combinational circuit having an array structure and a small number of elements, minimize propagation of a carry value, and simplify the circuit configuration. The object of the present invention is to provide a high-speed arithmetic processing device that can be easily mounted on an LSI by implementing the above-mentioned processing.

Means for Solving Problems The above-mentioned object is that each digit is positive in the internal arithmetic number of the arithmetic processing unit.
Using a signed digit (that is, SD) number (base n) that can take either 0 or a negative value, for each signed digit number Y in which each digit other than the most significant digit is non-negative (or non-positive), (a) Sign reversal (or most significant digit size) of the complement of the most significant digit size of the number Y of signed digits (that is, the complement of n−1, where the one's complement is equivalent to logical negation). (B) each non-negative (or non-positive) digit other than the most significant digit of the signed digit number Y is complemented by the magnitude of that digit (or its digit). Second inversion of the complement of the magnitude of
(c) It is achieved by providing a sign reversing means having a third means for adding a correction term to the least significant digit of the signed digit number Y.

Operation For example, in internal arithmetic, the number of internal arithmetic is calculated using extended SD (Signed Digit) representation, that is, each digit is represented by 0, a positive integer, or a negative integer corresponding to the positive integer, that is, a signed digit representation. Represents

That is, each digit is {-1, 0, 1}, {-2, -1, 0,
1,2} or {-N, ...,-1,0,1, ...,
It is represented by any element such as N} and has redundancy so that one number can be expressed in any number. At that time, the intermediate carry (or intermediate borrow) and the intermediate sum (or intermediate difference) are the intermediate sum (or intermediate difference) of the digits even if there is a carry (or borrow) from the lower digit. Sum (or difference) with carry (or borrow) from the lower digit of
It is possible to determine the intermediate carry (or intermediate borrow) and the intermediate sum (or intermediate difference) of that digit so that each is always within one digit. Thereby, propagation of carry (or borrow) in addition (or subtraction) can be prevented, and parallel addition (or subtraction) by combinational circuit
Can be performed in a fixed time regardless of the number of digits in the calculated number. For example,
In the extended SD representation (that is, redundant binary representation) in which each digit is represented by an element of {-1, 0, 1}, carry (or borrow) at addition (or subtraction) does not propagate at most one digit. Can be Regarding this, the Institute of Electronics and Communication Engineers, Vol. J67-D, No.4 (198
4th year) From page 450 to page 457 or IEICE Transactions, Vol. J66-D, No. 6 (1983), pages 683 to 690, etc.

In addition, in operations such as multiplication, division, addition and subtraction, addition of an extended SD expression number (for example, redundant binary expression number) and an extended SD expression number (for example, binary expression number) where each digit is non-negative (or non-positive) or The circuit configuration can be simplified by using many subtractions. However, the most significant digit may be negative (or positive).

In the following, in particular, the augend (subtraction) is the redundant binary number X,
Addition or subtraction in which the addition (subtraction) number is the binary number Y and the addition number or the subtraction number (that is, the operation result of addition or subtraction) is the redundant binary number will be described.

In the addition rule of redundant binary number and binary number, the carry propagates only one digit, the intermediate sum is determined according to the rule shown in Table 1, and the intermediate carry is determined according to the rule shown in Table 2.

In the present invention, the redundant binary number Y = [y _n-1 , y _n-2 ... Y ₁ y ₀ ] _{SD2 in} which the most significant digit is non-positive and all other digits are non-negative.
Alternatively, a binary number in 2's complement notation Y = [y _n-1 , y _n-2 ...
The sign inversion of y ₁ y ₀ ] ₂ , that is, -Y, is a redundant binary number [w _{n-1 n-2} ..., Each digit other than the highest digit obtained by the first means and the second means is non-negative. ... _{1 0] SD2,} by adding 1 by the third means, can be expressed as _{[w n-1 n-2 ......} 1 0 ] _SD2 +1. However, w _n-1 has y _n-1 of 1 or -1.
Is 0, and when y _n-1 is 0, it is -1. That is, w _n-1 − | y _n-1 | . Further, _i means the logical negation of y _i (that is, 0 if 1 and 1 if 0), and | y
_n-1 | means the absolute value of y _n-1 .

Therefore, subtraction of X and Y be expressed in the form of the addition of -Y, logical NOT meiotic subtraction x _i -y _i of each digit and minuend x _i
It can be expressed in the form of addition with _i . That is, the subtraction can be performed by the adder circuit by taking the logical NOT of each digit of the subtraction.
However, it is necessary to perform exceptional processing or correction for the highest digit and the lowest digit. Accordingly, the addition and subtraction of the redundant binary number and the binary number can be executed by the addition circuit of the redundant binary number and the binary number, and the circuit configuration can be simplified, so that the high-speed arithmetic processing device can be easily implemented as an LSI.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic circuit diagram of a basic arithmetic circuit corresponding to one digit of addition and subtraction as an internal arithmetic, which constitutes an arithmetic processing unit of an embodiment of the present invention. In particular, FIG. 1 shows a circuit that executes addition and subtraction according to the value of the control signal q. When q = 0, addition is performed, and when q = 1, subtraction is performed. In other words, it is a circuit in the portion corresponding to one digit of the operation represented by the formula Z = X + Q (Y). However, X in the first term of the above equation is a redundant binary,
Y in the term is redundant 2 where each digit other than the most significant digit is non-negative
It is a base number, and Q (Y) = Y when q = 0 and Q (Y) = − Y when q = 1. First, the sign inversion function Q (Y) will be described before explaining FIG.

The above equation is the addition of the redundant binary number X and the redundant binary number Y in which each digit other than the most significant digit is non-negative when q = 0.

When q = 1, that is, the same addition circuit is used for subtraction between X and Y, and in order to simplify the circuit configuration, Q (Y) is always other than the most significant digit (that is, regardless of the value of q). Each digit of must be a non-negative redundant binary number. Here, since the expression conversion between the non-negative redundant binary number other than the most significant digit and the binary number of the two's complement display can be easily performed, Y is treated as the binary number of the two's complement display.

For simplicity, both X and Y are n-digit integers. That is, X = [x _n-1 ... X ₁ x ₀ ] _SD2 , Y = [y _n-1 ...
y ₁ y ₀ ] ₂ . However, the redundant binary number is [] _SD2 ,
The two's complement notation is expressed in binary notation [] ₂ .

They are and Means However, y _n-1 can be a sign bit and can be 0 when the number has no sign bit. First, if Y is positive, that is, when the y _n-1 = 0, _[n-2 ...... _{1 0] SD2} +1 is Which means Becomes In the above formula Therefore, the above formula is Next, -Y = _[n-2 ...... _{1 0] SD2} understood to be a +1. However, means -1 and _i
Means the logical negation of y _i . Further, when Y is negative, that is, when y _n-1 = 1, −Y is −Y = [0 _n-2 ... ₁ , ₀ ] ₂ +1 by the two's complement notation in the binary number. If this is a redundant binary representation, -Y = intact _{[0 n-2} ...... _1, 0] _SD2 +1 and expressed. In other words, the sign inversion of the Y in the redundant binary scheme, -Y = - expressed in _{[(n-1) n-2} ...... 1 0 ] _SD2 +1, the first term on the right-hand side is the digit other than the uppermost digit It is a non-negative redundant binary. Therefore, the addition formula is as follows: (I) When q = 0, [z _n z _n-1 ... Z ₀ ] _SD2 = [x _n-1 x _n-2 ... X ₁ x ₀ ] _SD2 + [y _{n-1 y n-2 ......} y 1 y 2 ] _2, (II) when q = 1, _{[z n z n-1 ...... z} 0 ] _SD2 = _{[x n-1 x n-2} ...... It can be expressed as x ₁ x ₀ ] _SD2 + [0 _n-2 ...... _{1 0} ] ₂ + [( _n-1 ) 0 ... 00] _SD2 +1. However, redundant binary numbers are indicated by [] _SD2 , and binary numbers in 2's complement notation are indicated by [] ₂ . Hereinafter, FIG. 1 shows a circuit for performing the operation from the first digit to the ( _{n−2) th} digit of one of the above two equations according to the value of the control signal q, and FIG.
FIG. 3 shows a circuit for performing the calculation of the most significant digit of one of the above two equations, that is, the _n- 1th digit, according to the value of the control signal q.
It shows a circuit for calculating the least significant digit of one of the above two equations, that is, the 0th digit, according to the value of the control signal q.

Next, description will be made on the binary signalization of the redundant binary number in the embodiment of the present invention.

One digit x _i or z _i of the redundant binary number is represented by a 2-bit signal ▲ x ^s _i ▼ ▲ x ^a _i ▼ or ▲ z ^s _i ▼ ▲ z ^a _i ▼, and -1 is 11, 0 is 10, 1 Is represented by 01 and a 2-bit binary signal. At this time, the i-th item of the second term Q (X) of the above equation
The digit d _i , the intermediate sum s _i , and the intermediate carry c _i are respectively d _i = qy _i , s _i = ▲ x ^a _i ▼ d _i , c _i = ▲ ^s _i ▼ + ▲ ^a _i ▼ ・ d _i Can be determined by the logical formula. The final sum z _i is given by a 2-bit signal represented by ▲ z ^s _i ▼ = s _i + _i-1 , and ▲ z ^a _i ▼ = s _i c _i-1 . Where i is 1
_Is an integer from to _n-1 . Z _n is also _{^{▲ z s n ▼ = ▲ x}} s n-1 ▼ + d n-1, ▲ z a n ▼ = ▲ x s n-1 ▼ · ▲ x a n-1 ▼ · d n-1 + s _n-1
It is given by a 2-bit signal represented by _n-1 , and z ₀ and carry c ₀ from the 0th digit are respectively ▲ z ^s ₀ ▼ = (y ₀ + ▲ x ^s ₀ ▼) ・ ( ₀ + ▲ ^s ₀ ▼ ＋ ▲ x
^a ₀ ▼), ▲ z ^a ₀ ▼ = ▲ x ^a ₀ ▼ y ₀ , c ₀ = ▲ x ^s ₀ ▼ · y ₀ + q · ₀ . In the above logical expressions, · is a logical product (AND), + is a logical sum (OR), is an exclusive logical sum (E _x −OR) ▲ ^s _i ▼, _i-1 is ▲ x respectively.
It is an operator that represents the logical negation of ^s _i ▼ and c _i-1 .

FIG. 1 is a circuit diagram showing an arithmetic circuit for intermediate digits in addition and subtraction which constitutes the present embodiment by the above-mentioned binary signal conversion. In the figure, gates 111 and 152 are exclusive NOR circuits, gate 132 is an exclusive OR circuit, gate 151 is a NAND circuit, and gate 131 is an OR-AND composite gate.
The signal q100 is added (when q = 0) but subtracted (q = 0).
= 1), the control signal for controlling whether or not ▲ x ^s _i ▼
101 and ▲ x ^a _i ▼ 102 are the i-th of the redundant binary number X.
A 2-bit signal representing a digit, y _i 103 is a bit signal representing the i-th digit of a binary number (or a non-negative redundant binary number) Y, and _i 111 is a first digit d _i of the addend Q (Y). Logical negation, c _i 141 is a 1-bit signal indicating the intermediate carry at the i-th digit, _i 142 is a 1-bit signal indicating the logical negation of the intermediate sum s _i at the i-th digit, and c _i-1 143 is the i _-th signal. A 1-bit signal indicating an intermediate carry from -1 digit, and ▲ z ⁱ _s ▼ 161 and ▲ z ^a _i ▼ 162 are 2-bit output signals representing the i-th digit of the operation result Z.

In FIG. 1, the adder circuit of the redundant binary number X and the binary number Q (Y) is an OR-NAND composite gate 131, an exclusive OR.
The circuit 132, the NAND circuit 151, and the exclusive NOR circuit 152 are included. In particular, the intermediate carry c _i
Make decisions by OR-NAND composite gate 131, to determine the logical negation _i of intermediate sum s _i an exclusive OR circuit 132, a signal representative of the intermediate carry from the signal 142 and the lower digit represents the intermediate sum c _{i- The circuit} that inputs ₁ 143 and outputs the final sum 2-bit signals ▲ z ^s _i ▼ 161 and ▲ z ^a _i ▼ 162 is a NAND circuit 151 and an exclusive NOR circuit 15
It is composed of two. In addition, the logical negation of the intermediate digit (that is, the first digit to the (n−2) th digit) is controlled by the control signal q to invert the positive / negative sign of the binary number or the non-negative redundant binary number Y.
The exclusive NOR circuit 111 realizes the means for performing the operation according to the value of.

That exclusive NOR circuit 111, when _{q = 0, i = 0y i} , i.e., d _i = y _i, when q = 1, _i = 1y _i i.e., operates as d _i = _i. However, 0y _i = y _i and 1 + y _i = _i can be easily inferred.

FIG. 2 is a schematic circuit diagram showing the arithmetic circuit of the most significant digit in addition and subtraction which constitutes the present embodiment.

In the figure, gates 211, 252 are exclusive NOR circuits, gate 232 is an exclusive OR circuit, and gates 202, 203, 2
31 is an inverter circuit, and gates 251 and 253 are NAN.
The D circuit and gate 254 are OR-NAND composite gates.

Further, the control signal q100 is the same signal as that of FIG. 1, the signal _{^{▲ x s n-1 ▼ 201}} , ▲ x a n-1 ▼ 202, y n-1
203, _n-1 221, _n-1 242, cn _-2 243, ▲
z ^s _n-1 ▼ 261 and ▲ z ^a _n-1 262 are signals ▲ x ^s _i ▼ 101, ▲ x ^a _i ▼ 102, respectively in FIG.
y _i 103, _i 121, _i 142, c _i-1 143, ▲ z
^{In s} _i ▼ 161 and ▲ z ^a _i ▼ 162, i = n−
The signal is the same as when it is set to 1. Further signal ▲ z ^s _i ▼ 2
In 63, ▲ z ^a _n 264 is a 2-bit output signal representing the nth digit of the operation result Z.

In FIG. 2, the exclusive OR circuit 232 determines the logical negation _n-1 of the intermediate sum s _i , and the NAND circuit 251 and the exclusive NOR circuit 252 output the signal _n-1 24 representing the intermediate sum.
2 and the signal c _n-2 243 representing the intermediate carry from the lower digit, the 2-bit signal ▲ z ^sn _-1 ▼ 261 and ▲ z ^a _n-1 ▼.
262 is a circuit for determining. The exclusive NOR circuit 211 implements a logical NOT of the most significant digit of Y (that is, the (n-1) th digit) according to the value of the control signal q. The operation is similar to that of the exclusive NOR circuit 111 shown in FIG.

Also, when adding to the logical negation _n-1 of y _n-1 negated, even if adding the y _n-1 as it is, the value of the intermediate sum s _n-1 are the same, y _n- effect of sign inversion of the logical negation _n-1 of ₁ extends only to the n-digit of the operation result. Therefore y
_The means for performing the sign inversion of the logical negation _n-1 of _n-1 is the n-1th
A NAND circuit 253, an OR-NAND composite gate 254, and inverter circuits 202, 203, and 231 are used in combination with a circuit that determines the intermediate carry of a digit. In other words, the circuit formed by them has d _n-1
= 0, x _n-1 = 1 then x _n = -1, and d _n-1 = 1,
If x _n-1 = -1, then z _n = -1, otherwise z
It operates so that _n = 0.

FIG. 3 is a schematic circuit diagram showing the arithmetic circuit of the least significant digit in addition and subtraction which constitutes the present embodiment. In the figure, gate 31
1, 312, 313, and 314 are inverter circuits, a gate 321 is an OR-NAND composite gate, and a gate 322.
Is an AND-NOR composite gate and gate 323 is an exclusive O
It is an R circuit.

The control signal q100 is the same signal as that shown in FIG.
x ^s ₀ ▼ 301 and ▲ x ^a ₀ ▼ 302 are the redundant binary numbers X
Is a 2-bit signal representing the 0th digit of y, y ₀ is a 1-bit signal representing the 0th digit of Y (or a non-negative redundant binary number), and c ₀ 331 represents an intermediate carry at the 0th digit. It is a 1-bit signal. Furthermore, ▲ z ^s ₀ ▼ 332 and ▲ z ^a ₀ ▼ 33
Reference numeral 3 is a 2-bit signal representing the 0th digit of the operation result Z.

Here, the logical NOT of the least significant digit of Y (that is, the 0th digit) is ₀
When adding 1, when the y ₀ = 0, when _{0 + 1 = 1 × 2 +} y 0, y 0 = 1, 0 + 1 = 0 × 2 + y 0, . Therefore, even not be negated the Y Least significant digit y
₀ does not change. Further, in that case, the sign inversion of Y affects the intermediate carry, and a carry occurs when q = 1 and y ₀ = 0.

Therefore, in FIG. 3, the composite gate 322, the exclusive OR circuit 323, and the inverter circuits 312, 313 are shown.
314 and half of the composite gate 321 (that is, the inverter 3
A circuit constituted by the output of 12 and the NOR circuit which receives the signal 301) is an addition circuit of the least significant digit when the sign inversion of Y is not performed. The means for adding 1 to the least significant digit according to the value of the control signal q100 is the composite gate 32.
1 and an inverter circuit 311. That is, this circuit operates so that when q = 1 and y ₀ = 0, the intermediate carry c ₀ = 1 of the least significant digit.

The exclusive OR circuit in the drawing of this embodiment is replaced with an exclusive NOR circuit by various combinations with an inverter, a NAND is combined with an inverter and replaced with NOR, and a composite gate is formed by a combination of NAND and NOR. It is known that one can easily do this or vice versa. Further, the switching circuit such as the composite gate 321 in FIG. It is also possible to use a gate.

Further, the arithmetic circuit of FIG. 1 has an exclusive O of 6 transistors.
If the R, exclusive NOR circuit is used, there are 28 transistors, and the number of gate stages in the critical path is 3.

In the above embodiments, especially, the binary binary sign inversion in which each digit is non-negative is realized by the binary logic in consideration of the CMOS circuit as a part of the arithmetic processing of addition and subtraction. It can be inferred that it can be easily applied to the sign inversion of a non-positive redundant binary number. In addition, the present invention provides other technologies (eg,
It can be easily realized by using NMOS, ECL, TTL, IIL, etc.) or multi-valued logic.

According to the present embodiment, the delay required for executing a basic operation such as addition and subtraction of a redundant binary number and a binary number is uniformly 3 gate stages regardless of the number of digits of the operation number. 1
The circuit corresponding to one digit is composed of about 30 transistors.

Therefore, the divider composed of the combinational circuit of the regular array structure of the basic arithmetic circuit has about half the number of transistors and the calculation time (compared with the conventional subtraction shift type divider having the array structure of the sequential carry adder). Number of gate stages)
In the case of 32 bits division, about 1/12 and 64 bits division results in about 1/24.

That is, L of the reduction of the circuit elements of the arithmetic processing device such as the divider
This is effective in facilitating SI and speeding up.

Advantageous Effects of Invention According to the present invention, it is possible to use a positive value for each digit in the internal calculation of the arithmetic processing unit.
When adding or subtracting using the number of signed digit representations that allow 0 or negative values, all but the most significant digit are non-negative (or non-positive)
Since it is possible to represent the sign inversion of the signed digit representation number of, as a non-negative (or non-positive) signed digit representation number other than the same most significant digit as the original, (1) element of arithmetic processing unit The number can be reduced, and (2) the addition and subtraction can be processed at high speed in a fixed time regardless of the number of digits, so the speed of the arithmetic processing unit can be increased, and (3) the circuit configuration can be relatively simplified, (4) There is an effect that the LSI of the arithmetic processing device can be easily and economically realized.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram showing an arithmetic circuit of an intermediate digit in addition and subtraction which constitutes an embodiment of the present invention, and FIG. 2 is a schematic circuit diagram which shows an arithmetic circuit of a most significant digit in addition and subtraction which constitutes an embodiment of the present invention. FIG. 3 is a schematic circuit diagram showing an arithmetic circuit of the least significant digit in addition and subtraction which constitutes an embodiment of the present invention. 132, 232, 323, ... Exclusive OR circuit, 11
1, 152, 211, 252 ... Exclusive NOR circuit, 1
51, 251, 253 ... NAND circuit, 202, 20
3, 231, 311, 312, 313, 314 ... Inverter circuit, 131, 254, 321 ... OR-NAN
D composite circuit, 322 ... AND-NOR composite circuit.

Claims (6)

[Claims] 1. A signed digit number Y in which each digit other than the most significant digit is non-negative (or non-positive) is input, the sign of the signed digit number Y is inverted, and each digit other than the most significant digit is non-negative ( Or a non-positive) sign reversal means for generating a signed digit number, the sign reversing means comprising: (a) sign reversal (or most significant digit) of the complement of the most significant digit of the signed digit number Y; The complement of the size of
(B) Each non-negative (or non-positive) digit other than the most significant digit of the signed digit number Y is complemented by the magnitude of the digit (or complemented by the magnitude of the digit). Of the signed digit number Y, and (c) third means for adding a correction term to the least significant digit of the signed digit number Y. 2. A third means adds the correction term 1 (or -1) to the least significant digit of the signed digit number Y in which each digit other than the most significant digit is non-negative (or non-positive). The arithmetic processing unit according to claim 1. 3. The arithmetic operation according to claim 1, wherein the radix of the number of signed digits is 2, and the complement of the magnitude of each digit is the logical negation of the magnitude of each digit. Processing equipment. 4. The arithmetic processing unit according to claim 1, wherein the sign inverting means inputs a binary number Y. 5. A non-negative (or non-positive) radix-2 signed digit number Y with each digit other than the most significant digit is input, and the signed digit number Y is sign-inverted to obtain each digit other than the most significant digit. Is provided with a sign inverting means for generating a non-negative (or non-positive) radix-2 signed digit number, and the sign inverting means comprises: (a) a logical negation of the most significant digit of the signed digit number Y; First means for generating a sign inversion (or a logical NOT of the magnitude of the most significant digit); and (b) each non-negative (or non-positive) except the most significant digit and the least significant digit of the signed digit number Y. Second means for converting a digit to a logical negation of the digit size (or a sign inversion of the logical negation of the digit size); and (c) the least significant digit of the signed digit number Y is 0. At this time, the correction term 1 (there is one higher digit of the lowest digit) I-
And a third means for adding 1). 6. A signed digit number X and a signed digit number Y in which each digit other than the most significant digit is non-negative (or non-positive).
And (a) the control signal A and the most significant digit of the signed digit number Y are input, and the most significant digit of the signed digit number Y is set according to the value of the control signal A. First to generate the sign complement of the digit size complement (or the most significant digit complement)
(B) The control signal A and each non-negative (or non-positive) digit other than the most significant digit of the signed digit number Y are input, and the signed digit is selected according to the value of the control signal A. Each non-negative (or non-positive) digit of the number Y is the complement of the magnitude of that digit (or the sign inversion of the complement of the magnitude of that digit)
(C) The control signal A and the most significant digit of the signed digit number Y are input, and the least significant digit of the signed digit number Y is input according to the value of the control signal A. And a third means for adding a correction term to the sign number of the signed digit number Y according to the value of the control signal A, and the addition and subtraction of the signed digit number X and the signed digit number Y. An arithmetic processing device characterized by executing.