JPH0667852A - Divider - Google Patents

Abstract

PURPOSE:To provide an efficient divider for executing the scaling conversion of a normalized divisor range by using a redundant binary adder for partial residual calculation, and determining a quotient by the two upper digits of a partial residual value. CONSTITUTION:The divider is provided with a carry look ahead adder for executing the scaling conversion of the range of a divisor X into 1<=X<3/2, a redundant binary adder having no carry propagration (-1, 0, +1) in partial residual calculation, a circuit for controlling addition by determining a quatient by the two upper digits of a partial residual value, and a circuit 5 for converting a quotient from a redundant binary value into a binary value. Although 10 logical steps are used for the determination of one digit of a quotient in a convensional divider, the determination can be attained only by 7 steps in this divider, and since the conversion of a redundant binary value into a binary value can be efficiently executed, performance can be improved 30% or more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic operation control system for a computer system, and more particularly to a divider suitable for realizing high speed division.

[0002]

2. Description of the Related Art Generally, in division, a quotient is determined in units of one digit, a partial remainder is calculated based on the quotient determination, and in the next operation step, the partial remainder value is shifted by one digit.
Based on that, the quotient of the next digit is determined, and so on, and the iterative operation is executed. This method of determining the quotient in units of one digit is called a radix-2 division method. As a method for achieving this at high speed, redundancy is added to the partial remainder calculation.
A method has been devised in which a redundant binary adder that uses the expression of {+1, 0, -1} called a decimal number is provided to perform addition without carry propagation (Takashi Taniguchi, Toichi Edamatsu, Yasushi Nishiyama, Kunio). Nobushigero, Takagi Naofumi: High-speed multiplier / divider using redundant binary representation, IEICE Technical Report ICD88-39,
1-6, 1988).

[0003]

In this method, it is necessary to refer to the highest three digits of the partial remainder value to determine the quotient. Number of logical stages of circuit (2-input AND, OR or EO
(R equivalent is counted as one stage), which is four stages. Further, after the quotient is determined, the redundant binary adder is used to calculate the partial remainder, which requires 6 logical stages. Therefore, in order to determine one digit of the quotient, 10 stages are required as the total number of logic stages of the circuit. However, the divisor X is 1/2 ≦ X <1 (notationally, [1/2,
1) = O. In principle, it is impossible to make the reference of the partial remainder value for determining the quotient smaller than 3 digits unless it is normalized in the range of (1 ...).

Further, since the quotient determined by this method is represented by a redundant binary number, it is necessary to finally convert it into a normal binary number. This operation is easy, +1
The digit component represented by (1) and the digit component represented by -1 may be divided, and the latter may be subtracted from the former by a normal binary adder. Therefore, in most of the documents including the cited document, the redundant binary-to-binary converter is not directly configured because it can be easily configured by a normal binary adder. However, it will be easier if the redundant binary-to-binary converter is directly constructed.

Therefore, the object of the present invention is to determine the quotient decision logic by determining the range condition of the divisor which makes the reference digit number of the partial remainder value necessary for determining the quotient less than three digits. It is to provide a high-speed divider by simplifying and reducing the number of logic stages of the circuit and by directly configuring a redundant binary to binary converter of a quotient.

[0006]

[Means for Solving the Problems] As a result of obtaining a condition for determining a quotient by referring to a partial remainder value having less than three digits, the range of divisor is [1,3 / 2) = 1.0. .., which was clarified to be a two-digit reference. Therefore, the divisor is converted so that it falls within this range. Specifically, from the normalized divisor X = 0.1 ..., refer to the second digit after the decimal point, and if 0, double the divisor X, that is, 2X = Set to 1.0 ...
If 1, then add divisor X and (1/2) X by carry lookahead adder, ie X +
(1/2) X = 1.0 ... At this time, if the same conversion is applied to the dividend Y at the same time, the value of the quotient does not change, so that the quotient is correctly obtained.

Also, the quotient redundant binary → binary converter is +1.
The digit component represented by and the digit component represented by -1 are mutually exclusive by using the property that they are mutually exclusive.
Simpler than a base adder. Further, since the quotient is sequentially obtained in the operation step of one digit unit, it should be noted that the switching operation of the gate in the previous operation step has already been decided, so that it becomes faster than the operation speed of the normal circuit. Indicates that.

[0008]

According to the present invention, the range of the divisor is [1,3 / 2)
However, in order to prevent division by zero, normal division requires preprocessing such as detection of zero operands and alignment of the divisor and dividend. Therefore, the range conversion of the divisor can be executed in parallel with this preprocessing, and since there is no overhead at all, a high-speed divider can be realized.

[0009]

FIG. 1 shows an embodiment of the basic configuration of a radix-2 divider according to the present invention. Generally, in a floating point operation, it is divided into an exponent part, a sign part, and a mantissa part.
Only the processing of the mantissa, which is the heaviest processing and is essential, will be described. The other parts are not essential as the processing is not so heavy. In addition, digit alignment processing is required for application to fixed-point arithmetic or integer arithmetic, but this is not essential because it may be considered separately.

Let Y be the dividend and X be the divisor. The storage registers for the dividend Y and the divisor X are set to 10 and 20, respectively. These are converted into Y′11 and X′21, respectively, by performing a scaling operation described later. The quotient is determined for each digit based on the values of Y'and X '(circuit 30), and the partial remainder calculation is performed without carry propagation using the redundant binary adder (circuit 40). Then, the partial remainder calculation result is shifted by one digit, and the quotient of each digit is determined in the same manner. These arithmetic circuits 30, 31, ...
.., 40, 41, ... Are arranged in an array as shown in FIG. Finally, the determined quotient q (0) of each digit,
.., q (n-1) are represented by redundant binary numbers, and thus are converted into normal binary numbers by the redundant binary-to-binary converter 50 to obtain the final quotient.

The circuit operation of the multiplier shown in FIG. 1 will be described below in more detail.

First, it is assumed that the dividend Y and the divisor X are both normalized and have a shape of 0.1 ... As shown in Table 1, these are converted into Y′11 and X′21, respectively, by a scaling operation of keeping the range of the divisor X within [1,3 / 2].

[0013]

[Table 1]

That is, as shown in FIGS. 2 and 3,
If the value of the second digit after the decimal point is 0, the divisor X is doubled to form 2X = 1.0. If it is 1, the value of divisor X and its half is carried to adder with carry forward 1
Add 2 and 22 to form X + (1/2) X = 1.0 ... Let this conversion be M, X '= MX, Y' =
Assuming that MY and the quotient are Q, Q = Y / X = (MY) / (MX) = Y ′ / X ′ (Equation 1), so that the quotient can be correctly obtained by the scaling operation. Recognize.

The radix-2 division is repeatedly executed by the recurrence formula R (i + 1) = 2 (R (i) -q (i) X ') (Equation 2). Here, i represents the number of repeating steps of the calculation, and indicates that it is related to the calculation for determining the quotient at the i-th digit after the decimal point. R (i) is the partial remainder value before performing the partial remainder calculation at the i-th step,
Based on this value, the quotient of the i-th decimal place is determined. In particular, R (0) = Y '. Then, the partial remainder is obtained using the redundant binary adder without carry propagation.
The partial remainder result is doubled (shifted by one digit) to become the partial remainder value R (i + 1) used in the next calculation step i + 1.

Next, the quotient q (i) is determined from the upper two digits of the partial remainder value R (i), and the signal output allocation for controlling the addition of the redundant binary adder 80 shown in FIG. 4 is shown in Table 2. Show.

[0017]

[Table 2]

This is a scaling operation of the divisor X to X '.
= [1,3 / 2). There are qc and qv in the output of the addition control signal, and so to speak, qc is a code signal of the absolute value qv. Thereby, the quotient q (i) represented by the redundant binary number can be represented by two binary signals. According to this table 2, the quotient q
Even if the value of (i) is zero, the output value of the addition control signal qc is 1
Therefore, 1 may be input to the redundant binary adder 80. The reason is that when adding a zero value, there are two methods in the two's complement representation, and the present invention uses them properly. That is, if there is a decimal point between the second highest digit and the third highest digit, and the highest first digit is the sign bit for the 2's complement expression, the zero value can be expressed in the following two ways.

(1) 0 = 00.0 ... 00 or (2) 0 = 11.1 ... 11 + 00.0 ... 01 (that is, inversion of zero + 1 is also zero) Control logic is simplified by proper use,
As shown in FIG. 4, the quotient determination circuit 60 is composed of two logic stages, which is half of the conventional four stages. The upper two digits of the partial remainder value R (i) are input to the quotient determination circuit 60 of FIG. 4, and the symbols r0- and r0 + are respectively the -1 expression component of the second highest digit (0th decimal point), It indicates that the value of the +1 expression component is input. The symbols r1- and r1 + indicate that the values of the -1 expression component and the +1 expression component of the third highest digit (first digit after the decimal point) are input, respectively. Furthermore, the sign
rj- and rj + are the -1 expression components at the jth digit after the decimal point,
It is shown that the value of the +1 expression component is input to the redundant binary adder 80. Redundant binary adder 8th digit after the decimal point
The partial remainder calculation result of 0 is indicated by the symbols r'j-, r'j +.
The carry c-out (j + 1) at the (j + 1) th place after the decimal point is input to the redundant binary adder 80, but carry propagation to the higher order is not generated. Similarly, the carry c-out (j) at the jth digit after the decimal point is output. The symbol x '(j) indicates that the value of the scaled divisor X', which is the jth digit after the decimal point, is input.

Finally, the determined quotient q (0). q (1)
Since q (n-1) is a redundant binary number expression, it is converted to a normal binary number by the redundant binary-to-binary converter 50 to obtain the final quotient Q. 4-digit redundant binary number, (qj
-, qj +), (q (j + 1)-, q (j + 1) +), (q (j + 2)-, q (j + 2) +), (q (j + 3)
FIG. 5 shows an example in which-, q (j + 3) +) is converted into ordinary binary numbers qj, q (j + 1), q (j + 2), q (j + 3). The rightmost symbols + and-indicate that they are related to the values of the -1 expression component and the +1 expression component, respectively. The principle of this converter is that at each digit,
The logic is simplified by utilizing the property that the values of the −1 expression component and the +1 expression component are mutually exclusive. And
The logic is constructed by utilizing the property that if the value of the +1 expression component from a certain digit to the higher digit is zero, the value of the -1 expression component from the lower digit propagates. That is, when a certain digit has a value of the −1 expression component of 1, this is output as a borrow generation signal g. Further, when the value of the +1 expression component of a certain digit is zero, it is output as a digit borrow propagation signal p. For division,
As described above, the quotient is sequentially determined from the upper digit to the lower digit in units of one digit. Here, as shown in FIG. 6, if the logic circuit of the circuit 50 is configured by the basic logic circuit 90 using pass transistors, the circuit 9
Assuming that the A input (corresponding to the upper side input in the circuit 50), which plays the role of switching the gate of 0, operates earlier, the input B (corresponding to the lower side input in the circuit 50). Even if the operation of) is determined thereafter, the circuit 50 operates at high speed because the input signal of B simply passes through the gate instantaneously. Therefore, carry propagation does not occur unlike in the normal case only when the quotient is converted from redundant binary to binary.

[0021]

According to the present invention, the number of logic stages is conventionally required to be 10 in determining a quotient per digit, but it can be realized with 7 stages, and redundant binary → binary conversion is efficient. Therefore, there is an effect that performance improvement of 30% or more can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a radix-2 divider according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a method of executing scaling conversion in parallel with a zero detection circuit to eliminate overhead of scaling conversion.

FIG. 3 is a selector circuit that controls scaling conversion.

FIG. 4 is a circuit for calculating a quotient at an arbitrary step and calculating a partial remainder of a certain digit.

FIG. 5 is a circuit for performing redundant binary conversion.

FIG. 6 is a basic circuit for forming a logic circuit using pass transistors.

[Explanation of symbols]

1 ... Zero division detection signal, 2 ... Scaling conversion selector circuit, 10 ... Divisor Y storage register, 20 ... Divisor X storage register, 11 ... Scaling converted dividend Y'storage register , 12, 22 ... Adder with carry look ahead, 21 ... Scaling-converted divisor X'storage register, 30, 31, 32, 33 ... Quotation decision circuit, 4
0, 41, 42 ... Partial remainder calculation circuit, 50 ... Redundant binary-to-binary conversion circuit, 60 ... Quotient decision circuit, 80 ... Partial remainder calculation circuit for arbitrary digits, 90 ... Basic logic circuit constructed by using pass transistors, ∨ ・ ・ ・ OR, ∧ ・ ・ ・ AND,
¬ Logical negation.

Claims (5)

[Claims] 1. A redundant binary number called {+ in partial remainder calculation.
By providing a redundant binary adder using the expression of 1,0, −1}, scaling conversion of the divisor X to a range of 1 ≦ X <3/2, and referring to only the upper two digits of the partial remainder value A radix-2 divider that simplifies quotient decisions. 2. A radix-2 divider according to claim 1, wherein the scaling transform is executed in parallel with a preprocessing part such as zero division detection. 3. When a zero value is added to the partial remainder, (1) all 0 pattern and (2) all 1 pattern + 1, that is, inversion of all 0 pattern + 1 are used separately by the two's complement representation of the addend. The radix-2 divider of claim 1, wherein the quotient decision logic is simplified. 4. In the redundant binary number representation, a redundant binary → binary converter is provided, which utilizes the property that the −1 expression component and the +1 expression component do not appear simultaneously in the same digit.
The radix-2 divider according to claim 1, wherein the quotient expressed in a base number is efficiently converted into a normal binary number. 5. The circuit of the redundant binary-to-binary converter according to claim 4, wherein a logic circuit is constructed by using a pass transistor, and is executed at high speed without propagation delay of gate operation. The radix-2 divider according to claim 1.