JPH061433B2 - Processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic operation processing device, and more particularly to a high speed operation processing device having a cell array structure and suitable for use in an LSI.

2. Description of the Related Art Conventionally, for example, regarding high speed multipliers, the Institute of Electronics and Communication Engineers, Vol. J66-D, No. 6 (1983), pages 683 to 690, and a high-speed divider is described in The Institute of Electronics and Communication Engineers, Vol. J67-D, NO.4
(1984) pp. 450-457. These are arithmetic units that execute multiplication or division by a combinational circuit using a redundant binary representation (a kind of extended SD representation) in which each digit is represented by an element of {-1, 0, 1}.
Therefore, it is superior to other arithmetic units in terms of arithmetic processing time and regular array structure, but the number of elements and the area are reduced, and M
No consideration was given to practical use such as realization with an OS circuit.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the above-mentioned conventional technology, there has been proposed a method for realizing a combination circuit such as multiplication or division by taking advantage of the features of an ECL logic element capable of simultaneously taking NOR and OR. Practical aspects such as reduction in the number of elements and realization with other circuit diameters have not been taken into consideration. (1) The number of elements becomes enormous as the number of digits in the number of operations increases,
It is difficult to realize with one LSI chip.

(2) When implementing NOR and RO with a MOS circuit that cannot simultaneously obtain RO, it is necessary to configure RO with two stages of elements of NOR and inverter, and the number of stages of the arithmetic circuit increases accordingly. Grows larger.

There are problems such as.

An object of the present invention is to improve such conventional problems, to realize an arithmetic processing device as a combinational circuit having an array structure and a small number of elements, minimize propagation of a carry value, and simplify the circuit configuration. The object of the present invention is to provide a high-speed arithmetic processing device that can be easily mounted on an LSI by implementing the above-mentioned processing.

Means for Solving the Problems The above-mentioned object is to provide an arithmetic processing device equipped with an addition / subtraction means for performing addition or subtraction between a signed digit number and a binary number according to the value of a control signal. , (A) an intermediate carry (intermediate carry) determining means for inputting a signed digit number and a binary number and determining an intermediate carry (intermediate carry) in addition (subtraction) thereof, (b) Intermediate sum (intermediate difference) determining means for inputting a signed digit number and the binary number and determining an intermediate sum (intermediate difference) in addition (subtraction) thereof, and (c) the intermediate sum (intermediate difference)
Addition from the intermediate sum (intermediate difference) obtained by the determining means and the intermediate carry (intermediate carry) provided by the one-digit lower digit (intermediate carry) The final sum (final difference) determining means for determining the result of the subtraction) and outputting it as a signed digit number, and (d) the control signal and the signed digit number or binary number are input, and the control signal It is achieved by having a sign inverting means for inverting the sign of a signed digit number or a binary number, and performing an operation such as addition / subtraction or digit shift by addition (subtraction) means of the signed digit number and the binary number. .

Operation For example, in internal calculation, a digit with a sign (extended SD (Signed Digit) that represents each digit as 0, a positive integer, or a negative integer corresponding to the positive integer.
t)) expression is used to represent the internal operation number. That is, each digit is either {-1, 0, 1}, {-2, -1, 0, 1, 2} or {-N, ..., -1, 0, 1, ..., N}, etc. It is represented by such an element, and redundancy is provided so that one number can be expressed in any number. At that time, the intermediate carry (or intermediate carry) decision circuit and the intermediate sum (or intermediate difference) decision circuit in addition (subtraction) of the signed digit number and the binary number carry (or borrow) from the lower digit. ), The middle digit (or difference) of that digit and the carry (or borrow) from the lower digit always fit within one digit. Raising (or borrowing intermediate digits) and intermediate sum (or intermediate difference) can be determined respectively. Thereby, carry (or intermediate carry) propagation can be prevented to some extent in addition (or subtraction), and parallel addition (or subtraction) by the combination circuit can be performed in a constant time regardless of the number of digits of the operation number.
For example, an extended SD that represents each digit with an element of {-1, 0, 1}
In the representation (that is, redundant binary representation), carry (or borrow) in addition (or subtraction) can be propagated at most one digit. Regarding this, the Institute of Electronics and Communication Engineers, Vol. J67-D, NO.4 (19
1984) pp. 450 to 467 or IEICE Transactions, Vol. J66-D, NO.6 (1983) No. 6
There is an explanation from page 83 to page 690.

Further, the inverting circuit receives either one of the number of signed digits and the binary number which is an input of the intermediate carry (or intermediate carry) decision circuit and the intermediate sum (or difference) decision circuit, and subtracts the operation. Depending on the control signal indicating whether the operation number is addition or addition, the sign of the operation number is inverted or not. As a result, either addition or subtraction of the redundant expression can be executed only by addition (or subtraction) of the number of signed digits and the binary number, so that the number of elements can be reduced.

Further, the conversion circuit can set one of the internal operation numbers to 0 according to the value of the control signal such as 0 or 1. Thereby, the shift of the digit of the operation number or the operation such as the multiplication by 0 can be performed by using addition (or subtraction) of the number of signed digits and the binary number, so that the addition and subtraction and the digit shift are performed for the internal operation processing. It is possible to omit the circuit and reduce the number of stages of gates of the arithmetic circuit.

Therefore, it is possible to reduce the number of elements and the number of stages of the circuit for which each digit of each internal operation is determined, and it is possible to configure a high-speed operation circuit as a regular array structure of these circuits. .

Example Hereinafter, one example of the present invention will be described with reference to a cross section.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. Particularly, in this embodiment, an n-digit unsigned r-adic fractional divider will be described. Note that in FIG. 2, n = 8, r
It is a block diagram in case of = 2. In the figure, the dividend 20 is
1st digit, 2nd digit, ... nth digit value x ₁ , x ₂ ,
.., x _n are input to the initial partial remainder determination circuit 100 in the form of signals. Similarly, the divisor 40 is also the first digit, second digit, ..., Nth digit value y ₁ , y ₂ , ...
, Y _n in the form of a signal representing the initial partial remainder determination circuit 100
And partial remainder decision circuits 101, 102, 103, 10
It is input to 4, 105, .... The quotient 60 is the first digit of the integer z ₀ , the first digit of the decimal point z ₁ , the second digit of the decimal point z ₂ , ...
..., which is output from the conversion circuit 10 for converting to the R-ary as the R-ary of the nth digit z _n below the decimal point. Initial partial remainder determination circuit 100
Is the dividend [0. x ₁ x ₂ ...... x _n] r ²⁰ⁿ and the divisor [0. y ₁ y ₂ ... Y _n ] r ⁴⁰ⁿ is input, and this is a circuit that outputs the partial remainder after deciding the integer first digit of the quotient or the inverted sign of the partial remainder. In particular, when the dividend and divisor are normalized, x ₁ = y ₁ = 1 and q ₀
= 1 can be easily obtained. However, q ₀ is a quotient [q in the SD representation number of the radix r that is an input to the r-adic conversion circuit 10.
₀ . It is _{q 1 q 2 ...... q n]} SDr integer first digit. The normalized divisor and divisor will be described below.

Further, the partial remainder decision circuits 101, 102, 103, 10
, 105 are output from the partial remainder determination circuit (or the initial partial remainder determination circuit 100) in the upper stage of the figure and the divisor 40 and the quotient determination cells 201, 202, 202 respectively corresponding to the same stage. 203, 204, 205 ...
Control signals 251, 252, 253, 25 which are outputs of
4, 255 ... Is an input, and is a circuit that outputs a partial remainder or an inversion of the sign of the partial remainder to be the input to the partial remainder determination circuit of the next stage (that is, the lower stage).

Quotient decision cells 201, 202, 203, 204, 205
.. are the upper three digits and the upper stage (that is, j-1) of the partial remainder or the inversion of the sign of the partial remainder output from the partial remainder determination circuit of the upper stage (for example, j-1 stage), respectively.
The value of the j-1th digit after the decimal point of the quotient represented by the expanded SD expression already expanded by the quotient determination cell
The value of the j-th digit below the decimal point of the quotient and the control signal 25 for the partial remainder determination circuits of the same stage (that is, j stages), respectively.
It is a circuit for outputting 1, 252, 253, 254, 255, ....

The r-adic conversion circuit 10 includes quotient decision cells 201 and 20.
2, 203, 204, 205, ..., each digit of the quotient expressed in the extended SD expression determined respectively is input, and each digit is a non-negative ordinary r-ary quotient [z ₀ . z ₁ z ₂ ……
It is a circuit that outputs z _n ] r ⁶⁰ .

Next, a division method using these blocks will be described.

The subtraction shift type division method is generally expressed by the following recurrence formula.

R ^{(j + 1)} = where _{^{r × R (j) -q j}} × D, j is the index of the recurrence formula, r is the radix, D is the divisor, q _j
Is the jth digit after the decimal point of the quotient, R ^(j) is the partial divisor before determining q _j , and R ^{(j + 1)} is the partial remainder after determining q _j .
Thus, for each index j recurrence formula, the quotient determined for cells that determines the quotient q _j, or subtracting D from r × R ^(j) according to the value of q _j, the partial remainder decision circuit or not reduce Provided,
It can be realized as a combinational circuit.

It is possible to realize a high-speed divider by using the extended SD expression for the above internal calculation. At that time, for example, using the extended SD representation of radix 2, 1 bit of the integer part,
An unsigned binary number X having a decimal part of n bits is represented by X = [x ₀ . x ₁ …… x _n ] SD2, X is Represents the value. However, each digit x _i is {-1, 0,
1} is an element. In this case, in the above recurrence formula, when representing the divisor D and the partial remainder R ^(j) in the extended SD representation of radix-2, depending on the value of q _j, when the q ^_j = -1 R ^_(j)
Is shifted to the left by one digit, D is added, R ^(j) is shifted to the left by 1 digit when q _j = 0, and R ^(j) is shifted by R when q _j = 1.
^It is necessary to add D after shifting ^(j) one digit to the left.

In the present invention, in particular, q is provided by means (circuit) for inverting the positive / negative of the internal operation number of the extended SD expression and means for assigning 0 to the internal operation number according to the value of the jth digit q _j below the decimal point of the quotient. The partial remainder R ^{(j + 1)} after determining _j is expanded as R ^{(j + 1)} = P ^(j) (P ^(j) (r x R ^(j) )) + D ^(j) ) It can be determined only by adding SD expressions. Here, P ^(j) is a function that performs positive / negative inversion, and D ^(j)
(j) and P ^(j) have several methods. An example is shown below.

P ^(j) (x) = X (that is, P ^(j) is an identity transformation).

However, is the number obtained by inverting the positive and negative numbers of the expanded SD representation numbers D and X, respectively. The positive / negative inversion in this extended SD expression is set to -1 if the digit is 1, and 1 if it is -1, and 0 is left unchanged. But, like,
When D is an extended SD expression in which each digit is non-negative, it is possible to perform positive / negative inversion by the two's complement display.

Therefore, in the case of (II) above, each digit of D ^(j) is always non-negative, and also in the case of (I), by displaying 2's complement, most digits except the leading digit are Since it is possible to make it non-negative, a column of redundant adder circuits (cells) in the one-digit extended SD representation, where one (addition number) is non-negative, is used to determine the partial remainder. Configure the decision circuit.

Next, the above two cases of the method of determining R ^{(j + 1)} will be specifically described using mathematical expressions.

(I) Inversion of addition (that is, divisor): First, in the initial partial remainder determination circuit 100, R ⁽¹⁾ = [0. x ₁ x ₂ ...... x _n] SD2- [0. y ₁ y ₂ ... Y _n ] SD2 is calculated, and the partial remainder R ⁽¹⁾ is determined. However, the above formula is calculated in redundant binary (that is, extended SD of radix 2), and R ⁽¹⁾ is a redundant binary number. Also, x ₁ = 1, y ₁ =
Since it is 1, the first digit of the integer of the quotient is q ₀ = 1. Further, since x ₁ , x ₂ , ..., X _n , y ₁ , y ₂ , ..., Y _n are non-negative, the initial partial remainder determination circuit 100 subtracts redundant binary numbers whose digits are non-negative. It can be easily realized by a circuit or an ordinary subtraction circuit. Further, the determinant of the partial remainder R ⁽¹⁾ is R ⁽¹⁾ = [0. x ₁ x ₂ ...... x _n] SD2 + [0. It is possible to add a redundant binary number and a redundant binary number in which each digit is non-negative like _{1 2} ... _n ] SD2. However, _i means the positive / negative inversion of y _i . That is, when y _i = 1, _i = −1, y _i =
When 0, _i = 0. Here, i is an integer from 1 to n. Therefore, the initial partial remainder determination circuit 100
Can also be implemented as a redundant binary number and a redundant binary number addition circuit in which each digit is non-negative.

Then, now, the partial remainder R ^(j) = [▲ r ^j ₀ ▼. ▲ r ^j ₁ ▼ ▲
r ^j ₂ ▼ …… ▲ r ^j _n ▼] SD2 and the decimal point of the quotient j−
The one digit q _j-1 has already been determined, and the decimal point j of the quotient
The determination of the digit q _j and the partial remainder R ^{(j + 1)} will be described.
However, j is an integer from 1 to n. The jth digit q _j below the decimal point of the quotient is the upper 3 digits of the partial remainder R ^(j) [▲ r ^j ₀ ▼. [R ^j ₁ ▼ r ^j ₂ ▼] It can be determined by the value of SD2. That is, if the upper 3 digits of R ^(j) are positive, then q _j
If = 1 and 0, q _j = 0, and if negative, q _j = −1. The determination of the j-th digit q _j below the decimal point of this quotient is made by the quotient determination cell 2
Among the cells 01, 202, 203, 204, 205, ...

Further, the partial remainder decision circuits 101, 102, 103, 10
In the _j -th circuit from the higher order among the four, 105, ..., When (i) q _j = -1, R ^{(j + 1)} = [▲ r ^j ₀ ▼ ▲ r ^j ₁ ▼. ▲ r ^j ₂ ▼ …… ▲ r ^j _n ▼ 0] SD2 + [0. y ₁
y ₂ ...... y _n ] SD2 (ii) q _j = 1 and R ^{(j + 1)} = [▲ v ^j ₀ ▼ ▲ v ^j ₁ ▼. ▲ v ^j ₂ ▼ …… ▲ v ^j _n ▼, 1] SD2 + [0.
u ₁ u ₂ ...... u _n] SD2 However, i = 1, ......, relative to n, a _{u i = 1-y i,} ▲ v j 1 ▼ and ▲ v ^j ₀ ▼ value, ▲ When r ^j ₁ ▼ = 1, ▲ v ^j ₀ ▼ = ▲ r ^j ₀ ▼, ▲ v ^j ₁ ▼ = 0, when ▲ r ^j ₁ ▼ = 0 ▲ v ^j ₀ ▼ = ▲ r ^j ₀ ▼, ▲ v ^j ₁ ▼ = -1, ▲ r ^j ₁ ▼ =
When −1, ▲ v ^j ₀ ▼ = 0 and ▲ v ^j ₁ ▼ = 0. Here, D = [0. y ₁ y ₂ …… y _n ] SD2 is represented by the two's complement notation: = [(-1). 00 ... 1] SD2 + [0. u ₁ u ₂ ... u _n ] SD2 is used.

(iii) When q _j = 0, R ^{(j + 1)} = [▲ r ^j ₀ ▼. ▲ r ^j ₁ ▼ ▲ r ^j ₂ ▼ …… ▲ r ^j _n ▼ 0] SD2 + [0.0
0 ... 0] SD2 is calculated to determine the partial remainder R ^{(j + 1)} . Above (i),
In the formulas for determining the partial remainder R ^{(j + 1)} in (ii) and (iii), in each case, the second page has non-negative digits, so the partial remainder determining circuits 101, 102, 103, 104, 105, ...
... is a redundant binary number and a redundant binary number in which each digit is non-negative (that is, 2
It can be realized by an addition circuit for a base number and a circuit for determining the addition number.

In this case, the control signals 251, 252, 253, 254,
255 ... are q _j of the corresponding stages.

Finally, each digit q _j of the quotient is determined as above from j = 1 to n, and the quotient Q = [q ₀ . q ₁ q ₂ ...... q when _n] SD2 is determined, extended SD representation quotient Q usual r by the conversion circuit 10 to r advance (i.e. 2) proceeds representation Z = [z _0. z ₁ z ₂
...... converted to z _n] r _60. The r-adic conversion circuit 10 is
Only digits that is a 1 in the quotient Q of the redundant binary representation of unsigned from binary Q ⁺ you 1, the quotient Q unsigned binary number was 1 only digit to become -1 Q ^- normal Subtraction of Q ⁺ Q ⁻
And a carry look-ahead addition circuit or a carry look-ahead addition circuit.

(II) When augend inversion (i.e. partial remainder): Now, consider the partial remainder R ^(j) a code by different Ru value A ^(j) in place of the partial remainder R ^(j). Hereinafter, this value is also called a partial remainder.
A ^{(j + 1)} is defined as A ^{(j + 1)} = P ^(j) (r × R ^(j) ) + D ^(j) . However, P ^(j) is a function that performs positive / negative inversion according to the value of q _j .

First, in the initial partial remainder determination circuit 100, A ⁽¹⁾ = [0. _{1 2} ...... _n ] SD2 + [0. y ₁ y ₂ ... Y _n ] SD2 is calculated, and the partial remainder A ⁽¹⁾ is determined. However, i
= 1, ..., N, _i is a number obtained by inverting the sign of x _i . Furthermore, y _i is always non-negative for i = 1, ..., N, so the initial partial remainder determination circuit 100 is redundant 2
This can be realized by a redundant binary number addition circuit in which each digit and each digit are non-negative. Also, as in the case of (I), each digit has a non-negative redundancy 2
It can also be realized by using a subtraction circuit between base numbers. The first digit of the integer in the quotient in the redundant binary representation is q ₀ as in the case of (I).
= 1.

Next, the partial remainder A ^(j) = [▲ a ^j ₀ ▼. ▲ a ^j ₁ ▼ ▲ a ^j ₂
▼ …… ▲ a ^j _n ▼] SD2 and the decimal point j-1 of the quotient
The determination of the decimal point j-th digit q _j and the partial remainder A ^{(1 + 1)} when the digit q _j-1 has already been determined will be described.

The jth digit after the decimal point q _j of the quotient is the quotient determination cell 2 of the jth stage.
01, 202, 203, 204, 205 ...
Upper 3 digits of partial remainder A ^(j) [▲ a ^j ₀ ▼. ▲ a ^j ₁ ▼ ▲ a ^j ₂ ▼] It is determined by the value of SD2 and the j−1th digit q _j−1 below the decimal point of the quotient. That is, if the upper three digits of the value is a positive _{^{A (j) q j = sign}} (-
q _j-1 ), q _j = 0 if 0, q _j = -sign (-if negative
q _j-1 ). However, sign (-q _j-1 ) is It is defined as

Further, the partial remainder decision circuits 101, 102, 103, 10
In the circuit of the jth stage among 4, 105, ...^{(j + 1)}= P^(j)(2 x P^(j-1)(A^(j))) + D^(j) Is calculated, and the partial remainder A^{(1 + 1)}To decide. However,
The first term in the above equation is (i) sign (-q_j-1) × sign (-q_j) = 1
K, P^(j)= (2 x P^(j-1)(A^(j))) = [▲ a^j ₀▼ ▲ a^j ₁▼. ▲ a^j ₂▼ …… ▲ a^j
_n▼ 0] SD2 (ii) sign (-q_j-1) × sign (-q_j) =-1
When P^(j)= (2 x P^(j-1)(A^(j))) = [▲ a ₀▼ ▲ a ₁▼. ▲ a _Two▼ ...
… ▲ a _n▼ 0] SD2, and the second term is (i) q_jWhen ≠ 0, D^(j)= [0. y₁y₂...... y_n] SD2 (ii) q_jWhen = 0, D^(j)= [0.00 ... 0] SD2, and each digit is a non-negative redundant binary number. Therefore part
Remainder determination circuits 101, 102, 103, 104, 10
5, ... Adds a redundant binary number and a redundant binary number in which each digit is non-negative.
Arithmetic circuit, redundant binary number inversion circuit and addition number are determined
It can be realized by a circuit. In this case, the partial remainder decision circuit
Control signals 251, 252, 253, 254, 25 to
5 ... is the corresponding digit q of the quotient_jThe size of
-Q_jAnd -q_j-1It is composed of whether or not there is a difference in sign.

Finally, the redundant binary representation of the quotient Q = [q ₀ . y ₁ y ₂ ...... y _n ]
From SD2 the usual binary representation Z = [Z ₀ . z ₁ z ₂ ...... z _n ]
The conversion to 2 is performed in the r-adic conversion circuit 10 in the same manner as in the case of (I).

The above is the description of the division method using the individual blocks constituting the divider shown in FIG. 2, but in the case of (I),
Each quotient determination cell 202, 203, 204, 2 in the figure
The input signal lines 271, 272, 273, 274, ... from the upper quotient decision cells to 05, 206, ... Are unused and may be omitted.

Next, the partial remainder determination circuits 101, 102, 103, 10
4, 105, ... Will be described.

FIG. 3 is a partial remainder determination circuit 101,
2 is a block diagram showing a configuration example of 102, 103, 104, 105, .... Partial remainder determination circuit 300 (11
01, 102 ...) are n + 1 redundant addition cells 31.
An array of 0, 311, 312, 313, ..., 329, 330. Now, suppose that the partial remainder determination circuit 300 is the second
Assuming that the partial remainder determining circuit at the j-th stage in the figure, the inputs 340, 341, 342, 343, ... Corresponding to the augends.
, 359 are the respective digits of the partial remainder determined in the previous stage (that is, j-1 stage) ▲ r ^j ₁ ▼, ▲ r ^j ₂ ▼, ......, ▲
r ^j _n ▼, or ▲ a ¹ _j ▼, ▲ a ² _j ▼, ..., ▲ a ⁿ _j
Indicates the value of ▼. Inputs 361 and 36 corresponding to the number of additions
₁ , 363, ... 379, 380 respectively represent the digits y ₁ , y ₂ , ..., Y _n of the divisor. The control signal 390 is
One of the control signals 251, 252, ... In FIG. 1, which is a signal determined from the already determined digit q _j or q _j-1 of the quotient in the quotient determining cell in the same stage (that is, j stage). is there. Input from the lower redundant addition cell to the upper redundant addition cell 441, 442, 443, ..., 450
Indicates the middle carry from the lower digit, respectively. Further, the outputs 410, 411, 412, ..., 430 of the redundant addition cells 310, 311, 312, ..., 330 are respectively the respective digits of the partial remainder ▲ r ^{j + 1} ₀ ▼, ▲ r ^{j + 1} _1. ▼, ▲ r
^{j + 1} ₂ ▼, ……, ▲ r ^{j + 1} _n ▼ or ▲ a ^{j + 1} ₀ ▼, ▲ a
^{j + 1} ₁ ▼, ▲ a ^{j + 1} ₂ ▼, ..., ▲ a ^{j + 1} _n ▼. In the case of r = 2, that is, in the case of binary representation, the first digit after the decimal point of the divisor is fixed as y ₁ = 1 and thus the input 361 may be omitted. Further, in the case of (II), the carry 450 of the last digit can be omitted.

Redundant addition cells 310, 311, 312, 313, ...
…, 329, 330 are partial remainders R ^{(j + 1)} or A
It is a cell that determines the integer first digit of ^{(j + 1)} , the first digit after the decimal point, the second digit after the decimal point, ..., And the nth digit after the decimal point. Among these redundant addition cells, in order to reduce the number of elements, the redundant addition cells 312, 313, ... The redundant addition cells 310 and 311 of the digits and the redundant addition cell 330 of the least significant digit (that is, the nth digit after the decimal point) may be exceptional cells. Further, the redundant addition cells 310 and 311 of the upper two digits are arranged in the same stage (that is, j stage).
It is also possible to combine them with the quotient decision cell of No. 1 into one cell, or the redundant addition cell 3 of the lowest digit of the jth stage.
It is also possible to reduce the number of elements by combining the redundant addition cells 329 of 30 and j + 1 stages with n-1 digits below the decimal point into one cell. Further, for an integer j in the range of n / 2 <j ≦ n−1, in the partial remainder determination circuit of the jth stage, the redundant addition cells after 2 × (n−j + 1) digits after the decimal point are omitted. Good. FIG. 2 particularly shows an example in which this part is omitted.

Next, the basic cell in the redundant addition cell will be described for each of the cases (I) and (II).

FIG. 4 shows (I), that is, each redundant addition cell 312, 313, ..., 329 in FIG.
FIG. 3 is a block diagram showing a configuration example of a basic cell configuring

The basic cell 470 (312, 313 ...) Is composed of an addition number determination circuit 472, an intermediate sum determination circuit 473, an intermediate carry determination circuit 474, and a final sum determination circuit 475. The input 481 is a signal representing the value of the _{i +} 1th digit ▲ r ^j _{i + 1} ▼ below the decimal point of the partial remainder R ^(j) , and ▲ r ^j _{i + 1}
Since ▼ is redundant binary, a 2-bit signal is required.
The input 482 is a signal d _i that represents a value y _{i of} i digits to the right of the decimal point of the divisor, and since d _i is a binary number, it may be a 1-bit signal. Further, the control signal 483 is the j-th decimal point of the quotient.
It is a signal representing the digit q _j , and since q _j can take values of 1, 0, -1, it must be a 2-bit signal. Addition number 4
Since 85 is a binary number that takes values 0 and 1, it is a 1-bit signal. The signal 486 is a 1-bit signal indicating the intermediate sum ▲ s ^j _i ▼ of the i-th digit below the decimal point, the signal 487 is a 1-bit signal indicating the presence or absence of intermediate carry of the i-th digit below the decimal point, and the signal 488 is This is a 1-bit signal indicating the presence / absence of an intermediate carry from the (i + 1) th digit after the decimal point. Further, the output 489 of the final sum decision circuit 475 is a 2-bit signal representing the value of the i-th digit ∇r ^{j + 1} _i ▼ below the decimal point of the partial remainder R ^{(j + 1)} .

The addition number determination circuit 472 is a circuit that determines the _i- th digit ▲ d ^j _i ▼ below the decimal point of the addition number according to the value of the j-th digit after the decimal point q _j of the quotient. That is, when q _j = -1, ▲ d ^j _i ▼
= D _i , q _j = 0, ▲ d ^j _i ▼ = 0 and q _j = 1, ▲ d ^j _i ▼ = 1-d _i, and the addition number is determined by inverting or allocating 0.

The intermediate sum determination circuit 473 uses the redundant binary augend ▲ r ^j _{i + 1}
This is a circuit for determining an intermediate sum by performing redundant addition of ▼ and a normal binary addition number ▲ d ^j _i ▼. That is, the intermediate sum is determined as shown in Table 1.

The intermediate carry determination circuit 474 is a circuit for determining an intermediate carry value by performing redundant addition of the augend ▲ r ^j _{i + 1} ▼ and the addition number ▲ d ^j _i ▼. That is, the intermediate carry value is determined as shown in Table 2.

The final sum determination circuit 475 obtains the sum of the intermediate sum of the i-th digit after the decimal point and the intermediate carry value of the i + 1-th digit after the decimal point, and calculates the i-th digit r ^{j + 1} _i of the decimal point of the partial remainder R ^{(j + 1).} It is a circuit to decide.

Next, a similar explanation will be given for the case of (II).

FIG. 1 shows (II), that is, the redundant addition cells 312, 313, ..., 32 in FIG. 3 in the case of inversion of the augend.
FIG. 9 is a block diagram showing an example of the configuration of a basic cell that constitutes No. 9.

The basic cell 510 (312, 313 ...) Has a positive / negative inversion circuit 511, a divisor conversion circuit 512, and an intermediate sum determination circuit 51.
3. Intermediate carry determination circuit 514 and final sum determination circuit 5
It consists of 15. Input 521 is a 2-bit signal representing the value of the decimal point (i + 1) th digit ▲ a ^j _{i + 1} ▼ partial remainder A ^(j), the control signal 523, the decimal point of quotient of the j digit q _j size , And a 2-bit signal indicating whether or not there is a sign difference between −q _j−1 and −q _j . Positive / negative inversion circuit 511
Output 524 of 2 is 2 representing the redundant binary augend ▲ e ^j _i ▼
It is a bit signal. Also, the output 5 of the divisor conversion circuit 512
Reference numeral 25 is a 1-bit signal representing a binary addition number ▲ d ^j _i ▼. Also, signals 526, 527 and 528 are the same as signals 486, 487 and 488 in FIG. 4, respectively. The output 529 is a 2-bit signal representing the value of the i-th digit ▲ a ^{j + 1} _i ▼ after the decimal point of the partial remainder A ^{(j + 1)} .

The plus / minus inversion circuit 511 has a decimal point j, j−1 digits q of the quotient.
It is a circuit for determining ▲ a ^j _{i + 1} ▼ of the _{i +} 1th digit below the decimal point of the partial remainder according to the difference in the signs of _j and q _j-1 . That is, when sign (-q _j-1 ) × sign (-q _j ) = 1, ▲ e ^j _i ▼ = ▲ a ^j _{i + 1} ▼, sign (-q _j-1 ) × s
When ign (−q _j ) = − 1, ▲ e ^j _i ▼ = ▲ ^j _{i + 1} ▼
The positive and negative inversions are performed to determine the augend. However, ▲
If a ^j _{i + 1} ▼ = -1, then ▲ ^j _{i + 1} ▼ = 1, ▲ a ^j _{i + 1} ▼ = 0
Then, if ▲ ^j _{i + 1} ▼ = 0 and ▲ a ^j _{i + 1} ▼ = 1, then ▲ ^j
_{i + 1} ▼ = -1.

The divisor conversion circuit 512 is a circuit that determines the _i- th decimal place ▲ d ^j _i ▼ of the addition number according to the j-th decimal place q _j of the quotient. That is, when q _j ≠ 0, ▲ d ^j _i ▼
= D _j , q _j = 0, the addition number is determined by assigning 0 so that ▲ d ^j _i ▼ = 0. However, d _j represents the value of the i-th digit y _{i after} the decimal point of the divisor.

Intermediate sum determination circuit 513, intermediate sum carry determination circuit 514,
The final sum decision circuit 515 is a circuit similar to 473, 474, and 475 in FIG. 4, respectively.

The above is the partial remainder determination circuits 101 and 10 shown in FIG.
2, 103, 104, 105, ... will be described.

Further, the initial partial remainder determining circuit 100 can basically be configured as an array of cells in the case of q ₀ = 1 in the basic cell 470 or 510, similarly to the partial remainder determining circuits 101, 102, .... it can. Since the initial partial remainder determination circuit 100 is a redundant subtraction between normal binary numbers or a redundant addition of a normal binary number and a non-positive redundant binary number, the intermediate carry of each digit is always 0. And each cell can be simplified.

Next, quotient decision cells 201, 202, 203, 204, 2
The construction method of 05, ... Will be briefly described.

FIG. 5 shows each quotient determination cell 201, 20 in FIG.
It is a block diagram which shows the structural example of 2,203,204,205, ....

The quotient determining cell 550 (201, 202 ...) Is composed of a quotient determining circuit 551, a positive / negative inverting circuit 552, and a control signal determining circuit 553. Inputs 560, 561 and 5
62 is the first three digits of the partial remainder ▲ r ^j ₀ ▼, ▲ r ^j ₁ ▼, respectively.
And ▲ r ^j ₂ ▼, or ▲ a ^j ₀ ▼, ▲ a ^j ₁ ▼ and ▲
The input 563 is a 2-bit signal representing the value of a ^j ₂ ▼, and the input 563 is a 1-bit signal determined from the j-1 th digit q _j-1 below the quotient. The signal 564 is the jth digit q _j below the decimal point of the quotient.
Is a 2-bit signal representing a temporary value having a sign difference.
The output 565 is a 2-bit signal that represents the value of the j-th digit q _j below the decimal point of the quotient, and the output 566 is a 2-bit signal that controls the partial remainder determination circuits 101, 102 ....

The quotient decision circuit 551 uses the upper three digits 560, 56 of the partial remainder.
The values of 1 and 562 [▲ r ^j ₀ ▼, ▲ r ^j ₁ ▼ ▲ r ^j ₂ ▼]
SD2 or [▲ a ^j ₀ ▼, ▲ a ^j ₁ ▼ ▲ a ^j ₂ ▼] SD
2 is a circuit for determining a temporary value 564 of the j-th digit q _j below the decimal point of the quotient. That is, if the value of the upper 3 digits of the partial remainder is positive, the temporary value is 1, 0 if the temporary value is 0, and if negative, the temporary value is -1.

The positive / negative inverting circuit 552 can be omitted in the case of the above (I), and in the case of the above (II), the j-1th digit q _{j-1 after} the decimal point of the quotient.
It is a circuit that performs positive / negative inversion according to the value of and determines the j-th digit q _j below the decimal point of the quotient. That is, when q _j-1 = 1
Perform positive / negative inversion to replace 1 with -1 and -1 with 1.
When q _j-1 = -1,0, the value is output as it is.

In the case of (I), the control signal determination circuit 553 can omit the j-th digit q _j of the quotient as a control signal, and therefore can be omitted. In the case of (II), the magnitude of q _j and − q _j and −q
It is a circuit that determines whether or not there is a difference in the sign of _j-1 . In addition,
This circuit 553 has many parts in common with the quotient determination circuit 551, and normally, because the number of elements is deleted, these two circuits are put together and the common part is shared.

The above is the description of the configuration method of the quotient determination cell.

Next, a specific circuit realized according to the above configuration method will be described in the case of (II).

First, an example of binary coding for each signal is shown below.

Redundant binary representation of 1 digit ▲ a ^j _i ▼ or q _j is 2 bits ▲
a ^j _{i +} ▼ ▲ a ^j _i- ▼ or ▲ q _{j +} q _j- ▼, respectively, and binary-codes -1 for 11, 0 for 10, and 1 for 01. At this time, the magnitude and sign of the j-th digit q _j below the decimal point of the quotient can be represented by q _j- and q _{j +} , respectively. Also,
A signal indicating whether or not there is a difference in sign between the j-th digit q _j and the j−1-th digit q _j−1 below the decimal point of the quotient is designated as t _j . That is, if there is a difference in sign _{(sign (-q j) × sign} (-q j-1) = - 1
, T _j = 0, otherwise (when sign (−q _j ) × sign (−q _j−1 ) = 1), t _j = 1. Therefore, t _j is t _j = ▲ a ^j ₀₊ ▼ (▲ a ^j _0- ▼ + ▲ a ^j ₁₊ ▼) · (▲ a ^j _0- ▼ + ▲ a ^j _{1 in} the control signal determination circuit 553. _- ▼ ＋ ▲ a ^j ₂₊
▼) ・ (▲ a ^j _0- ▼ + ▲ a ^j _1- ▼ + ▲ a ^j _2- ▼ + q _{j-1 +} ) Further, q _j- and q _{j +} are respectively q _j- = ▲ a ^j _0- ▼ + ▲ a ^j _1- ▼ + ▲ a ^j _2- ▼ Can be determined by the formula. However, · is the logical product (AND),
+ Is a logical sum (OR), and is an exclusive logical sum (Ex-O
R) _Are operators that represent the logical negation of ▲ a ^j _i- ▼ + ▲ a ^j _{k +} ▼ and q _j- , respectively.

Furthermore, addition number at the first view ▲ d ^j _i ▼ 525, intermediate sum ▲ s ^j _i ▼ 526 and intermediate carry ▲ s ^j _i ▼ 527, respectively _{^{▲ d j i ▼ = y i}} · q j- ▲ s ^j _i ▼ = ▲ a ^j _{i + 1-} ▼ ▲ d ^j _i ▼ ▲ c ^j _i ▼ = (▲ a ^j _{i + 1-} ▼ t _j ) ・ ▲ a ^j _{i + 1-} ▼ + ▲ d ^j _i ▼・ It can be determined by the formula of ▲ ^j _{i + 1-} ▼. Also, the output of the basic cell 510 ▲ a
^{j + 1} _i ▼ is an expression of ▲ a ^{j + 1} _{i +} ▼ = ▲ s ^j _i ▼ + ▲ ^j _{i + 1} ▼ ▲ a ^{j + 1} _i- ▼ = ▲ s ^j _i ▼ ▲ c ^j _{i + 1} ▼ Can be determined by.

FIG. 6 shows the basic cell 5 of FIG. 1 obtained by the above binary coding.
An example of a circuit diagram in which 10 is realized by a CMOS circuit is shown. The gates 611 and 625 are Ex-OR, the gate 612 is an inverter, the gate 613 is a 2-input NOR, and the gate 631 is 2.
The input NAND gate 632 is an Ex-NOR gate. Also, p-channel transistor 621 and n-channel transistor 622, and p-channel transistor 623 and n-channel transistor 624.
Respectively constitute transfer gates.

Further, ▲ a ^j _{i + 1 +} ▼ 601 and ▲ a ^j _{i + 1-} ▼ 602 are 2-bit inputs 521 in FIG. 1, and the logical negation _i 603 of the _i- th digit y _i of the decimal point of the divisor is the first. This is an input 522 in the figure. _j- 604 and t _j 605 form the 2-bit control signal in FIG. Also ▲ d ^j _i ▼ 6
14 is the addition number 525 in FIG.
And 602 give information corresponding to the augend 542. Further, a signal ▲ ^j _i ▼ 626 representing an intermediate sum or a signal ▲ c ^j _i ▼ 627, ▲ c ^j _{i + 1} indicating the presence or absence of an intermediate carry.
▼ 628 is the 1-bit signal 52 in FIG.
6 or 527,528. Output ▲ a ^{j + 1} _{i +}
633 and ▲ a ^{j + 1} _i- ▼ 634 are 2-bit signals 529 representing the i-th digit after the decimal point of the partial remainder in FIG.

Further, the divisor conversion circuit 512 in FIG. 1 is a NOR gate 613, and the positive / negative inversion circuit 511 is an Ex-OR gate 61.
1 and the transfer gates 621 and 622, the core of the intermediate sum decision circuit 513 is Ex-OR 625, and the intermediate carry decision circuit 514 is the final sum decision by the inverters 612 transfer gates 621 and 622 and transfer gates 623 and 624. The circuit 515 includes a NAND gate 631 and an Ex-NOR gate 632.

In addition, although the transfer gate is used in this example,
It can also be realized by using a normal gate.

FIG. 7 is an example in which the partial circuit 700 using the transfer gate in FIG. 6 is configured by a NOR gate. Gates 701, 702 and 703 are both 2-input gates, in this case gates 701 and 612.
Represents a part of the positive / negative inversion circuit 511 in FIG. 1, and the gates 702 and 703 form an intermediate carry determination circuit 527. However, as shown in FIG. 7, since the number of stages and the number of elements of the circuit increase, a configuration using a composite gate is also possible.

Next, the implementation of the quotient decision cell 550 of FIG. 5 in a CMOS circuit will be described.

FIG. 8 shows a quotient determination cell 550 by the above-mentioned binary encoding.
FIG. 3 is a CMOS circuit diagram showing one example. In the figure, a gate 811 is an inverter, gates 813 and 823 are 2-input NORs, gates 814, 815 and 822 are 3-input NORs, and gates 812 and 821 are 4-input NOs.
The R gate 831 is an Ex-NOR gate.

Further, ▲ a ^j ₀₊ ▼ 801 and ▲ a ^j _0- ▼ 802 are 2-bit inputs 560 in FIG. 5, and ▲ a ^j ₁₊ ▼ 803
And ▲ a ^j _1- 804 are 2-bit inputs 561,
▲ a ^j ₂₊ ▼ 805 and ▲ a ^j _2- ▼ 806 are 2-bit inputs 562. Input q _{j-1 +} 807 is the input signal 563 from the upper quotient decision cell in FIG. The outputs q _{j +} 832 and _j- 833 are 2-bit signals 565 representing the j-th digit below the decimal point of the quotient, and the outputs _j- 833 and t _j 834 are 2-bit signals that control each basic cell 510 in the j-th stage. Is.

In addition, the quotient decision circuit 551 in FIG.
11, the NOR gates 813, 814, and 815, and the positive / negative inverting circuit 552 includes the NOR gate 82.
3 and Ex-NOR gate 831.
In addition, the control signal determination circuit 553 includes inverters 811 and N.
OR gates 812, 813, 814, 821, and 8
It is composed of 15. Inverters 811, N
The OR gates 813, 814 and 815 are commonly used by the quotient decision circuit 551 and the control signal decision circuit 553.

An example of implementation by the CMOS circuit in the case of (II) in this embodiment has been described above. In the above example, in the binary encoding, the partial remainders a ^j _i and the quotients q _j are assigned the same code, but different binary encodings may be performed. Similarly, in the case of (I), it can be easily realized by a CMOS circuit. Although only the addition of the redundant binary number and the normal binary number has been described in the present embodiment, the embodiment can be similarly created for the subtraction.

The basic cell shown in FIG. 6 is a 6-transistor Ex-O.
When using R and Ex-NOR, it is 32 transistors,
The number of gates on the critical path is three. In addition, in the quotient determination cell of FIG.
It is a transistor, and the number of gates in the critical path is two.

Further, in the present embodiment, the divider is realized by the binary logic of the CMOS circuit, but the present invention is not limited to other technologies (for example,
It can be easily realized by using NMOS, ECL, TTL, etc.) or multi-valued logic. Further, the present invention can be similarly implemented for the multiplier.

According to the present embodiment, the CMOS circuit is used as the divider to determine the quotient of about 50 transistors and the basic cell composed of elements of about 30 transistors, with a delay of about 5 gates per digit of quotient. Since it can be realized as a combinational circuit with a regular array structure of cells, compared with the conventional subtraction shift type divider using a sequential carry adder,
The number of transistors is about half, the calculation time (the number of stages of gates) is about 1/12 when divided by 32 bits, and about 1/24 of 64 bits. Further, the conventional binary binary adder / subtractor is used. The number of transistors is about half that of the subtractive shift type divider.

Therefore, it is effective in reducing the number of circuit elements of the divider, facilitating the formation of an LSI, and increasing the speed.

EFFECTS OF THE INVENTION According to the present invention, a redundant addition circuit of a redundant representation number such as an extended SD representation number and a binary representation number that allows a negative value for each digit, such as addition or subtraction that appears in an internal operation such as division or multiplication, or Since it can be realized as a combinational circuit with only one of the redundant subtraction circuits, and carry or borrow of each digit of addition and subtraction can propagate only at most one digit, (1) The number of elements of the arithmetic processing unit can be reduced. (2) Addition and subtraction can be processed at high speed in a fixed time regardless of the number of digits, so the speed of the arithmetic processing unit can be increased, and (3) LSI of the arithmetic processing unit can be implemented easily and economically. There is.

[Brief description of drawings]

1 and 4 are block diagrams showing the structure of a basic cell in the redundant addition cell shown in FIG. 3, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is FIG. 5 is a block diagram showing an example of the configuration of the partial remainder determination circuit of FIG. 5, FIG. 5 is a block diagram showing the structure of the quotient determination cell in FIG. 2, and FIG. 6 is a CMOS circuit diagram of the basic cell of FIG. 6 is a diagram for explaining the transfer gate of FIG. 6, and FIG. 8 is a CMOS circuit diagram of the quotient determination cell of FIG. 10 ...... R-adic conversion circuit, 20 ...... dividend, 40 ......
Divisor, 60 ... Quotient, 100 ... Initial partial remainder determination circuit,
101, 102, 103, 104, 105 ... Partial remainder determination circuit, 201, 202, 203, 204, 205 ...
... quotient decision cells, 310, 311, 312, 313 ...
Redundant addition cell, 470, 510 ... Basic cell, 472
...... Addition number determination circuit, 511 ... Positive / negative inversion circuit, 512
…… Divisor conversion circuit, 474,514 …… Intermediate carry determination circuit, 473,513 …… Intermediate sum determination circuit, 475,5
15 ... Final sum decision circuit, 551 ... Quotation decision circuit, 55
2 ... Positive / negative inverting circuit, 553 ... Control signal determining circuit.

Claims (8)

[Claims] 1. An arithmetic processing device comprising addition / subtraction means for performing addition or subtraction between a signed digit number and a binary number according to the value of a control signal, wherein the addition / subtraction means is arranged to (a) sign each digit. An intermediate carry (intermediate carry) determining means for inputting an attached digit number and a binary number and determining an intermediate carry (intermediate carry) in the addition (subtraction) thereof, and (b) the signed digit number An intermediate sum (intermediate difference) determining means for inputting the binary number and determining an intermediate sum (intermediate difference) in addition (subtraction) thereof; and (c) an intermediate sum obtained by the intermediate sum (intermediate difference) determining means. Determines the result of addition (subtraction) from the sum (intermediate difference) and the intermediate carry (intermediate carry) determined by the intermediate carry (intermediate carry) determination means provided in the lower digit of one digit. Then
Final sum (final difference) determining means for outputting as a number of signed digits, and (d) a control signal and a number of signed digits or a binary number are input, and the number of signed digits or a binary number is input according to the value of the control signal. An arithmetic processing unit, comprising: a sign inverting means for inverting the sign. 2. A constant setting means for inputting the control signal and the number of digits with a sign or a binary number and replacing the number of digits with a sign or the binary number with a constant and outputting the constant according to the value of the control signal. 2. The intermediate carry (borrow) borrow determining means and the intermediate sum (intermediate difference) determining means both use the output of the constant setting means as at least one common input. The arithmetic processing device described. 3. (f) The number of signed digits as an output of the final sum (final difference) determining means and the control signal are input, and the sign of the number of signed digits is inverted according to the value of the control signal. Final sum (final difference) sign inverting means, and both the intermediate carry (intermediate borrow) determining means and the intermediate sum (intermediate difference) determining means use the output of the sign inverting means as at least one common input. The arithmetic processing unit according to claim 1 or 2 characterized by the above-mentioned. 4. A binary number in which the sign inverting means and the constant setting means, depending on the value of the 2-bit control signal, input the binary number as it is, replace the binary number with 0, or invert the binary number. The arithmetic processing unit according to claim 2, wherein any one of the above is output. 5. The sign reversing means, depending on the value of the 1-bit control signal, keeps the input number of signed digits as it is or the number of signed digits obtained by inverting the positive and negative signs for each digit of the signed digit number. The arithmetic processing device according to claim 1 or 2, wherein the arithmetic processing device outputs. 6. The constant setting means outputs the input binary number as it is or by replacing the binary number with 0 according to the value of the 1-bit control signal, and outputs the binary number. Processing unit. 7. An intermediate carry (borrow) borrow determining means, an intermediate sum (intermediate difference) determining means, a final sum (final difference) determining means, and a sign inverting means each correspond to one digit of internal operation. The arithmetic processing unit according to claim 1, characterized in that the arithmetic processing unit comprises a plurality of cells and has an array structure of a plurality of the cells. 8. An intermediate carry (intermediate carry) deciding means, an intermediate sum (intermediate difference) deciding means, a final sum (final difference) deciding means, a sign inverting means and a constant setting means respectively for one digit of internal calculation. The arithmetic processing device according to claim 2, wherein the arithmetic processing device is configured by cells corresponding to the operation of (3) and has an array structure of a plurality of the cells.