JPH06230933A - Operation processor - Google Patents

Abstract

PURPOSE:To prevent the propagation of a carry value in internal addition/ subtraction, to simplify circuit constitution and to easily perform mounting to an LSI chip by performing conversion to a digit number with a code by performing subtraction by a subtraction means. CONSTITUTION:An intermediate partial product generator 110 obtains the product of a multiplicand and the digit of a multiplier recorded by a multiplier recorder 100 and generates an intermediate partial product. A redundant subtractor 120 subtracts the adjacent odd-numbered, that is, (2k+1)-th partial product generated at the intermediate partial product generator 110 from the even-numbered, that is, (2k)-th partial product generated at the intermediate partial product generator 110 and outputs the difference in the form of redundant binary numbers for which respective digits are any values of {-1, 0, +1.} A redundant adder 130 constitutes an addition tree and performs addition in the redundant binary system of general redundant binary numbers. A redundant binary/binary converter 140 converts the redundant binary number obtained as the product to a binary number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic operation processing device, and more particularly to a high speed operation processing device that includes addition and subtraction in internal operation and is suitable for LSI implementation.

[0002]

2. Description of the Related Art Conventionally, high-speed multipliers have been described in the Transactions of the Institute of Electronics and Communication Engineers, Vol.
Pages 690 to 690 discuss binary multipliers using redundant binary addition trees. In the multiplier using the redundant binary addition tree, the redundant binary expression (a kind of signed digit expression) in which each digit is an element of {-1,0,1} is used for internal calculation. In n-bit multiplication, n pieces of n-bit partial products are regarded as redundant binary numbers and are added to each other in a binary tree system in a redundant binary number system, and finally the product obtained by the redundant binary representation is converted into a normal binary product. Convert to binary representation. In the redundant binary number system, addition of two numbers can be performed in a constant time regardless of the number of digits of the operation number without propagation of carry. Therefore, in the multiplier using the redundant binary addition tree, n-bit multiplication can be performed at high speed with a calculation time of 0 (logn). The calculation speed is comparable to the high speed multiplier using the Wallace tree, which is considerably faster than the conventional array type multiplier. Moreover, the circuit structure is regular like the array type multiplier, and the layout is easier than the multiplier using the Wallace tree.

Further, in this multiplier, the 2-bit Booth
The amount of hardware can be reduced by applying the method. In the 2-bit Booth method, the number of partial products is reduced by recoding the multiplier to a digit number with a quaternary code (a quaternary number in which each digit is an element of {-2, -1, 0, 1, 2}). It can be halved to speed up the calculation and reduce the amount of hardware. At this time, in generation of the partial product, it is necessary to double the multiplicand and invert the sign. Double can be done by 1-bit left shift. Positive / negative inversion is performed by taking the 2's complement, or by utilizing the fact that the positive / negative inversion of the redundant binary number can be performed by the positive / negative inversion of each digit, the digit which is 1 in the multiplicand is -1. By doing.

[0004]

In the above prior art, the partial product can be easily generated, but since each digit of the partial product can be positive (that is, 1) or negative (that is, -1), the addition is performed. It was necessary to configure the entire tree with the same general redundant binary addition cells. Considering that the amount of hardware of each redundant binary addition cell is large (about 50 transistors), practical considerations such as reduction of the number of elements and simplification of the circuit configuration are not taken into consideration. When implemented as a combinational circuit, the number of elements becomes large and the circuit configuration becomes complicated when the number of digits of the number of operations becomes large, and the arithmetic processing unit is reduced to 1LS.
There are problems such as difficulty in mounting on an I-chip.

An object of the present invention is to improve such conventional problems, realize a multiplier as a combinational circuit having a regular circuit structure and a small number of elements, and prevent propagation of a carry value in internal addition / subtraction. Another object of the present invention is to provide a high-speed arithmetic processing device that can be easily mounted on an LSI chip by simplifying the circuit configuration.

[0006]

The object is to have subtraction means for inputting a dividend and a subtraction and generating a difference between them by a signed digit representation, wherein the subtraction means has two operation numbers (for example, This is achieved by converting each digit into a signed digit number, where each digit is a negative, zero, or positive value by subtracting the other from one.

[0007]

The difference can be generated in the form of a signed digit number by subtracting the other from one of the two calculated numbers (for example, a binary number). Since these two operands are both non-negative or non-positive in the corresponding digits, the redundant subtraction (that is,
Carrying (or borrowing) does not occur at all in the subtraction in which the result of the subtraction is represented by the signed digit expression with redundancy, and this subtracting means can be made a very simple circuit configuration. For example, in the case of a binary number, it can be configured very simply by exclusive OR and logical product (or logical NOT of logical OR). Therefore, as compared with the conventional method, after converting two operation numbers (for example, a binary number) into a signed digit representation, a subtraction operation is performed by a normal signed digit adder (subtractor). The amount of hardware can be reduced.

Further, in the arithmetic unit using the adder in the signed digit representation system, the subtraction operation and the conversion into the number of signed digits can be realized simultaneously by a circuit with a short delay,
The delay time (that is, execution time) in operations such as multiplication and division is reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a multiplier to which the present invention is applied.

The multiplier recoding circuit 100 has a 2-bit Boot
Each digit of the multiplier is {-2,-
It is a circuit for recoding to a digit number with a quaternary code which is any one of 1, 0, 1, 2}.

The intermediate partial product generator 110 is a circuit for obtaining an intermediate partial product from the product of the digit of the multiplier and the multiplicand recoded by the multiplier recorder 100.

Redundant subtractor 120 outputs even partial, ie, 2k-th (including 0) intermediate partial product generator 110 from partial products (where each digit is non-negative).
The odd number next to it, that is, the 2k + 1th intermediate partial product generator 1
The partial product (where each digit is non-negative) generated in 10 is subtracted, and the difference is output in the form of a redundant binary number in which each digit is one of {-1, 0, 1}. It is a circuit to do.

The redundant adder 130 is a circuit that constitutes an addition tree and is a circuit that performs addition in a redundant binary system of general redundant binary numbers.

The redundant binary / binary converter 140 is a circuit for converting a redundant binary number obtained as a product into a binary number, and can be easily realized by a carry lookahead adder or the like.

Next, the multiplier recoding circuit 100 will be described. In the two's complement display format, the multiplier Y can be expressed by (Equation 1). However, y _n is a sign bit, and y _n-1 , ..., Y ₁ is a numerical part. For the sake of simplicity, if the length n of Y is an even number, it can be expressed as (Equation 2). However, y ₀ = 0.

[0016]

[Equation 1]

[0017]

[Equation 2]

At this time, the multiplicand X is multiplied by X.Y.
Can be expressed by (Equation 3).

[0019]

[Equation 3]

That is, in the intermediate partial product, j is an even number (0
Also includes. ), (Y _2j + y _{2j + 1} -2y _{2j + 2} ) * X.2 ^2j , and when j is an odd number, (2y _{2j + 2-} y _{2j + 1} -y _2j ). ^X.22j . The final partial product is obtained by subtracting the intermediate partial product when j is an even number and the intermediate partial product when j is an odd number. Therefore, in the multiplier recoding circuit 100, when j is an even number, (Equation 4), and when j is an odd number, the multiplication factor of each digit b _j is {-2, -1, 0 according to (Equation 5). ,
Recode to a digit number with a quaternary code that is either 1, 2}.

[0021]

[Equation 4]

[0022]

[Equation 5]

A circuit (that is, a cell) forming the multiplier recoding circuit 100 will be described with reference to FIGS. First, the recoded multiplier (that is, the number of digits with a quaternary code)
An example of the binary signal conversion of is shown below. 3-bit binary signal showing recoded multiplier digit b _j in (Table 1)

[0024]

[Outer 1]

[0025]

[0026]

[Outside 2]

[0027]

[0028]

[Outside 3]

It is expressed by

[0030]

[Table 1]

When the binary signal is converted as described above, the jth digit b _j of the recoded multiplier in the multiplier recoding circuit 100 is determined by the following logical expression. However, j
Is an integer that takes a value from 0 to n / 2-1.

(I) When j is an even number (that is, j = 2k),
(Equation 6)

[0033]

[Equation 6]

(Ii) When j is an odd number (that is, j = 2k + 1), (Equation 7).

[0035]

[Equation 7]

[0036]

[Equation 8]

However, when j = 0, (Equation 8) can be easily obtained. In the above logical expression, · is the logical product (A
ND), + is a logical sum (OR),

[0038]

[Outside 4]

The exclusive OR (E _X -OR), - is an operator representing a logical NOT. FIG. 2 and FIG. 3 are examples of circuits forming the even digit part and the odd digit part of the multiplier recoding circuit 100 of FIG. 1, respectively. That is, the circuit shown in FIG. 2 is a circuit for generating an even digit b _2k of the recoded multiplier, and the circuit shown in FIG. 3 is an odd digit b ₂ of the recoded multiplier.
_This is a circuit that generates _{2k + 1} .

In FIG. 2, j is an even number (that is, 2k, where k is 0 or a positive integer), a gate 211 is an inverter circuit, a gate 212 is a NAND circuit, and a gate 2 is used.
21 is an AND-NOR composite gate, and gate 222 is an OR
-NAND composite gate, gate 223 is an exclusive OR circuit. Signals y _{2j + 2} 201, y _{2j + 1} 202, y _2j 203
Are respectively the 2j + 2th digit, the 2j + 1th digit, the 2nd digit of the multiplier Y.
It is a 1-bit binary signal representing j digits. However, j is an even number. Also the signal

[0041]

[Outside 5]

231,

[0043]

[Outside 6]

232,

[0045]

[Outside 7]

233 is the j-th digit b _j of the recoded multiplier
Is a 3-bit signal representing Signal

[0047]

[Outside 8]

Is generated by the circuit composed of the OR-NAND composite gate 222 and the inverter circuit 211,

[0049]

[Outside 9]

Is determined by the exclusive OR circuit 223, and the signal

[0051]

[Outside 10]

Is determined by a circuit composed of an AND-NOR composite gate 221 and an inverter circuit 211.

FIG. 3 is a recoding circuit diagram when j is an odd number (that is, 2k + 1). In the figure, gates 261 and 261
62, 272 and 273 are the inverter circuit 211, the NAND circuit 212, and the OR-NA in FIG.
Similar to the ND composite gate 222 and the exclusive OR circuit 223, the gates 263 and 273 are NOR circuits. Also, the signals y _{2j + 2} 251, y _{2j + 1} 252, y _2j 2
53 is the 2j + 2th digit, 2j + 1th digit, and
This is a 1-bit binary signal representing the 2j-th digit. However, j is an odd number. Further signal

[0054]

[Outside 11]

281,

[0056]

[Outside 12]

282

[0058]

[Outside 13]

283 is the j-th digit b _j of the recoded multiplier
Is a 3-bit signal representing In FIG. 3, the signal

[0060]

[Outside 14]

282 and

[0062]

[Outside 15]

The circuit that determines 283 is the same as that of FIG.

[0064]

[Outside 16]

281 is determined by a circuit formed of NOR circuits 263 and 271. Next, the intermediate partial product generator 110 will be described.

The intermediate partial product is -2 depending on the value of b _j.
It will be one of X, -X, 0, X and 2X. However, the weight 2 ^j is omitted. 2X means twice the multiplicand X. Twice the multiplicand X can be realized by shifting 1 bit, and can be easily made by a combinational circuit. On the other hand, the sign inversion of positive and negative is the logical negation (for each digit) of the multiplicand X in order to display the two's complement.

[0067]

[Outside 17]

Generate the

[0069]

[Outside 18]

One may be added to the least significant digit of. But,
If the operation of adding 1 is performed by the intermediate partial product generator 110, not only the amount of hardware increases but also a large amount of time is spent for generating partial products. Therefore,

[0071]

[Outside 19]

If the operation of adding 1 to the least significant digit is not performed by the intermediate partial product generator 110 and is added to the subsequent partial product adding section, the hardware can be increased and the speed can be increased. Further, in order to facilitate the operation of adding the correction term 1 in the redundant adder 130, the intermediate partial product generator 110 slightly calculates in advance including the correction (that is, adding 1) in the lower digit part. It is good to put it. Specifically, the intermediate partial product generator 110 may calculate the least significant one digit and perform correction (that is, addition of 1) to the second least significant digit.

At this time, the j-th digit b of the recoded multiplier
The i th digit of the intermediate partial product corresponding to _j is determined by (Equation 9).

[0074]

[Equation 9]

However, c ₂ represents a correction term to be added to the second digit, which is added in the addition tree portion. Note that z ₁ ,
The subscript j is omitted for both z _i and c ₂ .

FIG. 4 is an example of a circuit forming a portion corresponding to each of the intermediate digits (that is, the second digit to the nth digit) of the partial product in the intermediate partial product generator 110 of FIG. The figure shows a circuit for generating an _i- th digit z _i between the second digit and the n-th digit of the intermediate partial product corresponding to the j-th digit b _j of the recoded multiplier. In the figure, the gate 411 is AN
It is a D-NOR circuit, and the gate 421 is an exclusive NOR circuit. Also the signal

[0077]

[Outside 20]

401,

[0079]

[Outside 21]

402 and

[0081]

[Outside 22]

Reference numeral 403 is a 3-bit binary signal representing the j-th digit of the recoded multiplier. However, j is 0 to n / 2
It is an integer up to -1. The signal z _i 431 is a 1-bit binary signal representing the i-th digit of the intermediate partial product. However, i
Is an integer from 1 to n. Note that z ₁ , z _{n + 1} and c
A circuit for generating ₂ can be easily constructed.

Next, the redundant subtractor 120 will be described. In the subtractor 120, the subtraction value of the partial product corresponding to the odd digit b _{2k + 1} from the partial product corresponding to the even digit b _2k of the recoded multiplier is represented by a redundant binary number, and a carry ( Or borrowing) has been eliminated. Therefore, the circuit can be constructed very easily.

2-bit binary signal showing redundant binary digit r _i as shown in (Table 2)

[0085]

[Outside 23]

,

[0087]

[Outside 24]

Expressed as, the i-th digit of the subtraction in the redundant subtractor 120 is determined as shown in (Table 2).

[0089]

[Table 2]

For the i th digit z _i of the intermediate partial product corresponding to the even digit b _2k and the i-2 th digit w _i-2 of the intermediate partial product corresponding to the odd digit b _{2k + 1} , The i-th digit r _i of the subtraction value is
It is determined by (Equation 10).

[0091]

[Equation 10]

The subtraction of the i-2th digit w _i-2 of the intermediate partial product for odd-numbered digits b _{2k + 1} from the i-th digit z _i of the intermediate partial product for even-numbered digits b _2k is as follows: This is because the partial products are shifted by two digits (that is, the weight is 2 ² ) depending on whether b _j is even or odd. Also, z _{n + 3} , z
_{n + 2} can be determined as zn _{+ 3} = zn _{+ 1} and zn _{+ 2} = zn _{+ 1} .

FIG. 5 shows a circuit for redundant subtraction which constitutes the redundant subtractor 120 shown in FIG. 1, and has a minuend z _{i for} each digit _i.
An example of a circuit for performing the subtraction between the subtraction factor w _i and In the figure, a gate 511 is a NAND circuit, a gate 521 is an inverter circuit, and a gate 522 is an OR-NAND circuit.

[0094]

[Outside 25]

501 is an even-numbered (that is, b_2kAgainst
Z) is the i th digit of the intermediate partial product _iThe logical negation of
1 bit signal, signal w_i502 is an odd number
(That is, b_{2k + 1}I- of the intermediate partial product
It is a 1-bit signal that represents two digits. However, for i = 1, 2
For the reduction w_iSince it is always 0, the minuend z_iThat
The subtraction result may be used as it is. When i = n + 3,
Is the minuend z of the input signal_iAnd reduction w_iTo replace and
Therefore, the subtraction circuit of FIG. 5 can be used. Furthermore, the signal

[0096]

[Outside 26]

531 and

[0098]

[Outside 27]

Reference numeral 532 is a subtracted value, that is, a 2-bit binary signal representing the i-th digit r _i of the partial product (that is, redundant binary number) per 4 bits of the multiplier. In addition, instead of the circuit of FIG.
It is obvious that the subtraction circuit can be easily configured by the 2-input NOR circuit and the exclusive NOR circuit. Here, FIG.
The logical negation of the intermediate partial product digit z _i in

[0100]

[Outside 28]

501 can be easily obtained by replacing the exclusive NOR circuit 421 in FIG. 4 with an exclusive OR circuit without increasing the number of gate stages.

Further, the addition of the correction terms of the even-numbered intermediate partial products (that is, corresponding to b _2k ) is calculated at the time of performing the redundant subtraction, the addition in the addition tree is extremely difficult. To be easier. In other words, the addition of the second digit z ₂ of the even-numbered intermediate partial product and the correction term c ₂ is (Equation 11), (Equation 1)
Determined in 2). The second digit of the intermediate partial product is (Equation 1
1), and the correction term (that is, carry) t ₃ to the third digit becomes (Equation 12). The correction term t ₃ and the correction term −c ₂ for the second digit of the odd-numbered intermediate partial product can be easily added by the addition tree. However, since the odd-numbered intermediate partial product is subtracted from the even-numbered ones, the correction term rather than c _2, the -c _2.

[0103]

[Equation 11]

[0104]

[Equation 12]

Finally, the redundant adder 130 that forms the addition tree
Will be described. Table 3 shows an addition rule in which the carry propagation in the redundant adder 130 is at most one digit.

[0106]

[Table 3]

At this time, the i-th digit x of the augend_iAnd the addend of
i digit y_iSignal p that represents the combination state with _iIs derived by (Equation 13)
Enter this p_iUsing the intermediate carry c of (Table 3)_iand
Intermediate sum s_iA variable u that is related to_i, V_i
And intermediate sum s_iAbsolute value of

[0108]

[Outside 29]

Each can be determined by (Equation 15).
The final sum z _i is a 2-bit signal represented by (Equation 16).

[0110]

[Outside 30]

,

[0112]

[Outside 31]

Is given by

[0114]

[Equation 13]

[0115]

[Equation 14]

[0116]

[Equation 15]

[0117]

[Equation 16]

FIG. 6 is a circuit diagram showing an example of redundant adder 130 in FIG. In the figure, the gate 311 is NOR
Circuit, gates 312 and 351 are NAND circuits, gate 3
13 is an exclusive OR circuit, gate 332 is an exclusive NOR circuit, gate 352 is an inverter circuit, and gate 331 is A.
ND-NOR composite gate, gate 352 is OR-NAN
It is a D composite gate.

Also, the signal

[0120]

[Outside 32]

301 and

[0122]

[Outside 33]

302 is a 2-bit signal representing the i-th digit x _i of the redundant binary number which is the augend;

[0124]

[Outside 34]

303 and

[0126]

[Outside 35]

304 is the i-th row of the redundant binary number which is the addend

[0128]

[Outside 36]

2-bit signal representing 1-bit signal 321
Represents the augend and addend status signal p _i at the i-th digit, and the 1-bit signal 323 represents the augend and addend status signal p _i-1 at the i−1-th digit, 1 bit Signal 322
Is a signal representing the absolute value of the intermediate sum at the i-th digit

[0130]

[Outside 37]

It is The signal 341 is the signal v _i related to the intermediate carry at the i th digit, the signal 343 is the signal v _i-1 related to the intermediate carry from the i−1 th digit, and the signal 342 is the i th position. Logical negation signal of the signal u _i related to said intermediate sum in digits

[0132]

[Outside 38]

It is Output signal

[0134]

[Outside 39]

361 and

[0136]

[Outside 40]

362 is 2 which represents the i-th digit z _i of the final sum
It is a bit signal. In the circuit diagrams shown in FIGS. 2 to 6 above, the exclusive OR circuit in the drawings is replaced with an exclusive NOR circuit by various combinations with an inverter, or an NA is used.
An ND circuit is combined with an inverter to replace it with a NOR circuit, or a composite gate, an exclusive OR circuit, or the like is a NAND circuit,
Composed of NOR circuit or combination of inverters,
Alternatively, it is known that the reverse can easily be done.

Although the present embodiment is realized by the binary logic in consideration of the CMOS circuit, other technologies (for example, NM) are used.
(OS, ECL, TTL, IIL, etc.) or multi-valued logic can be easily used.

In this embodiment, the multiplier using the redundant binary addition tree has been described, but the present invention can be easily applied to the multiplier using the Wallace tree or the array type multiplier.

According to this embodiment, the number of partial products can be reduced by adding a redundant subtraction circuit having a simple structure to the conventional Boot.
The number can be reduced to about half compared with the case of the method of h. For example, in a multiplier using a redundant binary addition tree, the number of stages in the addition tree is reduced by one stage, so the delay required for execution is reduced by 2 to 3 gate stages, and There is an effect such as a reduction of about 40%.

[0141]

According to the present invention, by adding a subtracting means having a simple circuit configuration, it is possible to perform an operation that takes two operation numbers as an input and a conversion into a number of digits with a sign, and the number of operation units. Therefore, (1) the number of elements of the arithmetic processing unit can be reduced, (2) the speed of the arithmetic processing unit can be increased, (3) the circuit configuration can be relatively simplified, and (4) the LSI of the arithmetic processing unit.
It has the effect of making it easy and economical.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiplier to which an embodiment of the present invention is applied.

FIG. 2 is a circuit diagram of a circuit forming an even part of a multiplier recoding circuit.

FIG. 3 is a circuit diagram of a circuit forming an odd part of a multiplier recoding circuit.

FIG. 4 is a circuit diagram of a circuit forming an intermediate partial product generator.

FIG. 5 is a circuit diagram of a circuit forming a redundant subtractor.

FIG. 6 is a circuit diagram showing an addition cell forming a redundant adder.

[Explanation of symbols]

 100 multiplier recoding circuit 110 intermediate partial product generator 120 redundant subtractor 130 redundant adder 140 redundant binary / binary converter

Claims (5)

[Claims] 1. A subtraction means for inputting a dividend and a subtraction and generating a difference between them by a signed digit representation, wherein the subtracting means subtracts to convert into a signed digit number. An arithmetic processing unit. 2. A subtraction means for inputting a subtraction and a reduction, and generating a difference between them by a signed digit representation, and (b) at least a signed digit number output from the subtraction means. An arithmetic processing unit comprising: a signed digit addition means for inputting as one side and outputting a signed digit number; and a subtraction means for converting into a signed digit number. 3. An arithmetic operation characterized in that the subtracting means according to claim 1 or 2 has a means for inputting each digit of the subtracted number and the subtraction and generating a digit in which the difference between them is represented by a signed digit. Processing equipment. 4. The subtracting means according to claim 1 or 2,
An arithmetic processing unit characterized by inputting a minuend and a subtraction, each of which can represent each digit by 1 bit. 5. A means for inputting two operation numbers each of which can be represented by one bit and generating a number of signed digits, said means comprising: (a) one digit x _{i of} said two operation numbers; means for outputting their exclusive or information expressed by the logical negation to input y _i, expressed by a logical product or logical sum thereof to input (b) the two digit x _i, y _i An arithmetic processing unit comprising: means for outputting information or its logical NOT.