JP2682142B2 - Multiplier - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-speed multiplication circuit suitable for LSI implementation.

Prior art Multiplied X and multiplier Y are 24 digits including the sign digit,
It is assumed that it is expressed as shown in equations (1) and (2).

X = ₂₃ X ₂₂ X ₂₁ ...... X ₂ X ₁ X ₀ (1) Y = ₂₃ Y ₂₂ Y ₂₁ ...... Y ₂ Y ₁ Y ₀ (2) However, ₂₃ = -X ₂₃ , ₂₃ = -Y ₂₃ Conventional FIG. 4 shows a configuration diagram of a parallel multiplier using the 2-bit Booth recoding method of (1). First of all, the multiplier Y
Is input to the 2-bit Booth recoding circuit 450-461. Then, according to the equation (3), it is recoded into 12 multiplier recode values R _{0 to} R ₁₁ .

R _i = -2Y _{2i + 1} + Y _2i + Y _2i-1 (3) where i = 0-11, Y
_-1 = 0 That is, Ri takes the value shown in Expression (4).

-2 ≤ Ri ≤ 2 (4) Multiply by using the 2-bit Booth recoding circuit
XY is expressed as in equation (5).

That is, it can be seen from the expression (5) that the partial product number becomes 1/2 by using the 2-bit Booth recoding.
The twelve partial products XRi shown in the equation (5) are multiplied by the multiplier recoding values Ri (i = i = n) in the redundant binary partial product generation circuit 401-412.
0-11) is used. The redundant binary partial product generation circuits 401-412 will be described below. In the redundant binary number partial product generation circuit 401-412, the multiplier recode value Ri (i-0-11)
The operation represented by the equation (6) is performed according to

(However, ~ indicates minus.) From the equation (6), each digit of 12 partial products XRi is (-
It takes three values of 1, 0, 1). To express these three values,
It is necessary to use signed digit numbers. Here, a redundant binary number, which is one of the signed digit numbers, is used. Now, the redundant binary number RB is the sign digit Rbs and the absolute value Rba.
Are coded as shown in Table 1.

Also, the multiplier recode value Ri (-2 ≤ Ri ≤ 2) is the code digit
Rsi, a digit R1i indicating that the absolute value is 1 and a digit R2i indicating that the absolute value is 2 are coded as shown in Table 2.

At this time, when the value of the bit string lower k + 1 digit of the partial product XRi and _{P k (k = 0-23),} P k is used sign digit Ps _k and absolute value digit Pa _k, (7) as equation Expressed in.

The _{Ps k = Rsi Pa k = R1i} · X k + R2i · X k-1 (7) (7) logic diagram of equation shown in FIG. 5. That is, in the conventional example, the redundant binary partial product generation circuits 401-412 can be configured with two gate stages. Next, using each redundant binary number partial product output from the redundant binary number partial product generation circuit 401-412,
Redundant binary number addition circuits 413-423 execute addition.
The redundant binary number addition circuits 413-423 are circuits which add arbitrary two redundant binary numbers and output one redundant binary number result. Here, the configuration of the redundant binary number adding circuits 413-423 will be described. The two redundant binary numbers are M and N, and the addition rule is shown in Table 3.

In Table 3, Ci and Si are intermediate carry and intermediate sum when Mi + Ni is executed, respectively, and the relationship of Mi + Ni = 2Ci + Si is established. Here, in Table 3, Mi + Ni = (-
In case of 2, 0, 2), Ci and Si are uniquely determined. However, when Mi + Ni = (i, -1), Ci and Si are not uniquely determined, and there are two cases. Which of these two selection branches to select is determined by the addition value (Mi-1 +
Ni-1) selected. For example, Mi + Ni = 1
When the addition value (Mi-1 + Ni-1) one digit lower is positive,
The value of 0 or 1 increases as the carry C _i-1 from the one place lower. In order to prevent the carry from being propagated to the higher order in the redundant binary number, the case of taking a value of 0 or -1 is selected as Si. That is, in the case of this example, (Ci, Si) = (1, -1) is selected. In other cases, it may be selected so that the carry does not propagate. Thus, we obtain (Ci, Si),
Next, the addition result is obtained by executing C _i-1 + Si.

As described above, the redundant binary number adder determines the intermediate carry and the intermediate sum of the lower digit based on the information of the lower digit (whether the added value of the lower digit is positive or negative). A 2-input 1-output adder has been realized, which extends only to the upper digit of at most one digit. A circuit of a typical redundant binary adder is shown in FIG. Ms and Ns are M and N code digits respectively, and Ma and Na are M and N absolute value digits respectively. Pi is a signal that represents the information of that digit, and Ri is a signal that represents the carry from that digit. The addition result is output in the code digit Zs and the absolute value digit Za. It can be seen that the number of gate stages can be four. That is, each redundant binary number partial product output from the redundant binary number partial product generation circuit 401-412 is added in the form of a binary tree by the redundant binary number addition circuits 413-423, and the redundant binary number addition stage number is four stages. Get the redundant binary intermediate product Zrb. Then, the redundant binary number intermediate product Zrb is converted into a binary number by the redundant binary number-binary number conversion circuit 424, and X
Get the product Z of Y.

Problems to be Solved by the Invention Conventionally, in a conventional multiplication circuit using a 2-bit Booth recoding circuit and using a redundant binary number for internal operation,
A 2-bit Booth recoding circuit was used to generate a 1/2 redundant binary number partial product when 2-bit Booth was not used, and this was added in a binary tree form by a redundant binary number adder. . That is, for example, if the number of digits of the multiplier is N, N / 2 redundant binary partial products are generated, and these are added in a binary tree form. Therefore, multiplication proportional to approximately log ₂ (N / 2) is performed. It takes time, and the multiplication time becomes longer when the number of digits of the multiplier increases, which is a problem. In view of the above point, the present invention has an object to provide a high-speed multiplication circuit by generating N / 6 redundant binary partial products.

Means for Solving the Problems According to the present invention, a 2-bit Booth recoding circuit that divides a multiplier into a set of 2-bit bit strings and converts the set into a digit number with a quaternary code, and the digit number with a quaternary code. In a parallel multiplication circuit that internally has a binary partial product generation circuit that generates a binary partial product by multiplying the value of multiplicand by the value of the multiplicand, one binary digit number is added by adding three binary partial products. It is a multiplication device characterized in that a signed digit number partial product generating circuit for generating is provided inside.

With the above-described configuration, the present invention generates the partial product generated from the 2-bit Booth recode value of the multiplier and the multiplicand in parallel so that each digit of the partial product is represented by a binary number, and Using a redundant binary number partial product generation circuit for generating a redundant binary number partial product sequence of one column by adding each digit of the partial products of each set of three columns and forming a partial product into a group of three columns Thus, the multiplication time can be shortened.

Embodiment FIG. 1 is a circuit diagram of a redundant binary partial product generation circuit in an embodiment of the present invention. The redundant binary number partial product generation circuit is composed of binary number partial product generation circuits 101, 102 and 103 and a binary number partial product addition circuit 104. The binary partial product addition circuit 104 is a circuit that adds three binary numbers to generate one redundant binary number. First, the binary partial product generation circuit 10
1, 102, and 10 will be described. Multiplicand X and multiplier Y are
It is assumed that the data is 24-digit data having the code digit shown in the equations (1) and (2) at the highest place. The multiplication XY can be expressed as shown in equation (5) by using a 2-bit Booth recoding circuit. Equation (5) is shown again here.

In the present invention, twelve partial products (XRi) take the two's complement of X · | Ri | when Ri <0 as shown in the equation (8).

(However, - the logic inversion, ~ sign inversion) That is, if the Bp the value of each digit of (8) than, binary partial product XRi, the value Bp _k of k + 1 digit than the lower is
It becomes as shown in the equation (9).

However, X ₋₁ = 0, that is, from the equation (9), the binary partial product generation circuits 101, 1
It can be seen that 02 and 103 can be configured with two gate stages. Note that the correction term generated at the time of generating the two's complement shown in the equation (8) has
Add with 104. Next, the binary partial product addition circuit 104 will be described. This circuit is a binary partial product generation circuit 101, 1
This is a circuit that adds the outputs of 02 and 103 and outputs the addition result in a redundant binary number. FIG. 2 shows a method of adding three binary partial products to obtain a redundant binary number in the case of XR ₀ + XR ₁ + XR ₂ . Here, CT ₀ and CT ₁ are correction terms for XR ₀ and XR ₁ , respectively. The upper digits of XR ₀ and XR ₁ are sign-extended according to XR ₂ . Here, the binary partial product addition circuit 104
Are shown for the k + 1th digit from the lower order shown in the area 201. Bp _k, the addition of _{Bp k-2, Bp k-} 4 is performed in two steps as follows. In the first step, Bp _k, the _{Bp k-2, Bp k-} 4 are added by full adders to produce an intermediate carry C _k and intermediate sum S _k. The intermediate carry C _k and the intermediate sum S _k have the logic shown in equation (10).

S _k = Bp _k Bp _k-2 Bp _k-4 C _k = Bp _k · Bp _k-2 + Bp _k-2 · Bp _k-4 + Bp _k-4 · Bp _k (10) In the second step, intermediate carry Add C _k-1 and the intermediate sum S _k . In the present invention, assuming that the bit strings of the intermediate carry and the intermediate sum are C and S, respectively, the addition of the intermediate carry C and the intermediate sum S is performed as the subtraction of the two's complement of the intermediate carry C and the intermediate sum S. This is expressed as in equation (11).

(However, -indicates logical inversion to sign inversion.) Since the result of equation (11) is a binary subtraction from a binary number for each digit, each digit of equation (11) is {-1, It is a redundant binary number having a value of 0, 1}. Assuming that the addition result of the area 201 is Rp _k , Rp _k uses the sign digit Rp _sk and the absolute value digit Rpa _k , and (1
It is expressed by the logic shown in Equation 2).

Rp _sk = C _k-1 + S _k Rpa _k = C _k-1 S _k (12) Therefore, the binary partial product addition circuit 104 shown in FIG.
It is configured by the logic shown in the equations (10) and (12), and has four gate stages. From the above, the redundant binary partial product generation circuit shown in FIG. 1 of the present invention can be configured with six gate stages. This has more gate stages and more transistors than the redundant binary partial product generation circuit described in the conventional example. But,
Since the number of redundant binary partial products can be reduced to 1/3 of that of the conventional example, the number of addition stages of partial products is reduced, leading to a reduction in multiplication time. FIG. 3 shows a block diagram of a multiplication circuit utilizing the present invention. Multiplicand X and multiplier Y are (1), (2)
It is 24-digit data including the code digit shown in the formula. Multiplier Y
Is input to the 2-bit Booth recoding circuits 310, 311, 312, 313, and 12 multiplier recoding values R0-R1 according to the equation (3).
Converted to 1. The multiplier recode value R0-R11 is 3
Redundant binary partial product generation circuits 301, 30
Input to 2, 303 and 304, four redundant binary partial products are generated. The four redundant binary number partial products are added in parallel by the redundant binary number adding circuits 305 and 306, and further added by the redundant binary number adding circuit 307 to obtain the redundant binary number intermediate product Zrb.
Is found. And finally, the redundant binary-to-binary conversion circuit
At 308, Zrb is converted into the multiplication result Z. Here, the redundant binary number addition circuits 305, 306, 307 and the redundant binary number / binary number conversion circuit 308 are the same as the circuits described in the conventional example. Table 5 shows a comparison of the number of gate stages from the input of the redundant binary partial product generating circuit to the acquisition of the redundant binary intermediate product Zrb.

From Table 5, it can be seen that the use of the present invention, which has conventionally required 18 gates, is realized with 14 gates, and the multiplication execution time can be shortened. It is also possible to reduce the Tr number of the entire multiplier. Although the present invention has been described above by taking a redundant binary number as an example, the present invention is also effective for other signed digit numbers, and similar effects can be obtained.

As described above, according to the present invention, in the multiplication circuit using the 2-bit Booth recode circuit, the redundant binary partial product number can be reduced to 1/3 of the conventional example. Therefore, a high speed multiplication circuit can be configured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a signed digit number partial product generating circuit in one embodiment of the present invention, and FIG. 2 is a diagram showing an algorithm for realizing the binary number partial product generating circuit of FIG.
3 is a block diagram of a multiplier using the circuit shown in FIG. 1, FIG. 4 is a block diagram of a conventional multiplication circuit, FIG. 5 is a circuit diagram of a conventional redundant binary partial product generation circuit, and FIG. The figure is a circuit diagram of a conventional redundant binary number addition circuit. 101-103 ... Binary partial product generation circuit, 104 ... Binary partial product addition circuit, 301-304 ... Redundant binary partial product generation circuit, 305-307 ... Redundant binary addition circuit, 308 ... Redundancy Binary-to-binary conversion circuit, 310 to 313 ... 2-bit Booth recode circuit.

Claims (1)

(57) [Claims] 1. A 2-bit Booth recoding circuit for dividing a multiplier into a set of 2 bits each in a bit string and converting the set into a digit number with a quaternary code, and a value of the digit number with a quaternary code to the multiplicand. A signed digit number that adds three binary partial products in a parallel multiplication circuit that internally has a binary partial product generation circuit that multiplies a value to generate a binary partial product A multiplication device having a partial product generation circuit therein.