GB2130774A

GB2130774A - Circuits for operating on N-digit operands

Info

Publication number: GB2130774A
Application number: GB08330889A
Authority: GB
Inventors: Frederick A Ware
Original assignee: Hewlett Packard Co
Current assignee: HP Inc
Priority date: 1982-08-23
Filing date: 1983-11-18
Publication date: 1984-06-06
Also published as: JPH0467211B2; GB2130771B; JPH03228120A; DE3326388A1; JPH03228122A; GB8306208D0; JPH0366693B2; JPH03229321A; GB2127187A; GB2130771A; GB2130774B; JPH0467213B2; JPH03228121A; JPH0467212B2; GB8330889D0; JPS5957343A; GB8330888D0; GB2127187B; JPH0450614B2; JPH03229320A

Abstract

A priority encoder for an N-digit operand A(7) to A(0) enables one of tri-state buffers 30 in dependence on the most significant one bit of the operand. The enabled buffer 30 supplies a respective 3-bit code as the encoder output. <IMAGE>

Description

1

SPECIFICATION Circuits for operating on N-digit operands

GB 2 130 774 A 1 This invention is concerned with circuits for operating on N-digit operands, and especially with circuits for priority coding on N-digit operands. The invention is related to that disclosed in our co5 pending UK patent application no. 8306208.

The addition of two N-bit operands to form an N-bit result, often called "carry propagate addition", is a fundamental operation in digital processors. A variety of techniques have been developed to perform this operation.

A simple method for performing carry propagate addition is the ripple adder. The ripple adder requires relatively few transistors per bit, but it is usually a relatively slow technique. The ripple adder is 10 thus the technique against which other methods are often measured.

Figure 1 of the accompanying drawings shows a typical ripple adder cell. A(i) and B(i) are individual bits of the two operands to be added, Cin(i) is the carry-in signal from a previous adder cell, Cout(i) is the carryout signal from the illustrated cell, and Sum(i) is the sum signal of the illustrated cell. The carry-out signal of one cell is the carry-in signal to the next cell. Table 1, shown as a PASCAL- 15 like language program, summarizes the Boolean equations for the ripple adder method, where -± is the Boolean "OR", "' is the Boolean "AND", and -XOR" is the Boolean "Exclusive-OR".

Table 1

For i=0 to N-1 (N bit adder) DO BEGIN KM=AM+130) 20 G0)=AM BM PM=AM XOR BM Cout(i)=GO) + [K(i) Cin(W=Cin(i+l) Surn(i)=PM XOR Cin(i) End 25 The ripple adder may be sped up with the addition of "carry look ahead- circuitry. To implement a carry look ahead adder, the ripple adder cells are organized into blocks of, for example, four ripple adder cells. Each block of four ripple adder cells, as shown in Figure 2 of the accompanying drawings, is provided with additional gates which allow carry propagation across the entire block if the 'W' bits are all 1 (i.e., the outputs of the OR gates K(ffi. The carry look ahead adder is moderately fast and is 30 economical to implement in MOS circuitry.

Another scheme is the "conditional sum" adder reported by Sklansky, "Conditional-Sum Addition Logic", I.R.E. Transactions on Electronic Computers, page 226, June 1960, Although very fast in operation, conditional sum addition takes far more logic to implement than the other, slower techniques discussed above. The result is that conditional sum addition has a very high cost per bit. In 35 practice, this technique has not enjoyed widespread usage.

Thus, several methods for performing N-bit addition have been used in the prior art. However, these known methods are often either too siow for the new generations of computers or they are substantially more complex and costly than is desirable.

In our co-pending UK application no. 8306208, there is disclosed a circuit for the addition of two 40 N-digit operands comprising a plurality of cells each coupled to one pair of digits, one digit of said pair from each of said operands, said cells comprising input means for accepting one digit of each of said two N-digit operands; first carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; 45 second carry-in means for accepting a carry-in signal for the plurality of cells; and summation output means for combining the carry-in signal, the output of said second carrying means and the output of said input means to produce an output summation digit.

The present invention provides a circuit for priority encoding an N-digit operand comprising a plurality of cells each coupled to one digit of said operand, said cells each coupled to one digit of said 50 operand, said cells comprising input means for accepting one digit of said N-digit operand; enable-in means for accepting an intermediate enable-in signal from the prior cell with the output of said input means and producing an intermediate enable-out signal for use by the next succeeding cell; and priority encoder output means for combining the intermediate enable-in signal and the output of said input means to produce an output priority encoder digit.

The cells of the plurality of cells are preferably serially coupled.

There now follows a detailed description, which is to be read with reference to Figures 5 and 6 of the accompanying drawings, of a priority encoder circuit according to the invention. Figures 3A, 3B and 4 correspond to Figures 3A, 3B and 4 of the drawings of our co-pending UK application no. 8306208 and are included together with the description thereof for the purpose of facilitating understanding of 60

2 GB 2 130 774 A 2 the present invention. The circuit illustrated in Figures 5 and 6 has been selected for description to illustrate the invention by way of example and not by way of limitation.

In Figures 3A to 6 of the accompanying drawings Figures 3A and 3B show a conditional carry adder "A"; Figure 4 shows the organization of a complete 8-bit conditional carry adder "B".

Figure 5 shows a complete 8-bit to 3-bit priority encoder using the conditional carry adder "B" technique; and Figure 6 shows the cells used for producing a priority encoder using the conditional carry adder "A" technique.

In Figures 3A, 3B and 4, there are disclosed two embodiments of a technique for performing N bit addition which are called the "conditional carry" adder. Both of these techniques, "A" and "B", can 10 also be applied to priority encoders, according to the present invention, as well as adders. As can be seen in Table 2, the conditional carrv adder compares favorably to the previously known techniques. In Table 2 adder speed is stated in terms of the number of gate delays required for the total addition. The data shown is for a 32-bit adder. J Figures 3A and 3B show the first adder, namely the conditional carry adder "A", and Table 3 15 presents the related Boolean equations. The three different cell types are shown in Figure 3A, a "start" cell, zero to any number of "continue" cells, and an "end" cell. Figure 3B shows how these cells are arranged to form, for example, a 9-bit adder. In this example each block contains between two and four one-bit cells, with two cells in block 0, three cells in block 1, and four cells in block 2. Thus, for example, in the second block (j=1), where there are three cells, bit number 2 is a start cell, bit number 20 3 is a continue cell, and bit number 4 is an end cell.

Table 2

Number of devices Total per bit number 25 of Static Static Method for performing addition delays NMOS CMOs Ripple adder 33 20 26 Carry look ahead adder 16 24 32 Conditional sum adder 14 72 104 30 Conditional carry adder-A 12 28 38 Conditional carry adder-B 8 36 52 For the whole adder:

Table 3

Cinblock (0)=Cinadder 35 For each block J:

C1n00=0 Ciril 0=1 Coutblock(j)=CoutO(imax) + [Coutl (imax) Ciriblock(D1 t =Cinblock(j+l) 40 _rl For each bit i of block j: KM=Affi + B0) G0)=AM B0) P(i)=A(i) XOR B(i) CoutOM=GO) + [0) CinOMI=CinO (i+l) 45 Coutl (i)=G(i) + [K(i) Cin 1 (i)I=Cin 1 fl+ 1) Cin(i)=CinO(i) + [Cin 1 (i) Cinblock (j)l Sum(i)=P(i) XOR Cin(i) Fundamentally, each block, j=0-2 in the example, generates two ripple carry output signals CoutOM and Coutl (i). Note that the CinO and Ciril for the start cell of each block is defined as 0 and 1 50 respectively. The Cout signals are combined with the carry-in signal to the current block Cinblock(j) to - produce the carry-out signal of the current block Coutblock(j). All of the blocks j=0-2 begin rippling their two carry chains at the same time. Block 0 produces its carry-out signal first and passes it on to block 1. Thereafter, only one gate delay is required for the carry to "jump" across each block. Since the block size increases as an arithmetic progression (i.e., 2, 3, 4 and so forth) the total delay is approximately proportional to the square root of the number of bits to be added. Thus, the conditional carry adder -A- gives 25% better performance than the carry look adder with only a 17% increase in f.

4 -A N=Bits in adder 10 For i=0 to (N-1) DO BEGIN Cout0(0,0=AM B(i)=G(i) Coutl (0,i)=A(i) + B0)=K0) P(i)=Affi XOR B0) End 15 For j=1 to LOG2(N) DO BEGIN W=2j For K=0 to (N/W -1) DO BEGIN LO=KW + W/2 L 1 =WW + W/2) 20 L2=(KW + W) 3 GB 2 130 774 A 3 the number of devices per bit. Also, the conditional carry adder -A- can be implemented with one-bit cells, rather than cells which stretch across multiple bits as in other high speed techniques. This permits an ordered integrated circuit layout which is easy and space-efficient to implement.

The second adder, the conditional carry adder "B", is shown in Figure 4 and the related Boolean equations are shown in Table 4. Note that Table 4 is shown as a PASCAL- like language program for any length adder and "2j" is equivalent to 2 raised to the jth power. The design is similar to the conditional carry adder "A" (Figures 3A and 313) and in similar fashion the inputs are assumed to be CinO=1 and Ciril =1 and the carry-out signals are computed accordingly.

Table 4

For i=(L0) to (L1 -1) DO BEGIN Couto(jj)=Couto(j-1J) Coutl (j,l)=Coutl (jl,i) End 25 For i=(L1) to (L2-1) DO BEGIN Couto(jJ)=Couffi(j-1J) + [Couti (j-JJ) CoutO(j-1), L1 -l)] Coutl (j,i)=couto(j-l,i) + [Coutl 0-11,0 Coutl (j-2), L1 -M 30 End End Cin(O)=CinAdder, K=LOG2N For i=0 to (W 1) DO BEG] N 35 D(i)=P(i) XOR Cin(i) Cin(l+ l)=CoutO(KJ) + [Coutl (K,i) CinADDERI End CoutADDER=Cin(N) In Figure 4 each stage generates the carry-out signals for each bit Cout0(jJ) and Cout(jj) assuming that the carry-in signals to that bit are zero and one respectively, where "j" is the stage number and -i- is the bit number. The object is to generate the carry-in signals for each bit as if the carry-in signals to the entire block of bits are a one and a zero respectively. The successive stages perform this function, as well as generating the carry-out signals for the block, Coutl and CoutO.

Figure 4 shows that when the final carry-in signals for each bit are generated, the carry-in signal 45 for the adder selects the correct carry-in signals for each bit, and Cin is exciusive-ORed with the appropriate P-bit P(O-7) to produce the final sum D(O-7).

As can be seen from Figure 4 the major difference between embodiment "B" and embodiment W' is that in "B" the block sizes increase as powers of two, which forms a geometric progression whereas the block size of embodiment -A- forms an arithmetic progression as discussed above. The 50 4 GB 2 130 774 A 4 total delay in embodiment "B" is thus proportional to the logarithm to the base two of the number of bits to be added.

The technique of both adders "A" and "B" can be adapted to produce a priority encoder. A priority encoder is a device that encodes the highest priority input of N bits to a coded output having fewer than N bits to which a numerical weight has been assigned (e.g., an eight-digit to three-digit 5 encoder or a 1 0-digit to 4-digit encoder).

Figure 5 shows an eight-digit to three-digit priority encoder using the conditional carry---W technique. As with the increments discussed above the B(O-7) inputs are set to zero and the carry-in signal is set to 1. Note that in this embodiment the carry-in signal is shown as an "enable" and has been inverted for convenience as ENABLE-0. Tristate buffers 30 have been included in each output cell which are enabled by the corresponding gates 40. The logic elements in the first four rows ensure that the only buffers 30 which will be enabled correspond to the most significant bit in the input operand having a value equal to one. The inputs to each tri-state buffer 30 in each output cell are hard wired to the appropriately binary weighted signals corresponding to the bit number of the respective operand inputs. Thus, for a three digit output each of the buffers 30 is formed by three buffers wired in parallel to form three output ENCODE lines. The tri-state buffers 30 in the A(O) column are then set to 0,0,0 the buffers 30 in the AM column are set to 0,0,1 and so forth up to the buffers 30 in the A(7) column being set to 1JJ. The eight buffers 30 (one from each column) corresponding to the least significant inputs are then wired together to form the ENCODE(O) output, the eight buffers 30 (one from each column) corresponding to the intermediate weighted inputs are wired together to form the ENCODE(1) 20 output, and the eight buffers 30 (one from each column) corresponding to the most significant inputs are wired together to form the ENCODE(2) output. Hence, the three encode lines provide the properly weighted outputs to perform the 8-bit to 3-bit encoder function and the properly enabled buffers provide the required priority corresponding to the most significant one in the input word. The technique for removal of redundant gates, along with the addition of the appropriate number of tri-state buffers 25 per bit can be used as shown in Figure 6 to create a priority encoder "A" based on the conditional carry adder -A- of Figure 3A. The Continue cell of Figure 6 can be used as many times as needed in each block.

Claims

1. A circuit for priority encoding an N-digit operand comprising a plurality of cells each coupled to 30 one digit of said operand, said cells comprising:

input means for accepting one digit of said N-digit operand; enable-in means for accepting an intermediate enable-in signal from a prior cell; enable-out means for combining the intermediate enable-in signal from the prior cell with the output of said input means and producing an intermediate enable-out signal for use by the next 35 succeeding cell; and priority encoder output means for combining the intermediate enable-in signal and the output of said input means to produce an output priority encoder digit.

2. A circuit according to claim 1 wherein the cells of said plurality of cells are serially coupled.

3. A circuit for priority encoding an N-digit operand substantially as hereinbefore described with reference to Figures 5 and 6 of the accompanying drawings.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1984. Published by the Patent Office, Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.

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