GB2127187A - Circuits for operating on N- digit operands - Google Patents

Abstract

A conditional carry adder for two N-digit operands is formed by blocks of cells. Each block receives a carry C IN BL0CK (j) from the preceding block and each cell receives two carries C IN 0(i) and C IN 1(i) from the preceding cell and provides the two carries to the next cell and a sum digit SUM(i). In addition, the technique is shown adapted for use as either an incrementer or as a priority encoder. <IMAGE>

Description

SPECIFICATION Circuits for operating on N-digit operands This invention is concerned with circuits for operating on N-digit operands.

The addition of two N-bit operands to form an N-bit result, often called "carry propagate addition", is a fundamental operation in digital processors. A variety of techniques have been developed to perform this operation.

A simple method for performing carry propagate addition is the ripple adder. The rippler adder requires relatively few transistors per bit, but it is usually a relatively slow technique. The ripple adder is thus the technique against which other methods are often measured.

Figure 1 of the accompanying drawings shows a typical ripple adder cell. A(i) and B(i) are individual bits of the two operands to be added Cin(i) is the carry-in signal from a previous adder cell, Cout(i) is the carry-out signal from the illustrated cell, the Sum(i) is the sum signal of the illustrated cell. The carry-out signal of one cell is the carry-in signal to the next cell.Table 1, shown as a PASCAL-like language problem, summarizes the Boolean equations for the ripple adder method, where "+" is the Boolean "OR", """ is the Boolean "AND", and "XOR" is the Boolean "Exclusive-OR": TABLE 1 1 For i = 0 through N - 1 (Nbit adder) DO BEGIN K(i) = A(i) + B(i) G(i) = A(i) * B(i) P(i) = A(i) XOR B(i) Cout(i) = G(i) + [ K(i) * Cin(i) ] = Cin(i + 1) Sum(i) = P(i) XOR Cin(i) End The ripple adder may be sped up with the addition of "carry look ahead" circuitry. To implement a carry look ahead adder, the ripple adder cells are organized into blocks of, for example, four ripple adder cells.Each block of four ripple adder cells, as shown in Fig. 2 of the accompanying drawings, is provided with additional gates which allow carry propagation across the entire block if the "K" bits are all 1 (i.e., the outputs of the OR gates K(i)). The carry look ahead adder is moderately fast and is economical to implement in MOS circuitry.

Another scheme is the "conditional sum" adder reported by Sklansky, "Conditional-Sum Addition Logic", l.R.E. Transactions on Electronic Computers, page 226, June 1960. Although very fast in operation, conditional sum addition takes far more logic to implement than the other, slower techniques discussed above. The result is that conditional sum addition has a very high cost per bit. In practice, this technique has not enjoyed widespread usage.

Thus, several methods for performing N-bit addition have been used in the prior art. However, these known methods are ofter either too slow for the new generations of computers or they are substantially more complex and costly than is desirable.

The present invention provides a circuit for the addition of two N-digit operands comprising a plurality of cells each coupled to one pair of digits, one digit of said pair from each of said operands, said cells comprising input means for accepting one digit of each of said two N-digit operands; first carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; second carry-in means for accepting a carry-in signal for the plurality of cells; and summation output means for combining the carry-in signal, the output of said second carryin means and the output of said input means to produce an output summation digit.

The present invention further provides a circuit for incrementing an N-digit operand comprising a plurality of cells each coupled to one digit of said operand, said cells comprising input means for accepting one digit of said N-digit operand; carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; and incrementer output means for combining the intermediate carry-in signal and the output of said input means to produce an output incrementer digit.

The present invention further provides a circuit for priority encoding an N-digit operand comprising a plurality of cells each coupled to one digit of said operand, said cells comprising input means for accepting one digit of said N-digit operand; enable-in means for accepting an intermediate enable-in signal from a prior cell; enable-out means for combining the intermediate enable-in signal from the prior cell with the output of said input means and producing an intermediate enable-out signal for use by the next succeeding cell; and priority encoder output means for combining the intermediate enable-in signal and the output of said input means to produce an output priority encoder digit.

The plurality of cells are preferably serially coupled.

Two preferred embodiments of a new and novel circuit are disclosed for the conditional carry addition of two N-digit operands. The adder is organized as a series of cells which generate intermediate carry signals. These intermediate carry signals for each pair of bits can then ripple independently through subsequent stages so that the time delay of the entire adder will be substantially reduced over the prior art, while at the same time the circuit complexity can be kept relatively low. This technique is also shown adapted to produce either an incrementer or a priority encoder.

Since the technique is based on a relatively small number of cell types, the cells can readily be combined in an ordered manner as shown to produce an adder, incrementer, or priority encoder of any length. Thus, not only is it possible to produce a circuit with high absolute speed, it is also possible to produce a device with low design complexity and cost when implemented in LSI by either bipolar or MOS techniques.

There now follows a detailed description which is to be read with reference to Figs. 3A to 8 of the accompanying drawings of several circuits according to the present invention; it is to be clearly understood that these circuits have been selected for description to illustrate the invention by way of example and not by way of limitation.

In the accompanying drawings:~ Figures 3A and 3B show the first embodiment of the present invention, the conditional carry adder "A"; Figure 4 shows the organization of a complete 8-bit conditional carry adder "B"; Figure 4 shows an 8-bit incrementer using the conditional carry adder "B" technique; Figure 6 shows the cells used for producing an incrementer using the conditional carry adder "A" technique; Figure 7 shows a complete 8-bit to 3-bit priority encoder using the conditional carry adder "B" technique; and Figure 8 shows the cells used for producing a priority encoder using the conditional carry adder "A" technique.

The present invention discloses two embodiments of a new and novel technique for performing N-bit addition which are called the "conditional carry" adder. Both of these techniques, "A" and "B", can also be applied to incrementers and priority encoders as well as adders as will be shown. As can be seen in Table 2, the conditional carry adder compares favorably to the previously known techniques. In Table 2 adder speed is stated in terms of the number of gate delays required for the total addition. The data shown is for a 32-bit adder.

Figs. 3A and 3B show the first embodiment of the claimed invention, the conditional carry adder "A", and Table 3 presents the related Boolean equations. The three different cell types are shown in Fig. 3A: A "start" cell, zero to any number of "continue" cells, and an "end" cell. Fig. 3B shows how these cells are arranged to form for example, a 9-bit adder. In this example each block contains between two and four one-bit cells, with two cells in block 0, three cells in block 1, and four cells in block 2. Thus, for example, in the second block ( = 1), where there are three cells, bit number 2 is a start cell, bit number 3 is a continue cell, and bit number 4 is an end cell.

TABLE 2 Total Number of Number of Method For Number Devices Per Bit Devices Per Bit Performing Addition of Delays Static NMOS Static CMOS Ripple Adder 33 20 26 Carry Look Ahead Adder 16 24 32 Conditional Sum Adder 14 72 104 Conditional Carry Adder-A 12 28 38 Conditional Carry Adder-B 8 36 52 TABLE 3 For the whole adder: Cinblock (O) = Cinadder For each block j: Cin0(0) = O Cin1(0)= 1 Coutblock (j)= Cout0(imax) + [ Cout(imax)*Cinblock(j) ] = Cinblock(j + 1) For each bit i of block j:: K(i) = A(i) + B(i) G(i) = A(i) * B(i) P(i) = A(i) XOR B(i) Cout0(i) = G(i) + [ K(i) * Cin0(i) ] = CinO(i + 1) Coutl (i) = G(i)#K(i) * Cin1 ] = Cinl(i)l = Cin1 (i + 1) Cin(i) = Cin0(i) + [ Cinl(i) * Cinblock(j) ] Sum(i)= P(i) XOR Cin(i) Fundamentally, each block j = 0 - 2 in the example, generates two ripple carry output signals CoutO(i) and Cout1 (i). Note that the CinO and Cin1 for the start cell of each block is defined as O and 1 respectively. The Cout signals are combined with the carry-in signal to the current block Cinblock(j) to produce the carry-out signal of the current block Coutblock(j).All of the blocks j = O~2 begin rippling their two carry chains at the same time. Block O produces its carry-out signal first and passes it on to block 1. Thereafter, only one gate delay is required for the carry to "jump" across each block. Since the block size increases as an arithmetic progression (i.e., 2, 3, 4 and so forth), the total delay is approximately proportional to the square root of the number of bits to be added. Thus, the conditional carry adder "A" gives 25% better performance than the carry look adder with only a 17% increase in the number of devices per bit. Also, the conditional carry adder "A" can be implemented with one-bit cells, rather than cells which stretch across multiple bits as in other high speed techniques.This permits an ordered integrated circuit layout which is easy and space-efficient to implement.

The second embodiment of the invention, the conditional carry adder "B", is shown in Fig. 4 and the related Boolean equations are shown in Table 4. Note that Table 4 is shown as a PASCAL-like language program for any length adder and "2**j" is equivalent to 2 raised to the jth power. The design is similar to the conditional carry adder "A" (Figs. 3A and 3B) and in similar fashion the inputs are assumed to be CinO = 1 and Cin1 = 1 and the carry-out signals are computed accordingly.

TABLE 4 N = Bits in Adder For i = 0 thru (N - 1) DO BEGIN Cout0(0,i) = A(i) * B(i) = G(i) Couti (0,i) = A(i) + B(i) = K(i) P(i) = A(i) XOR B(i) End For j = 1 thru LG02(n) DO BEGIN W = 2**j For K=Othru (N/W - 1) DO BEGIN LO = K*W L1 = (K*W + W/2) L2 = (K*W + W) For i = (LO) thru (Li - 1) DO BEGIN Cout0(j,i) = Cout0(j - 1, i) Couti(j,i)=Couti(j- 1, i) End For i = (L1) thru (L2 - 1) DO BEGIN Cout0(j,i) = CoutO(j - 1, i) + #Couti (j - 1, i) * Cout0(j - 1), Li - 1 ] Cout1(j,1)=Cout0(j-1,i)+[Cout1(j-1,i)*Cout1(j-2),L1-1] End End Cin(0) = CinAdder K = LOG2(N) For i = 0 thru (N - 1) DO BEGIN D(i)= P(i) XOR Cin(i) Cin(i + 1) = CoutO(K,i) + [ Cout(K,i) * CinADDER# End CoutADDER = Cin(N) In Fig. 4 each stage generates the carry-out signals for each bit CoutO(j,i) and Cout(j,i) assuming that the carry-in signals to that bit are zero and one respectively, where "j" is the stage number and "i" is the bit number.The object is to generate the carry-in signals for each bit as if the carry-in signals to the entire block of bits are a one and a sero respectively. The successive stages perform this function, as well as generating the carry-out signals for the block, Cout1 and CoutO.

Fig. 4 shows that when the final carry-in signals for each bit are generated, the carry-in signal for the adder selects the correct carry-in signal for each bit, and Cin is exclusive-ORed with the appropriate P-bit P(O-7) to produce the final sum D(O-7).

As can be seen from Fig. 4 the major difference between embodiment "B" and embodiment "A" is that in "B" the block sizes increase as powers of two, which forms a geometric progression whereas the block size of embodiment "A" forms an arithmetic progression as discussed above. The total delay in embodiment "B" is thus proportional to the logarithm to the base two of the number of bits to be added.

The technique of both adders "A" and "B" can be adapted to produce both an incrementer or a priority encoder. An incrementer is a device for adding 1 to a prior N-bit number; and a priority encoder is a device that encodes the highest priority input of N bits to a coded output having fewer than N bits to which a numerical weight has been assigned (e.g., an eight-digit to three-digit encoder or a 10-digit to 4-digit encoder).

Fig. 4 shows an incrementer using the conditional carry "B" technique. Since none of the B(0-7) inputs are used in an incrementer, they can be set to zero and when B = 0: K=A* B=O G=A+B=A P+AXOR B=A In like fashion the Cin signal can be set to 1 for an incrementer if the incrementer is always to be enabled. Thus, all of the logically redundant gates can be removed from the conditional carry adder "B" shown in Fig. 4 to form an incrementer "B" as shown in Fig. 5. This same technique for removal of redundant gates can be used as shown in Fig. 6 to create an incrementer "A" based on the conditional carry adder "A" of Fig. 3A. As with the adder of Figs. 3A and 3B the Continue cell of Fig. 6 can be used many times as needed in each block.

Fig. 7 shows an eight-digit to three-digit priority encoder using the conditional carry "B" technique. As with the incrementers discussed above the B(0-7) inputs are set to zero and the carry-in signal is set to 1. Note that in this embodiment the carry-in signal is shown as an "enable" and has been inverted for convenience as ENABLE = O. Tri-state buffers 30 have been included in each output cell which are enabled by the corresponding gates 40. The logic elements in the first four rows ensure that the only buffers 30 which will be enabled correspond to the most significant bit in the input operand having a value equal to one. The inputs to each tri-state buffer 30 in each output cell are hard wired to the appropriately binary weighted signals corresponding to the bit number of the respective operand inputs.Thus, for a three digit output each of the buffers 30 is formed by three buffers wired in parallel to form three output ENCODE lines. The tri-state buffers 30 in the A(O) column are then set to 0,0,0 the buffers 30 in the A(i) column are set to 0,0,1 and so forth up to the buffers 30 in the A(7) column being set to 1,1,1 The eight buffers 30 (one from each column) corresponding to the least significant inputs are then wired together to form the ENCODE(0) output, the eight buffers 30 (one from each column) corresponding to the intermediate weighted inputs are wired together to form the ENCODE(1) output, and the eight buffers 30 (one from each column) corresponding to the most significant inputs are wired together to form the ENCODE(2) output. Hence, the three encode lines provide the properly weighted outputs to perform the 8-bit to 3-bit encoder function and the properly enabled buffers provide the required priority corresponding to the most significant one in the input word. As with the incrementers discussed above the technique for removal of redundant gates, along with the addition of the appropriate number tri-state buffers per bit can be used as shown in Fig. 8 to create a priority encoder "A" based on the conditional carry adder "A" of Fig. 3A. Once again the Continue cell of Fig. 8 can be used many times as needed in each block.

Claims (3)

1. A circuit for the addition of two N-digit operands comprising a plurality of cells each coupled to one pair of digits, one digit of said pair from each of said operands, said cells comprising: input means for accepting one digit of each of said two N-digit operands; first carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; second carry-in means for accepting a carry-in signal for the plurality of cells; and summation output means for combining the carry-in signal, the output of said second carry-in means and the output of said input means to produce an output summation digit.

2. A circuit for incrementing an N-digit operand comprising a plurality of cells each coupled to one digit of said operand, said cells comprising: input means for accepting one digit of said N-digit operand; carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; and incrementer output means for combining the intermediate carry-in signal and the output of said input means to produce an output incrementer digit.

3. A circuit for the addition of two N-digit operands substantially as hereinbefore described with reference to Figs. 3A, 3B and 4 of the accompanying drawings.

3. A circuit for priority encoding an N-digit operand comprising a plurality of cells each coupled to one digit of said operand, said cells comprising: input means for accepting one digit of said N-digit operand; enable-in means for accepting an intermediate enable-in signal from a prior cell; enable-out means for combining the intermediate enable-in signal from the prior cell with the output of said input means and producing an intermediate enable-out signal for use by the next succeeding cell; and priority encoder means for combining the intermediate enable-in signal and the output of said input means to produce an output priority encoder digit.

4. A circuit according to any one of the preceding claims wherein said plurality of cells are serially coupled.

5. A circuit for incrementing an N-digit operand substantially as hereinbefore described with reference to Figs. 3A-8 of the accompanying drawings.

CLAIMS (11 Nov 1983)

1. A circuit for the addition of two N-digit operands and comprising a plurality of cells each coupled to one pair of digits, one digit of said pair from each of said operands, said cells comprising: input means for accepting one digit of each of said two N-digit operands; first carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; second carry-in means for accepting a carry-in signal for the plurality of cells; and summation output means for combining the carry-in signal, the output of said second carry-in means and the output of said input means to produce an output summation digit.

2. A circuit according to claim 1 wherein the cells of said plurality of cells are serially coupled.