JPH03228121A - Priority encoder - Google Patents

Abstract

PURPOSE: To perform a high-speed operation with a relatively less gate amount by allowing an adder to have the serial connection constitution of cells for generating intermediate carry signals. CONSTITUTION: At a stage where final carry inputs Cout0 (k, i) and Cout1 (k, i) to respective bits are generated, a conditional carry adder selects the correct carry input to the respective bits for the carry input Cin to the adder. The selected carry input is exclusively ORed with appropriate P bits PR(0)-P(7) and final sums D(0)-D(7) are generated. Then, this priority encoder is constituted based on the conditional carry adder by the method of redundant gate elimination in addition to the addition of the appropriate number of tristage buffers to the respective bits. Thus, the high-speed operation is performed with the relatively less gate amount.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to carry in digital adders and the like, and particularly to a high-speed carry method that greatly reduces carry propagation delay with a relatively small amount of gate usage.

Adding two N-bit operands to obtain an N-bit result (often referred to as carry propagation addition) is a fundamental operation in digital processors. Various carry schemes have been used in the past to perform this operation.

To easily perform carry propagation addition, use the so-called rip/
A ripple adder may be used. Ripple adders require relatively few transistors per bit, but are relatively slow - for boat fishing. The ripple adder is thus a basic, yet slow, adder that is often used as a basis for measuring the performance of other adders.

FIG. 1 is a diagram showing a typical ripple adder cell. In FIG. 1, A(i) and B(are the bits of each of the two operands being added, and C1n(
i) is the carry input from the previous ripple adder cell, and Cout (i) is this ripple adder cell.
This is the carry output from the adder cell, and D(1) is the sum of this ripple adder cell.

The carry output of one ripple adder cell becomes the carry input of the next stage ripple adder cell. Table IK
A program written in a PASCAL-like language illustrates the logical operation of an N-bit ripple adder. In the program shown in Table 1, "+" indicates a logical sum, "." indicates a logical product, and "XOR" indicates an exclusive logical sum.

or Table 1 i=o to N-I DOBCGINK(i)
= Ali ) + B(i)G(i) = A(i
)・B(1) P(i) = A(i) XORB(i) Cout(i)
= G(i) + (K(i) −C1n(i−1)
=Cin (i + 1) D(t)=P(i) XORC1n(i)nd The ripple adder can be made faster by adding a carry look ahead circuit. To implement a carry look-ahead adder, the ripple adder [11] is composed of a block of, for example, four ripple adder cells. Each block of the four high-speed adders has an additional gate, as shown in FIG.
When '', the carry output from the previous block passes through this block and is propagated to the next block.

The carry look-ahead adder is relatively fast and can be constructed inexpensively with MO3 circuits.

As another method, 1. R, E, ) Transactions 1
On Electronic Computers (I,
R,E,Transactions on Elec
tronic Computers) i19606
Monthly issue, page 226, 5klansk
There is a conditional phase adder announced by Mr.

Although conditional sum addition is very fast, it requires significantly more logic than the relatively slow addition described above. As a result, conditional sum addition results in a very high price per bit. In fact, this method is not widely used.

As mentioned above, various carry schemes have been used in the past to perform carry propagation addition.

However, these known approaches were often too slow for new generations of computers, or were much more complex and expensive than expected.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the drawbacks of the above-mentioned conventional methods and to provide a high-speed carry method for conditional carry addition that is fast and easy to implement.

The adder to which the present invention is applied has a structure in which cells that generate intermediate carry signals are connected in series. Therefore, the intermediate carry signal of each of these bit pairs can be propagated independently and successively through successive stages. Therefore, according to the present invention, the delay time of the full adder can be reduced compared to the known example, and the complexity of the circuit can be kept relatively low.

The invention can also be applied to incrementors and priority encoders. Examples of these applications are also discussed below.

Since the fast carry scheme of the present invention requires relatively few types of cells, they can be easily combined in a regular manner as shown below when constructing an adder, incrementer, or priority encoder of arbitrary length. be able to. Therefore, according to the present invention, it is possible to realize a circuit with a high absolute speed, and even if the LSI is manufactured using either bipolar or MO8 technology, it can be constructed at a low cost without complicating the design.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

In the following, two adders A, B are disclosed that use the fast carry scheme of the present invention to perform carry propagation addition, referred to as conditional carry addition. It will be understood from the following explanation that the configurations of these two adders A and B can be applied not only to adders but also to incrementers and priority encoders. Table 2 shows a comparison between a known scheme and a conditional carry adder using the present invention. In Table 2, the speed of the adder is indicated by the number of gate delay stages required to perform the full addition. The data shown in Table 2 is for a 32-bit adder.

3A and 3B are diagrams showing a conditional carry adder A according to a first embodiment of the present invention, and Table 3 shows logical expressions related to the conditional carry adder A. Figure 3A shows 3
Cells of different species are shown. They are a start cell, an arbitrary number (may be O) of continuation cells, and an end cell.
It is a cell.

FIG. 3B is a diagram showing an example of a cell configuration in the case of a 9-bit adder. In this embodiment, each block includes 2 to 4 1-bit cells. In other words, floc O has 2
1 cell, block 1K 3 cells, and block 2
Four cells are currently being constructed. For example, the second block (j
=1) has three cells, bit number 2
is the start cell Bit number 3 is the continuation (can t
1nue) cell, and the hit number 4 is the end cell, fil.

Table 2 Ripple adder carry look-ahead adder conditional phase adder conditional carry add good person conditional carry adder B For table full adder: For Cin block (01 = C group adder each block) Cin 0 (0) = 0 Cin 1 (01 = 1 Cout bu (77ri (j) = Cout □ (ima
x) + (Cout 1 (i max) - Cin block ())] = C1n block (j + 1) For each bit 1 of block: K (11: A (i) + B (i) G (i) =A
(il・B(1) P(it = A(i)
1nO(i+1) G(i)+(K(il ・Cin 1(i))=Ci
n l (i+I) C1n(i) = Cin 0(i)+ (Cin 1
(i) ・C]) (i) = P(i) XORC1n
(i) n block (J)] Basically, in each block (for example, in "20~2") two ripple carry outputs Cout Q(i) and C
out 1(il is generated. Note that in the start cell of each block, carry inputs C1nQ and C1n1 are defined as 0°° and "l", respectively. These two carry outputs Cout is the carry output Cout of the current block by combining with the carry input Cin block ('') input to the current block.
Generates a block (''). In every block of J=O~2, those two carry chains (CoutO−C
in Q and Coutl −Cin 1 ) are simultaneously propagated one after another. Block 0 first generates its carry output and propagates to block I. Thereafter, only one gate delay is required for the carry to "jump over" each block. Therefore, in the conditional carry adder A, when the carry propagation delay time is minimized, the block size, that is, the bit length, increases in an arithmetic progression as the block number j increases (i.e., 23.4... etc.), the total delay time increases approximately in proportion to the square root of the bit length of the operand.

Therefore, the conditional carry adder A has 17% more elements per bit than the carry lookahead adder, as seen from Table 2.
A 25% performance improvement can be obtained by simply increasing the number of pixels. Similarly, conditional carry adder A is constructed from 1-bit cells and does not use cells spanning multiple bits as in other high-speed techniques. Because of this K, it is possible to create an integrated circuit with a regular layout that is easy to implement and has good chip area usage efficiency.

A second embodiment using the high-speed carry method of the present invention,
Conditional carry adder B is shown in FIG. 4, and a program written in a PASCAL-like language illustrating its operation is shown in Table 4. The program in Table 4 shows the case where the operand length is N bits, and here "2 * *
j'' represents 2j.

The configuration of this embodiment is similar to conditional carry adder A (Figures 3A and 3B), and similarly the inputs are considered as C1n021 and C1n1 = 1, and the carry output is Calculated according to

Table 4 For i-Oto (N-1) Do BEG
INoout O(0,i)-Afil ・Bfil
−GtilOul 1 (0,i)=Afil
+ Bfil -K11lPfi+
-Alil XORB+i)nd FOR j-1to LOG2N W-2 books.

O EGIN For K-Oto (N/W-1) LO-K"W Ll - (K”W-4-W/2) L2- (K”W+W) D.

EOIN For Ko - (LO) ro(Ll-1)D.

EOIN CoutO(j, self)-Cout0(j-1,1
)Coull(j, 1)-Oou口(j-1,i)n
d For -(L-1)Io (L2-1)Do BEGINC
ou+0 (i.

0ou + l (j.

i) -0ou+0(j-1,i)+(Coull (
j-1・Cout 0(j-L Lt-1) )i)
−Cout O(i −1,i )+(Cout I
(i-1゜-Coutl (j '2. Lt -1
)) I) ) nd C1n (01-Cin adder K -LOG2υ For i -OIo (N-1) DOBEGI
ND(breath 1-PfilXORO group(i+C7n(i+1)-CoutO(K,I)+C0our
l(K.

nd)・CIn adder Cout adder-Cin(N) In FIG. 4, each stage has a carry output Cout O(J T ') and Coutl generated from each bit.
(j, i) is generated assuming that the carry inputs to that bit are “0” and 1, respectively. However,
'' is the stage number and l' is the bit number. The purpose of this is to generate a carry input for each bit assuming that the carry inputs applied from the lower order to the entire block of bits are ``0'° and ``1'' respectively. In addition to executing this function, the carry output Co for this block is
Generate ut 1 and Cout O.

K, the final carry input for each bit (Cout □ (k, i) in Table 4, as shown in stage 4 of Figure 4)
and Coutl (k, i)), the carry input Cin to the adder is the correct carry input for each bit (Cin (i+1) in Table 4).
Choose. This selected carry input is then exclusive-OR'ed with the appropriate P pitle(o)-P(7) to generate the final sum D(0)-D(7). .

As can be understood from Fig. 4, conditional carry adder B
The main differences between the conditional carry adder A and the conditional carry adder A are as follows. In conditional carry adder B, the block size increases by a power of 2, that is, in a geometric progression, but the block size of conditional carry adder A is As mentioned above, it increases in an arithmetic progression. Therefore, the total delay time of conditional carry adder B is proportional to the base 2 logarithm of the number of bits to be added.

The carry of the conditional carry adders A and B can be applied to either an incrementer or a priority encoder. An incrementer is a circuit that adds 1 to a number represented by N bits, and a priority encoder generates an output that encodes the highest priority (most significant) bit in an N-bit input (for example, an 8-bit to 3-bit encoder). or a 10-bit to 4-bit encoder).

Figure 5 shows an incrementer using a carry in the conditional carry adder BE.In the incrementer, the second inputs B(0) to B(7) in the adder are not used, so they are set to zero. can be set to . At this time, K, G, and P generated at stage O in FIG. 4 are as follows.

K=A B=OG G=A+B=A P =A In this way, the incrementer shown in FIG. 5 can be constructed by removing all logically redundant gates as an incrementer from the conditional carry adder B shown in FIG. . Using a similar redundant gate removal method, the third
The incrementer shown in FIG. 6 is constructed based on the conditional carry adder A shown in FIG. Similar to the adders shown in FIGS. 3A and 3B, the continuation cells of FIG. 6 can be used as many times as necessary in each block.

FIG. 7 is a diagram showing an 8-bit to 3-bit priority encoder using the high-speed carry method of conditional carry adder B. Similar to the incrementer described above, B(0) ~
The B(7) input is set to 0'' and the carry signal is set to 1°'.

In this embodiment, the carry input is shown as "enabled" and is inverted to keep the priority encoder enabled. (In other words, the enable terminal is actually grounded and given "O"). Each output cell includes a three-state buffer 30 and is enabled by a corresponding gate 40. The first four rows of logic elements allow the 8-bit input A (
7) It is guaranteed that only the buffer 30 corresponding to the most significant bit of "1" of ~AOω is enabled. Each 3-state buffer 30 of each output cell
The inputs to are wired with appropriately binary weighted signals corresponding to the bit numbers of each operator input. Like this,
Each three-state buffer 30 is composed of three buffers connected in parallel, forming three encode output lines with 3-bit output. The output settings when each three-state buffer 30 is enabled are as follows: A(0) digit is set to 0, 0.0, A(
1) The digits are set to 0°, 0.1, and so on, all the way to A (power digit 1.1.1) and correspond to the lowest of the 3-bit inputs to each 3-state buffer. The outputs of the eight buffers (one from each digit) are connected together to form the encoded (0) output, and the eight buffers (one from each digit) corresponding to the intermediate weighted (i.e. weight 2) inputs are connected together to form the encoded (0) output.
) are connected in common to form the encode(1) output, and the eight buffers (one from each digit) corresponding to the most significant inputs are connected in common to form the encode(2) output. These three encode lines then provide appropriately weighted outputs to perform the 8-bit to 3-pinto encoder function, and provide appropriately enabled priority numbers. In addition to adding the appropriate number of three-state buffers for each bit in a manner similar to the incrementer described above, redundant gate elimination techniques can be used to construct the conditional carry adder shown in Figure 3A. The priority encoder shown in FIG. 8 can be constructed based on A. In this case as well, the continuation cells shown in FIG. 8 can be used as many times as necessary in each block.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one pin point of a riffle adder according to the prior art, FIG. 2 is a circuit diagram showing a carry look-ahead adder according to the prior art, and FIG. 3A is a circuit diagram showing a high-speed carry method of the present invention. FIG. 3B is a block diagram illustrating the configuration of the adder shown in FIG. 3A when the bit length is expanded. FIG. 4 is a circuit diagram showing the adder used in this invention. A circuit diagram showing an adder, FIGS. 5 and 6 are circuit diagrams showing an incrementer using the high-speed carry method of the present invention, and FIGS. 7 and 8 are circuit diagrams showing an incrementer using the high-speed carry method of the present invention. This is a circuit diagram showing a priority encoder. A, B: Operand, D: Sum, Cin: Carry input, Cout: Carry output IGB Procedural amendment December 28, 1990■. Indication of the case 2, 3 (1// and the patent application filed on November 30, 1990 (5) 2゜Name of the invention Priority encoder 3゜Relationship with the case Patent applicant address 3000 Hanover Street, Palo Alto, California, U.S.A. Name: Hewlett-Paracard Company Representative
Steven Pea Fox Nationality United States 4°

Claims (1)

[Claims] In a priority encoder that includes a plurality of blocks and targets N-digit operands, each block has the following (A) and (B); (A) a plurality of blocks that start/continue the block; Start/continuation cell means: Each of the start/continuation cell means includes the following (A-1) to (A-1).
-4); (A-1) first input means for accepting a first digit from said operand and providing a first logic output signal; (A-2) a first input means from said first input means; a first carry means that combines the logic output signal and the first carry input signal to provide a first carry output signal; (A-3) a first block enable signal to the start/continue cell means; (A-4) a logic output signal from said first input means, said first block enable signal, said first carry input signal; 1 binary weighted signal to provide a first plurality of coded output signals.
Encoder output means; (B) End cell means for terminating each of the blocks; The end cell means includes the following (B-1) or (
B-4); (B-1) second input means for accepting a second digit from said operand and providing a second logic output signal; (B-2) a second digit from said second input means; (B-3) a second carry means for combining the logic output signal of No. 2 and a second carry input signal from the preceding cell means to provide a second carry output signal; (B-3) said second carry; a second block enable means for combining the output signal with a second block enable signal to provide a final block enable signal; (B-4) a logic output signal from the second input means and a second block enable signal; A second block enable signal, said second carry input signal, and a second binary weighting signal are combined to provide a second plurality of coded output signals.
encoder output means; wherein the plurality of blocks are connected in series only by the final block enable signal and the plurality of encoded output signals, and each of the blocks has a variable number of serially connected start/continue signals. cell means, the variable number of serially connected start/continue cell means receiving the first carry output signal and the first block/continue cell means;
an enable signal and said plurality of encoded output signals connected in series with each other, said start/continue cell means at the end of each of said blocks receiving said first carry output signal and said plurality of coded output signals; serially coupled to said end cell means by a block enable signal and said plurality of coded output signals, said variable number of start/continue cell means in said plurality of serially connected blocks; is a priority encoder characterized by increasing in an arithmetic progression.