JP3199196B2 - 5-input adder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a five-input adder for use in a Wallace tree multiplier or a multi-operand adder, which adds five bits to generate a one-bit sum and a two-bit carry. Things.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a full adder (FA) 1 of a first conventional example. FIG. 5B shows the internal structure of the full adder (FA) 1 shown in FIG. 5A in detail. 3 bits (X0, X1,
X2) and outputs a 1-bit sum (S0) and a 1-bit carry (C0). FIG. 6 shows a truth table. In addition. In the following description, S indicates sum, C indicates carry,
It is shown with suffix numbers as appropriate.

The exclusive OR gate 2 generates A0 from inputs X0 and X1. As shown in FIG. 6, two types of combinations of X0 and X1 (X0 = 0, X1 = 0 or X0 =
1, X1 = 1), A0 = 0. At this time, the exclusive OR gate 3 passes the input X2 through to generate the sum S0. Note that when X0 = X1 = 0, C0 = 0 and X
When 0 = X1 = 1, C0 = 1. In addition, two types of combinations (X0 = 1, X1 = 0 or X0 = 0, X1 =
In 1), A0 = 1. At this time, the exclusive OR gate 3 inverts the input X2 to generate the sum S0. Note that X
When 2 = 0, C0 = 0, and when X2 = 1, C0 = 1.
It is. That is, as shown in FIG. 5, the selector 4 selects X1 (or X0) when A0 = 0, and
By selecting X2 when 0 = 1, carry C0 is selected.
Can be generated. Note that 0 and 1 written in the selector 4 are:
When the selection signal A0 = 0, the side written with 0 means that the side written with 1 when A0 = 1 means to be selected. 0 and 1 on the selector 18 described later have the same meaning as those written on the selector 4. The critical path for determining the worst delay time is evaluated by the number of exclusive OR gates 2 and 3 and the number of selectors 4 necessary to generate a carry or a sum from an input signal. According to this evaluation criterion, the critical path of FA1 in FIG. 5 has two stages because there are two exclusive OR gates 2 and 3.

FIG. 7 shows a configuration of an (4 + 1) input adder 5 in which two FAs 1 are connected in series, and FIG. 8 shows a truth table thereof. The (4 + 1) input adder 5 outputs a 1-bit sum (S1) and a 2-bit carry (C0, C1). (4+
1) By arranging m input adders 5 and connecting C0 to D0 on the left (one bit higher), four m-bit data are added, and a 4-input carry save addition that generates a carry and a sum The unit (hereinafter referred to as 4CSA) 6 can be configured as shown in FIG. The critical path of 4CSA6 is 4
It is a step. When 4CSA6 is used, four 4-bit data a0 to d0, a1 to d1, a2 to d2, and a3 to d3 can be added to generate a 4-bit sum and carry.

[Conventional Example 2] FIG. 10 shows a configuration of an (8 + 2) input adder 9 of Conventional Example 2 in which the 4CSAs 6 shown in FIG. 9 are connected by a Wallace tree method. In FIG. 10, FIG.
3 shows the inside of the CSA 6 in detail. C0 * and D
0 *, C1 * and D1 *, C4 * and D4 * are connected inside 4CSA6. An (8 + 2) input adder 9 adds eight m-bit data to generate a carry and a sum.
An input carry save adder can be configured. This 8
The input carry save adder has eight critical paths. Regarding this adder, for example, MARK R. SA
NTRO, MARK A. HORDWITZ, "SP
IM: A Pipelined 64 × 64-bit
Iterative Multiplier ", IEEE
EJ. Solid-State Circuits,
vol. SC-24, no. 2, pp. 487-49
3, Apr. 1989.

[0006] In addition, (4+
1) A 2-bit carry (C0, C0)
1) is output. Since the weights of C0 and C1 are equal, when one is 0 and the other is 1, the function as a (4 + 1) input adder is equivalent regardless of which one is 1. FIG. 11 shows a truth table of the (4 + 1) input adder 10 focusing on this point. FIG. 12 shows the configuration of the (4 + 1) input adder 10 derived from FIG. Even if the (4 + 1) input adder 10 is used as a component, a 4-input carry save adder (hereinafter referred to as 4CSAA) can be configured.
While the sum of 4CSAs 6 shown in FIG. 9 is generated through four exclusive OR gates, the sum of 4CSAA is generated through three exclusive OR gates. This circuit is described in, for example, Mori, M .; Nagamats
u, M. Hirano, S.M. Tanaka, M .; No
da, Y. Toyoshima, K .; Hashimot
o, H .; Hayashida, K .; Maeguch
i, "A 10-ns 54 × 54-bit Para
llell Structured Full Arra
y Multiplier with 0.5-μm
CMOS Technology "IEEE J. So
lid-State Circuits, vol. SC
-26, no. 4, pp. 600-606, Apr. 1
991.

[0007]

However, in the conventional example 1, the critical path of 4CSA has four stages,
There is a problem that the delay time is large.

In the second conventional example, the use of the 4CSA 6 as a component of the Wallace tree has a more regular configuration than the Wallace tree using the full adder, but the wiring between the 4CSAs becomes complicated. There is. In addition, the 4CSAA can generate the sum with three stages of exclusive OR gates, and has a shorter physical path than the 4CSA6. However, there is a problem that the path for generating the carry becomes critical.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the 4CSA critical path to three exclusive OR gates without increasing the amount of hardware. Is to provide a possible technology.

[0010]

In order to solve the above problems, the present invention provides a 5-input adder that receives 5 bits and outputs a 2-bit carry and a 1-bit sum.
First, an exclusive OR of the first and second input bits is taken, and when the result is 0, one of the first and second input bits is selected, and when the result is 1, the third input bit is selected. Means for generating a first carry by selecting a bit, an exclusive OR of a third input bit and a fourth input bit, a result thereof, and a signal used for selecting the first carry. , And when the result is 0, the fourth input bit is selected.
By selecting the fifth input bit when
Means for generating an exclusive OR of a fifth input bit and a signal used for selecting the second carry, and generating a sum.

[0011]

The Walla using the 5-input adder according to the present invention.
When the ce tree is configured, the number of critical paths per stage of the 5-addition adder can be reduced to three stages of exclusive OR gates.

[0012]

1 is a block diagram showing the configuration of an (4 + 1) input adder 16 according to an embodiment of the present invention. The same reference numerals as in FIG. 5 denote the same parts, 17 is an exclusive OR gate, 18 is a selector. Is shown. FIG. 2 shows two circuits 19 and 20 for generating A1 from inputs A0, X2 and X3, and FIGS. 3 and 4 show truth tables of the circuits 19 and 20, respectively. As can be seen from FIGS. 3 and 4, the exclusive OR of A0 + X2 and X3
Is equivalent to the exclusive OR of X2 and X3 and the exclusive OR of A0, and the circuits 19 and 20 are equivalent. Further, it is not necessary to output the intermediate sum S0 in configuring the (4 + 1) input adder. Therefore, the (4 + 1) input adder 16 of FIG. 1 in which the circuit 19 of FIG. 7 is replaced by the circuit 20 is equivalent to the (4 + 1) input adder 5 of FIG. However, while the critical path of the 4CSA 6 configured using the (4 + 1) input adder 5 of FIG.
Using a 4-input array type carry save adder (hereinafter 4CS
AB), there are three critical paths.

[0013]

As described above, when the Wallace tree is constructed, the use of the five-input adder according to the present invention has the effect of suppressing an increase in wiring complexity and reducing the critical path.

Further, when configuring a carry save adder with a very large number of bits, the wiring complexity is increased by combining the plurality of array-type carry save adders according to the present invention to form an adder tree. This has the effect of suppressing the increase in the number of critical paths and reducing the critical path.

[Brief description of the drawings]

FIG. 1 is a logic diagram showing a configuration of a (4 + 1) input adder according to an embodiment of the present invention.

FIG. 2 is a logic diagram for explaining the principle of the present invention.

FIG. 3 is a diagram showing a truth table of FIG. 2 (a).

FIG. 4 is a diagram showing a truth table of FIG. 2 (b).

FIG. 5 is a logic diagram showing a configuration of a full adder.

FIG. 6 is a diagram showing a truth table of FIG. 5;

FIG. 7 is a logic diagram showing a configuration of a (4 + 1) input adder according to a conventional example.

FIG. 8 is a diagram showing a truth table of FIG. 7;

FIG. 9 is a logic diagram showing a configuration of a four-input adder according to a conventional example.

FIG. 10 shows a 4-input carry save adder of the prior art example as W
FIG. 4 is a logic diagram showing a configuration of an (8 + 2) input adder connected by an alley tree method.

FIG. 11 is a diagram illustrating a truth table of a (4 + 1) input adder;

FIG. 12 is a logic diagram showing a configuration of a (4 + 1) input adder that generates a sum with three stages of an exclusive OR gate according to a conventional example.

[Explanation of symbols]

Reference Signs List 1 full adder (FA) 2 exclusive OR gate 3 exclusive OR gate 4 selector 5 (4 + 1) input adder 6 4-input carry save adder 9 4-input carry save adder connected by Wallace tree method (8 + 2) input adder 10 A sum is generated by three stages of exclusive OR gates (4+
1) Input adder 11 Exclusive OR gate 12 AND gate 13 OR gate 14 NOR gate 16 (4 + 1) input adder with three stages of critical path 17 Exclusive OR gate 18 Selector 19 Two stages of exclusive OR gate Circuits connected in series 20 Circuits in which exclusive OR gates are connected in two stages in series

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-166424 (JP, A) JP-A-53-31927 (JP, A) JP-A-62-140138 (JP, A) JP-A-4- 289917 (JP, A) JP-A-4-92920 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F ^7/ 38-7/54

Claims (1)

(57) [Claims] 1. A five-input adder that receives five bits and outputs a two-bit carry and a one-bit sum, first takes an exclusive OR of the first and second input bits, and the result is Means for generating a first carry by selecting one of the first and second input bits when it is 0, and selecting a third input bit when the result is 1; And the exclusive OR of the fourth input bit and the exclusive OR of the result and the signal used for selecting the first carry, and when the result is 0, the fourth input bit And select
Means for generating a second carry by selecting the fifth input bit when it is 1, and exclusive-ORing the fifth input bit with the signal used for selecting the second carry, Means for generating a sum.