GB2130771A - Incrementer for operating on N- digit operands - Google Patents

Incrementer for operating on N- digit operands Download PDF

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Publication number
GB2130771A
GB2130771A GB08330888A GB8330888A GB2130771A GB 2130771 A GB2130771 A GB 2130771A GB 08330888 A GB08330888 A GB 08330888A GB 8330888 A GB8330888 A GB 8330888A GB 2130771 A GB2130771 A GB 2130771A
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United Kingdom
Prior art keywords
carry
digit
adder
cells
signal
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Granted
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GB08330888A
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GB2130771B (en
GB8330888D0 (en
Inventor
Frederick A Ware
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HP Inc
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Hewlett Packard Co
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Abstract

An incrementer for an N-digit operand A(0) to A(7). <IMAGE>

Description

1
SPECIFICATION Circuits for operating on N-digit operands
GB 2 130 771 A 1 This invention is concerned with circuits for operating on N-digit operands, and especially with circuits for incrementing an N-digit operand. The invention is related to that disclosed in our co5 pending UK patent application no. 8306208.
The addition of two N-bit operands to form an N-bit result, often called "carry propagate addition", is a fundamental operation in digital processors. A variety of techniques have been developed to perform this operation.
A simple method for performing carry propagate addition is the ripple adder. The ripple adder requires relatively few transistors per bit, but it is usually a relatively slow technique. The ripple adder is 10 thus the technique against which other methods are often measured.
Figure 1 of the accompanying drawings shows a typical ripple adder cell. A(i) and B(i) are individual bits of the two operands to be added, Cin(i) is the carry-in signal from a previous adder cell, Cout(i) is the carryout signal from the illustrated cell, and Sum(i) is the sum signal of the illustrated cell. The carry-out signal of one cell is the carry-in signal to the next cell, Table 1, shown as a PASCALlike language program, summarizes the Boolean equations for the ripple adder method, where -+" is the Boolean "OR", "" is the Boolean "AND", and "XOR" is the Boolean "Exclusive-OR".
End For i=0 to N-1 (N bit adder) DO BEGIN KM=AM+BO) G(i)=A(I)13(i) P(i)=A(i)XOR B(i) Cout(i)=:PG(i)+[K(i)Cin(i)I=Cin(i+ 1) Sum(i)=P(i)XOR Cin(i) Table 1
25- The ripple adder may be sped up with the addition of "carry look ahead- circuitry. To implement a carry look ahead adder, the ripple adder cells are organized into blocks of, for example, four ripple adder cells. Each block of four ripple adder cells, as shown in Figure 2 of the accompanying drawings, is provided with additional gates which allow carry propagation across the entire block if the 'W' bits are all 1 (i.e., the outputs of the OR gates K(i)). The carry look ahead adder is moderately fast and is 30 economical to implement in MOS circuitry.
Another scheme is the "conditional sum- adder reported by Sklansky, "Conditional-Sum Addition Logic-, I.R.E. Transactions on Electronic Computers, page 226, June 1960. Although very fast in operation, conditional sum addition takes far more logic to implement than the other, slower techniques discussed above. The result is that conditional sum addition has a very high cost per bit. In 35 practice, this technique has not enjoyed widespread usage.
Thus, several methods for performing N-bit addition have been used in the prior art. However, these known methods are often either too slow for the new generations of computers or they are substantially more complex and costly than is desirable.
In our copending UK application no. 8306208, there is disclosed a circuit for the addition of two 40 N-digit operands and comprising a plurality of cells each coupled to one pair of digits, one digit of said pair from each of said operands, said cells comprising input means for accepting one digit of each of said two N-digit operands; first carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; second carry-in means for accepting a carry in signal for the plurality of cells; and summation output means for combining the carry-in signal, the output of said second carry-in means and the output of said input means to produce an output summation digit.
The present invention provides a circuit for incrementing an N-digit operand comprising a plurality of cells each coupled to one digit of said operand, said cells comprising input means for accepting one digit of said N-digit operand; carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; and incrementer output means for combining the intermediate carry-in signal and the output of said input means to produce an output incrementer digit.
The cells of the plurality of cells are preferably serially coupled.
There now follows a detailed description which is to be read with reference to Figures 5 and 6 of the accompanying drawings of an incrementer circuit according to the invention. Figures 3A, 313 and 4 correspond to Figures 3A, 3B and 4 of the drawings of our co-pending UK patent application no.
8306208 and are included together with the description thereof for the purpose of facilitating 60 understanding of the present invention. The circuit illustrated in Figures 5 and 6 has been selected for description to illustrate the invention by way of example and not by way of limitation.
2 GB 2 130 771 A 2 In Figures 3A to 6 of the accompanying drawings:Figures 3A and 3B show a conditional carry adder "A"; Figure 4 shows the organization of a complete 8-bit conditional carry adder "B".
Figure 5 shows an 8-bit incrementer according to the present invention, using the conditional 5 carry adder "B" technique; and Figure 6 shows the cells used for producing an incrementer according to the present invention using the conditional carry 6dder "A" technique.
In Figures 3A, 3B and 4 there are disclosed two embodiments of a technique for performing N-bit addition, both of which are called the "conditional carry" adder. Both of these techniques, "A" and "B", can also be applied to incrementers according to the present invention, as well as adders. As can be 10 seen in Table 2, the conditional carry adder compares favorably to the previously known techniques. In Table 2 adder speed is stated in terms of the number of gate delays required for the total addition. The data shown is for a 32-bit adder.
Figures 3A and 3B show the first adder, namely, the conditional carry adder "A", and Table 3 presents the related Boolean equations. The three different cell types are shown in Figure 3A, a "start" cell, zero to any number of "continue" cells, and an "end" cell. Figure 3B shows how these cells are arranged to form, for example, a 9-bit adder. In this example each block contains between two and four one-bit cells, with two cells in block 0, three cells in block 1, and four cells in block 2. Thus, for example, in the second block (j=l), where there are three cells, bit number 2 is a start cell, bit number 3 is a continue cell, and bit number 4 is an end cell.
Table 2
Number of devices per bit Method for performing Total number Static Static addition of delays NMOS CMOs 25 Ripple adder 33 20 26 Carry Look Ahead Adder 16 24 32 Conditional Sum Adder 14 72 104 Conditional Carry Adder-A 12 28 38 Conditional Carry Adder-B 8 36 52 30 For the whole adder:
Cinblock (0)=Cinadder For each block j:
CinO (0)=0 Cinl 0=1 Coutblock (j)=CoutO (imax)+[Coutl (imax)Cinblock(j)l =Cinblock(j+l) Table 3
For each bit i of block j: It KM=AM+130) 40 G(i)=Affi13(i) P(i)=A(i) XOR B(i) CoutO (i)=G(i)+[K(i)CinO (01=CinO (i+l) Coutl (i)=G(i)+[K(i)Cinl (i)]=Cinl (i+l) Cinffi=CinO (i)+[Cinl (i)Cinblock (j)l Sum W=PM XOR Cin(i) Fundamentally, each block, j=0-2 in the example, generates two ripple carry output signals CoutO(i) and Coutl (i). Note that the CinO and Cinl for the start cell of each block is defined as 0 and 1 respectively. The Cout signals are combined with the carry-in signal to the current block Cinblock(j) to produce the carry-out signal of the current block Coutblock(j). All of the blocks j=0-2 begin rippling 50 their two carry chains at the same time. Block 0 produces its carry-out signal first and passes it on to block 1. Thereafter, only one gate delay is required for the carry to "jump" across each block. Since the block size increases as an arithmetic progression (i.e., 2, 3, 4 and so forth) the total delay is approximately proportional to the square root of the number of bits to be added. Thus, the conditional carry adder -A- gives 25% better performance than the carry look adder with only a 17% increase in 55 the number of devices per bit. Also, the conditional carry adder -A- can be implemented with one-bit 3 GB 2 130 771 A 3 cells, rather than cells which stretch across multiple bits as in other high speed techniques. This permits an ordered integrated circuit layout which is easy and space-efficient to implement.
The second adder, the conditional carry adder "B", is shown in Figure 4 and the related Boolean equations are shown in Table 4. Note that Table 4 is shown as a PASCAL-like language program for any length adder and "2j" is equivalent to 2 raised to the jth power. The design is similar to the conditional carry adder "A" (Figures 3A and 3B) and in similar fashion the inputs are assumed to be Cin0=1 and Cin1=1 and the carry-out signals are computed accordingly.
N=Bits in Adder For i=0 to (N-1) DO BEGIN CoutO(O, i)=A(i)B(i)=G(i) Coutl (0,i)=A(i)+B(i)=K(i) PM=Affl XOR B0) End Forj=1 to LOG2(N) DO BEGIN W=2j For K=0 to NW-1) DO BEGIN LO=KW+W/2 L1 =KW+W/2) L2=(KW+W) For!=(L0) to (L1 -1) DO BEGIN couto(i,i)=couto(j-l,i) Coutl (j,1)=Coutl (j-1J) End For i=(L1) to (L2-1) DO BEGIN couto(i,i)=couto(j-l,i) Table 4 +[Coutl (j-l,i)CoutO(j-1), L1 -l)] Coutl (j,i)=couto(j-l',i) End End +[Coutl (j-1,1)Coutl (j-2), Ll-1)1- Cin(O)=CinAdder K=LOG2N For 1=0 to (N-1) DO BEGIN D(i)=P(i) XOR Cin(i) Cin(41)=CoutO(I(J)+[Coutl (I(J)CinADDER1 End CoutADDER=Cin(N) In Figure 4 each stage generates the carry-out signals for each bit Cout0(jj) and Cout(jJ) assuming that the carry-in signals to that bit are zero and one respectively, where "j" is the stage 40 number and 'T' is the bit number.
The object is to generate the carry-in signals for each bit as if the carry-in signals to the entire block of bits are a one and a zero respectively. The successive stages perform this function, as well as generating the carry-out signals for the block Coutl and CoutO.
Figure 4 shows that when the final carry-in signals for each bit are generated, the carry-in signal 45 for the adder selects the correct carry-In signal for each bit, and Cin is exclusive-ORed with the appropriate P-bit P(O-7) to produce the final sum D(O-7).
As can be seen from Figure 4 the major difference between embodiment "B" and embodiment W' is that in 'W' the block sizes increase as powers of two, which forms a geometric progression whereas the block size of embodiment -A- forms an arithmetic progression as discussed above. The 50 4 GB 2 130 771 A 4 total delay in embodiment -B- is thus proportional to the logarithm to the base two of the number of bits to be added.
The technique of both adders -A- and---Wcan be adapted to produce an incrementer according to the present invention. An incrementer is a device for adding 1 to a prior N-bit number.
Figure 5 shows an incrementer using the condition carry "B" technique. Since none of the 5 B(O-7) inputs are used in an incrementer, they can be set to zero and when B=O:
K=AB=0 G=A+B 0 A P+A XOR B=A In like fashion the Cin signal can be set to 1 for an incrementer if the incrementer is always to be 10 enabled. Thus, all of the logically redundant gates can be removed from the conditional carry adder -Bshown in Figure 4 to form an incrementer -B- as shown in Figure 5. This same technique for removal of redundant gates can be used as shown in Figure 6 to create an incrementer "A" based on the conditional carry adder -A- of Figure 3A. As with the adder of Figure 3A and 313 the Continue cell of Figure 6 can be used as many times as needed in each block.

Claims (3)

  1. Claims 1. A circuit for incrementing an N-digit operand comprising a
    plurality of cells each coupled to one digit of said operand, said cells comprising: input means for accepting one digit of said N-digit operand; 20 carry-in means for accepting an intermediate carry-in signal from a prior cell; carry-out means for combining the intermediate carry-in signal from the prior cell with the output of said input means and producing an intermediate carry-out signal for use by the next succeeding cell; and incrementer output means for combining the intermediate carry-in signal and the output of said input means to produce an output incrementer digit.
  2. 2. A circuit according to claim 1 wherein the cells of said plurality of cells are serially coupled.
  3. 3. A circuit for the addition of two N-digit operands substantially as hereinbefore described with reference to Figures 5 and 6 of the accompanying drawings.
    Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1984. Published by the Patent Office, 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.
    f
GB08330888A 1982-08-23 1983-03-07 Incrementer for operating on n-digit operands Expired GB2130771B (en)

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GB08306208A Expired GB2127187B (en) 1982-08-23 1983-03-07 Circuits for operating on n-digit operands
GB08330889A Expired GB2130774B (en) 1982-08-23 1983-11-18 Circuits for operating on n-digit operands

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GB08330889A Expired GB2130774B (en) 1982-08-23 1983-11-18 Circuits for operating on n-digit operands

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JPS6055438A (en) * 1983-09-05 1985-03-30 Matsushita Electric Ind Co Ltd Two-input adder
JPS6275840A (en) * 1985-09-30 1987-04-07 Toshiba Corp Carry selecting adder
DE58909280D1 (en) * 1988-07-29 1995-07-13 Siemens Ag Carry select adders.
US4956802A (en) * 1988-12-14 1990-09-11 Sun Microsystems, Inc. Method and apparatus for a parallel carry generation adder
US5136539A (en) * 1988-12-16 1992-08-04 Intel Corporation Adder with intermediate carry circuit
JPH0651950A (en) * 1992-07-30 1994-02-25 Mitsubishi Electric Corp Adder circuit
US6527748B1 (en) 1998-08-17 2003-03-04 Yutaka Suzuki Method of gastrostomy, and an infection preventive cover, kit or catheter kit, and a gastrostomy catheter kit

Citations (1)

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GB1103518A (en) * 1964-11-17 1968-02-14 Siemens Ag Improvements in or relating to electric circuit arrangements

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US3078337A (en) * 1958-12-17 1963-02-19 Skiatron Elect & Tele Metering systems
US3138703A (en) * 1959-12-29 1964-06-23 Ibm Full adder
US3316393A (en) * 1965-03-25 1967-04-25 Honeywell Inc Conditional sum and/or carry adder
GB1143886A (en) * 1966-10-13
GB1391175A (en) * 1971-08-04 1975-04-16 Cambridge Consultants Lttd Electrical circuit means for use in acoustic emission detecting and or recording apparatus
GB1479939A (en) * 1973-09-25 1977-07-13 Siemens Ag Programme-controlled data switching systems
JPS537349B2 (en) * 1974-03-27 1978-03-16
JPS5446224U (en) * 1977-09-07 1979-03-30
EP0052157A1 (en) * 1980-11-15 1982-05-26 Deutsche ITT Industries GmbH Binary MOS carry look ahead parallel adder

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GB1103518A (en) * 1964-11-17 1968-02-14 Siemens Ag Improvements in or relating to electric circuit arrangements

Also Published As

Publication number Publication date
DE3326388C2 (en) 1993-04-01
JPH0467212B2 (en) 1992-10-27
JPH03228121A (en) 1991-10-09
JPH0467213B2 (en) 1992-10-27
JPH03228122A (en) 1991-10-09
JPH0450614B2 (en) 1992-08-14
JPH03229320A (en) 1991-10-11
GB2130771B (en) 1986-02-12
JPH0366693B2 (en) 1991-10-18
JPH03229321A (en) 1991-10-11
GB2130774B (en) 1986-02-12
JPS5957343A (en) 1984-04-02
GB2127187B (en) 1986-03-05
GB8330888D0 (en) 1983-12-29
GB8330889D0 (en) 1983-12-29
GB8306208D0 (en) 1983-04-13
JPH0467211B2 (en) 1992-10-27
GB2127187A (en) 1984-04-04
JPH0450615B2 (en) 1992-08-14
JPH03228120A (en) 1991-10-09
GB2130774A (en) 1984-06-06
DE3326388A1 (en) 1984-02-23

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