JPS61289425A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To attain high speed multiplication by forming a canonical recording circuit and a selector circuit and recording the value of a multiplying register simultaneously to plural bits on the basis of canonical decimal numbers. CONSTITUTION:A canonical recoding circuit 5 for converting a multiplied value into a canonical binary number in each prescribed bits and a selector circuit 6 for multiplying a multiplicand by + or -n (n is zero or natural numbers) in accordance with input data from the circuit 5 and outputting the multiplied value are formed. Consequently, the circuit 5 converts a multiplier into a canonical binary number in each prescribed bits and inputs a control signal corresponding to each canonical binary number to an ALU 4 and the selector circuit 6. The selector circuit 6 multiplies the multiplicand by a number corresponding to the control signal and the ALU 4 adds the value of an accumulator 1 to the output value of the selector circuit 6 and shifts the added value by the prescribed number of bits corresponding to the control signal to store the shifted value to the accumulator 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplication circuit, and more particularly, to a multiplication circuit that can speed up multiplication in, for example, an arithmetic unit section of a computer.

[Conventional technology]

FIG. 4 is a diagram showing a multiplication circuit using a conventional 1-bit shift method. In the figure, l is a register (accumulator) that stores calculation results, 2 is a multiplier register that stores a multiplier, 3 is a multiplicand register that stores a multiplicand, and 4 is an arithmetic logic unit (Arithmetic Logic Unit).
T? (hereinafter referred to as ALU).

Next, the operation will be explained.

Accumulator 1 is cleared before calculation. First, the least significant bit of multiplier register 2 is checked, and if it is 1, the value of accumulator 1 and the value of multiplicand register 3 are
The least significant bit of 0 multiplier register 2 is shifted to the right by 1 bit and put into accumulator 1.
In this case, no addition is performed. Next, multiplier register 2 is shifted to the right by 1 bit. Repeat the above operation for the number of bits of the multiplier. The multiplication result is found in accumulator 1.

[Problem that the invention seeks to solve]

Since the conventional multiplication circuit is configured as described above, there is a problem in that addition is complicated by the number of bits of the multiplier in order to obtain a multiplication result.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a high-speed multiplication circuit that can perform multiplication with a small number of additions.

[Means to solve the problem]

The multiplication circuit according to the present invention includes a canonical recoding circuit that converts a multiplier into a canonical binary number by predetermined bits, and a multiplicand multiplied by ±n (where n is O) according to input data from the canonical recoding circuit.
or a natural number) and a selector circuit for outputting the output.

[Effect]

In this invention, the canonical recode circuit converts the multiplier into a canonical binary number by predetermined bits and inputs a control signal corresponding to each canonical binary number to the ALU and the selector circuit, and the selector circuit converts the multiplicand into a control signal. The ALU adds the accumulator value and the output value of the selector circuit, shifts this by a predetermined number of bits according to the control signal, and stores it in the accumulator.In this way, multiple bits of the multiplier are multiplied at once. The multiplication is performed using fewer additions than traditional multiplication algorithms.

〔Example〕

An embodiment of the present invention will be described below using the circuit shown in FIG.

FIG. 1 shows a multiplication circuit according to an embodiment of the present invention, in which the same symbols as in FIG. 4 indicate the same parts.

In the figure, 5 is a canonical recode circuit, 6 is a selector circuit, and 0 multiplier register 2 is composed of a shift register. The canonical recode circuit 5 includes the lower three of the multiplier register 2.
The selector circuit 6 decodes the bit and generates a control signal for the selector circuit 6 and ALU 4. According to the control signal, the selector circuit 6 multiplies the value of the multiplicand register 3 by θ, ±1, and ±2 to obtain A.
Send it to LU4.

FIG. 2 shows the canonical recode circuit 5 in FIG. 1. The canonical recode circuit 5 generates a 2-bit signal 12.13, which is the basis of a control signal, from the lower bits BIIO, BO9 of the multiplier register 2 and the carry in the first latch 11 from the previous process. These 2-bit signals 12 and 13 are stored in the second latch 14, the multiplier register 2 is shifted to the right by 1 bit, and the same processing as now is performed to generate a similar signal. Combining these 4-bit signals, control signals CNTl 15 and CNT216°C
Make NT317 and CNT418. CNTl 15 is a signal that takes complement, CN7418 is a signal that multiplies by 0, CN7
418 is a signal to be multiplied by 1, and CN7418 is a signal to be multiplied by 2. In this way, canonical recoding for 2 bits can be realized with a simple circuit using a recoding circuit for 1 bit and a latch.

FIG. 3 shows the selector circuit 6 in FIG. 1. The selector circuit 6 multiplies the value of the multiplicand register 3 by 0, ±1, or ±2 and outputs the result.

These are realized by left-shifting the value of the multiplicand register 3 and taking the complement. However, when multiplying by -1 or 12, a correction signal is input to the least significant bit and ALU. In addition, in Fig. 3, 15 is CNT1.1
6 is CNT2.17 is CNT3, 1B is CNT4,19
is the nth bit of the multiplicand register, 20 is the ALU fi+
l bit input, 21 is ALU nth bit input, 22
is the 0th bit of the multiplicand register, 23 is the input of the ALU 1st bit, and 24 is ALUi! This is an O-bit input.

Canonical signed binary numbers are represented by three digits (1, 0, 1), and have the characteristic that the subject digits are separated by a zero digit (here, 1 represents -1). . Therefore, the only combination of two consecutive digits in a canonical signed number is (10, 01, 00, 01, 10). This converts the binary number to a canonical signed binary number and processes it in units of 2 digits. If you do, 0 times the multiplicand, ±
Multiplication can be performed by adding 1x and ±2x to the partial product.

ALU4 is 1 in 2 clock cycles (IALU cycle).
Complete one calculation process. On the other hand, the canonical recode circuit 5 generates the signals necessary for the next ALU control in these two clock cycles. First, in the first clock cycle, the canonical recode circuit 5 performs control using the lower two bits of the multiplier register 2 and the carry obtained in the previous process. Create the signal that is the source of the signal. These are the second latches 14
is stored in Also, a carry for processing in the second clock cycle is stored in the first latch 11. Furthermore, multiplier register 2 is shifted to the right by 1 bit. In the second clock cycle, a signal that becomes the basis of the control signal is generated in the same way as in the first clock cycle, and the multiplier register 2 is further shifted by 1 bit.

In the selector circuit 6, the canonical recode circuit 5 generates 0 times, ±1 times, and ±2 times the value of the multiplicand by taking the complement of the value of the multiplicand register 3 and shifting it to the left by 1 bit according to the control signal. Among the outputs, CNT314 and CNT41
5 and 1H' at the same time, and the values of adjacent bits at the entrance of the ALU 4 will not conflict.

, the above operations are performed in the IALU cycle.

While the ALU 4 is adding the output value of the selector circuit 6 and the value of the accumulator 1 obtained here, the next canonical recode can be performed. The addition result is shifted to the right by 2 bits and stored in the accumulator.

The multiplication is completed in 1/2 the number of ALU cycles as the number of multiplier bits, and the multiplication result is stored in the accumulator 1. Note that it is necessary to clear the accumulator 1 and the first latch 11 at the beginning of the calculation.

In the circuit of this embodiment, the canonical recode circuit for 2 bits can be realized with a simple configuration of a canonical recode circuit for 1 bit and a latch, and the selector circuit can be realized by a simple combination circuit with a transmission gate. realizable. By adding this canonical recode circuit and selector circuit to a conventional multiplication circuit, the multiplier is converted into a canonical binary number by the canonical recode circuit, making it possible to examine multiple bits at once, allowing multiplication with fewer additions. can be performed, speeding up multiplication.

In the above embodiment, a circuit was shown in which 2 bits of the multiplier register are recoded in the IALU cycle by providing one latch for the signal after canonical recoding, but by providing n-1 latches, the IALU cycle By recoding the n bits of the multiplier register (m bits), it is possible to expand the circuit to a high-speed multiplication circuit that can perform multiplication with ((m/n)+1) additions. However, m/n) is m
/ In this canonical recode for n bits, which indicates an integer not exceeding n, the ALU performs canonical recode for 1 bit n times while performing one operation, and stores the recode value up to the (n-1)th recode. This provides a canonical binary number for the next ALU operation.

〔Effect of the invention〕

As described above, according to the present invention, the canonical recode circuit and the selector circuit are provided, and the value of the multiplier register is recoded in multiple bits at a time using canonical binary numbers.
The number of additions can be significantly reduced compared to the conventional method, and there is an effect that high-speed multiplication can be performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a multiplication circuit according to an embodiment of the present invention;
FIG. 2 is a diagram showing a canonical recode circuit of the circuit of this embodiment, FIG. 3 is a diagram similarly showing a selector circuit, and FIG. 4 is a diagram showing a conventional multiplication circuit. 1...Accumulator, 2...Multiplier register, 3...
... Multiplicand register, 4... ALU, 5... Canonical recode circuit, 6... Selector circuit, 11... First latch, 14... Second latch. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) An accumulator, a selector circuit that multiplies the multiplicand by a number according to the control signal, adds the value of the accumulator and the output value of the selector circuit, and shifts the addition result by a predetermined number of bits according to the control signal. an arithmetic and logic operation unit that stores the multiplier in the accumulator; and a canonical recode circuit that converts the multiplier into a canonical binary number in units of predetermined bits and provides a control signal corresponding to each canonical binary number to the selector circuit and the calculation logic unit. A multiplication circuit characterized by comprising: (2) The multiplication circuit according to claim 1, wherein the canonical recode circuit comprises a latch that stores a carry generated during recoding and a latch that stores the recode result.