JPH08314697A - Multiplier used for both number with sign and number withoutsign - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplier with which multiplication is performed selectively between signed/unsigned numbers by applying a corrected booth algorithm. SOLUTION: A multiplier is composed of an encoder 22 which generates a recod digit from a multiplier B, a shifting/inverting unit 24 which generates a partial product by shifting/inverting a multiplicand A in accordance with the recod digit, a first partial product generator 25 which performs arithmetic operation in accordance with the recod digit and adds the results of the arithmetic operation to the partial product outputted front the unit 24, second to fourth partial product generators 26-28 which are successively connected to the output of the generator 25 and generate partial products by adding the output data of the preceding stage to the result of arithmetic operation performed on the multiplicand following the recode digit, a sign transmitting unit 23 which integrates the partial product to the extended sign bit of the multiplicand A, and a selector 21 which discriminates whether multiplicand is to be performed between signed or unsigned numbers from a select signal and provides extended signal bits to the multiplier B and multiplicand A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier, and more particularly to a modified Booth algorithm (mo
Apply the dified Booth algorithm) and apply the signed number (sign
ed number) and the unsigned number (unsigned number)
), The present invention relates to a signed / unsigned number-use multiplier capable of selectively performing multiplication between the two).

[0002]

2. Description of the Related Art Multiplication is a digital signal processing (DSP) process for processing image data.
This is one of the essential operations in g).

In practice, arithmetic units such as arithmetic and logic units (ALUs) in central processing units (CPUs) require multipliers, which multiply between signed numbers and unsigned. The multiplication between numbers must be done selectively.

As a method for realizing multiplication between signed numbers and multiplication between unsigned numbers in an arithmetic logic operation unit, there is a method of using both the multiplier for unsigned numbers and the multiplier for signed numbers. is there. However, this method has a disadvantage that circuit space is wasted because two multipliers are used.

As another method for realizing the multiplication between signed numbers and the multiplication between unsigned numbers in an arithmetic logic operation unit, the difference between the multiplication result between signed numbers and the multiplication result between unsigned numbers is calculated. There is a method of separately configuring an additional circuit for compensation.

In this method, the most significant bit (M
When SB) is "1", the remaining bits except the most significant bit of other multipliers are added to the final multiplication result. However, this method also has a disadvantage that it is difficult to obtain the square layout which is the advantage of the array multiplier.

On the other hand, US Pat. No. 5,153,850 ("METHOD AND APPARATUS FOR MODIFYING TWO'S COMP
LEMENT MULTIPLIER TO PERFORM UNSIGNED MAGNITUDE MU
LTIPLICATION ”) includes multiplication between unsigned numbers and 2
A multiplier for performing multiplication between the complements of is disclosed.

This US patent describes multiplication between unsigned numbers and 2
In order to selectively perform the multiplication between the two's complements, an addition circuit corrects the multiplication result between the two's complements to obtain an unsigned number result.

As a multiplication algorithm, the modified Booth's algorithm is Macro
Annaratone) 's "Digital CMOS Circuit Design"
(Pp 211-221).

The modified Booth algorithm is a kind of recoding algorithm, in which a multiplier is divided into a predetermined bit set, an operation corresponding to each bit set is performed on a multiplicand, and a partial product which is an intermediate result is obtained. Then, the partial products generated for each bit set are added together to obtain the final result of the multiplication of the multiplier and the multiplicand. This modified Booth algorithm takes into account that "0" has no effect on multiplication, and can improve the operation speed of multiplication. Hereinafter, a two's complement multiplier to which the existing Booth algorithm is applied will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the configuration of a normal 2's complement multiplier. As shown in the figure, a normal 2's complement multiplier includes an encoder 1, a code transmission unit 2, a shift / inversion unit 3, first to third partial product generators 4, 5, 6 and a carry look ahead. It consists of an adder 7. The multiplier shown in FIG. 2 is an 8 × 8 multiplier, where A is the multiplicand and B is the multiplier.

The encoder 1 to which the 8-bit multiplier B is input encodes a group of bits of the multiplier divided into 3 bits to generate a recoding digit (-2x, -1x, 0x, + 1x, + 2x) set is generated.

Each recoded digit of this set of recoded digits is transmitted to the shift / inversion unit 3 and the corresponding one of the first to third partial product generators 4, 5, 6 to shift / invert unit 3. The corresponding operation is performed on the 8-bit multiplicand A in the first to third partial product generators 4, 5, and 6. The result of the operation performed in this way is output to the outside through carry look ahead adder 7. Further, the code transmission unit 2 is for processing the code bits in which the multiplicand is expanded.

[0014]

However, the above-described multiplier has a disadvantage that it can multiply signed numbers represented by 2's complement, but cannot multiply unsigned numbers.

An object of the present invention is to provide a combined signed / unsigned number multiplier capable of selectively performing a multiplication between signed numbers and a multiplication between unsigned numbers by applying a modified Booth algorithm for multiplication. To provide.

[0016]

Signed / according to the present invention
The unsigned multi-purpose multiplier is an encoder that codes a bit set of a multiplier to generate a recode digit corresponding to each bit set, and a shift and inversion operation of a multiplicand according to a recode digit transmitted from the encoder. A shift / inversion unit for generating a product and a corresponding operation are performed on the multiplicand according to the recode / digit transmitted from the encoder, and the operation result is added to the partial product output from the shift / inversion unit. A first partial product generator for generating a predetermined partial product, and an operation result for the multiplicand according to the output digit of the preceding stage, which is sequentially connected to the output of the first partial product generator and the transmitted recode digit, and is added. Second to fourth partial product generators for respectively generating partial products, the shift / inversion unit, and the first unit. A code transmission unit connected to the fourth partial product generator for accumulating and adding partial products for the extended code bits of the multiplicand, and multiplication between signed numbers or unsigned numbers depending on an input selection signal And a selector that provides extension code bits to the multiplier and the multiplicand based on the determination result.

Further, the signed / unsigned number-use multiplier according to the present invention is such that the carry output from the shift / inversion unit and the first to third partial product generators and the fourth partial product generator output. Sum and carry are entered,
It is characterized by including a carry look ahead adder for accumulating and adding this.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Before describing the multiplier according to the present invention, the multiplication process to which the embodiment of the present invention is applied will be described by taking the multiplication of 8 bits × 8 bits as an example.

Letting A be the multiplicand and B be the multiplier, (-4) ×
The multiplication of (-2) can be expressed as a signed number, an unsigned number, and a binary number as follows.

[0021]

## EQU00001 ## A.times.B (-4) .times. (-2) .... Signed number + 252.times. + 254 ..... Unsigned number 1111 1100.times.1111 1110 ..... Binary number

The multiplication process between the signed numbers expressed as described above can be expressed by a mathematical expression as follows.

[0023]

## EQU00002 ## A 11 | 11 | 11 | 00 × B 11 | 11 | 11 | 10 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−− -(-2x) 00 | 00 | 00 | 00 | 00 | 00 | 10 | 00 (0x) 00 | 00 | 00 | 00 | 00 | 00 | 00 (0x) 00 | 00 | 00 | 00 | 00 | 00 (0x) 00 | 00 | 00 | 00 | 00 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− P 00 | 00 | 00 | 00 | 00 | 00 | 10 | 00

In the above formula, (-2x) and (0x) on the left side of the intermediate block are the recoded digits of the multiplier. In order to obtain this recode digit, first, the three bits of the multiplier are combined into one bit set, and it is determined which of the predetermined recode digits each bit set corresponds to.
The table for determining the bit set is as follows.

[0025]

Table 1 Bit (i + 1) Bit i Bit (i-1) Recode Digit 0 0 0 0xx 0 0 1 + 1x 0 1 0 + 1x 0 1 1 + 2x 1 0 0 -2x 1 0 1 -1x 1 1 0 -1x 1 1 1 0x

The recode digit 0x in the above table performs the operation of adding 0 to the partial product, and the recode digit 1x.
Is an operation for adding a multiplicand A to the partial product, a recode digit 2x is an operation for adding a double multiplicand 2A to the partial product, and a recode digit (-1x) is a subtraction of the multiplicand A from the partial product. The recode digit (−2x) subtracts the double multiplicand 2A from the partial product.

As a result, the recoded digits 0x, 0x, 0x, (-2x) are obtained in order from the upper bits of the multiplier B. Then, to obtain -2A necessary for the operation performed corresponding to the (-2x) recoded digit,
After inverting, add 1 and shift 1 bit to the left.

Thus, in the multiplication, four partial products are obtained, and the result P becomes the decimal number 8.

On the other hand, for multiplication between unsigned numbers, two bits must be extended before the sign bit of the input. This can be expressed as a mathematical expression as follows.

[0030]

A 00 | 11 | 11 | 11 | 00 × B 00 | 11 | 11 | 11 | 10 −−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−− (−2x) 11 | 11 | 11 | 10 | 00 | 00 | 10 | 00 (0x) 00 | 00 | 00 | 00 | 00 | 00 | 00 (0x) 00 | 00 | 00 | 00 | 00 | 00 (0x) 00 | 00 | 00 | 00 | 00 (+ 1x) 11 | 11 | 11 | 00 −−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−− P 11 | 11 | 10 | 10 | 00 | 00 | 10 | 00

The recode digit in the above equation is also generated from the bit set of the multiplier, and the partial product is increased by one compared with the multiplication between the signed numbers to become five. Taking the above multiplication as an example, the bit set of the multiplier is (001111111).
For each multiplier B which is 0), one bit is superposed on each bit set, and (001), (111), (1
11), (111), and (100). When the last bit set is 2 bits, the third bit of the bit set is 0.

It can be seen that the multiplication between the unsigned numbers is accurate and efficient in comparison with the general multiplication process expressed by the following formula.

[0033]

## EQU00004 ## A 11 | 11 | 11 | 00 × B 11 | 11 | 11 | 10 −−−−−−−−−−−−−−−−−−−−−−−−−−−−− 00 | 00 | 00 | 00 1 | 11 | 11 | 10 | 0 11 | 11 | 11 | 00 | 1 | 11 | 11 | 10 | 0 11 | 11 | 00 | 1 | 11 | 11 | 10 | 0 11 | 11 | 11 | 00 1 | 11 | 11 | 10 | 0 −−−−−−−−−−−−−−−−−−−−−−−−−−−− P 11 | 11 | 10 | 10 | 00 | 00 | 10 | 00 When this is expressed by a decimal number, 252 × 254 = 640
It will be 08.

Next, a multiplier according to the present invention which can selectively perform the multiplication between the signed numbers and the multiplication between the unsigned numbers will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of a signed / unsigned number-use multiplier according to the present invention.

As shown in FIG. 1, the multiplier according to the present invention comprises a selector 21, an encoder 22 and a code transmission unit 2.
3, a shift / inversion unit 24, first to fourth partial product generators 25, 26, 27, 28 and a carry look ahead adder 29. The multiplier shown in FIG. 1 is an 8 × 8 multiplier, where A is the multiplicand and B is the multiplier.

Referring to FIG. 1, the 8-bit multiplier B is 3
The encoder 22 that is divided into bits and inputs the coded bit sets of the multipliers corresponds to the recoded digits (-2x, -1x, 0x, + 1x, +) corresponding to the bit sets.
2x) set is generated. The method of generating the recoded digit is as described above.

Each recoded digit of the set of recoded digits is transmitted to a corresponding one of the shift / invert unit 24 and the first to fourth partial product generators 25-28. Shift / inversion unit 24 and first to fourth
In the partial product generators 25 to 28, the corresponding operation is performed on the 8-bit multiplicand A according to the input recoding digit. The shift / inversion unit 24 receives the recoded digit provided from the encoder 22 and the multiplicand A divided into 3 bits, performs an operation corresponding to the recoded digit on each 3 bits of the multiplicand A, and First sum and carry generated from the result
Output to the partial product generator 25. In this embodiment,
Partial product means sum and carry.

The first partial product generator 25 receives the sum and carry output from the shift / inversion unit 24, and the second to fourth partial product generators 26, 27 and 28 are from the preceding partial product generators. The output sum and carry are input.
In addition, the corresponding recode digit is input from the encoder 22 to each of the partial product generators 25 to 28, and the multiplicand A divided into 3 bits is input. Each partial product generator 25
˜28 performs an operation corresponding to the input recode digit on the input multiplicand A and adds the result to the sum and the carry input from the previous stage to generate a new sum and carry. The generated sum and carry are output to the next stage. In order to perform such a function, each of the partial product generators 25 to 28 is internally provided with the shift / inversion unit 2.
4 includes a shift / inversion means having the same structure, and an addition means for adding the sum and carry input from the preceding stage and the output of the shift / inversion means.

Next, the operation of the shift / inversion unit 24 or each of the partial product generators 25 to 28 corresponding to each of the recoded digits will be described in detail.
First, when the recoded digit is (-2x), in order to obtain -2A from the multiplicand A, after inverting A, 1
Is added, and the data obtained by shifting left by 1 bit is added to the partial product which is the intermediate result of the previous stage.

When the recode digit is (-1x), in order to obtain -A from the multiplicand A, the data obtained by inverting A and adding 1 is the intermediate result of the previous stage. Add to product. When the recode digit is 0x, 0 is added to the partial product which is the intermediate result of the previous stage, but there is no substantial operation effect by 0x. Recode
When the digit is 1x, A is added to the partial product which is the intermediate result of the previous stage. When the recode digit is 2x, 2A is obtained from the multiplicand A, so that data obtained by shifting A to the left by 1 bit is added to the partial product of the preceding stage.

The outputs of the shift / inversion unit 24 and the first to fourth partial product generators 25 to 28 which operate in this way are output to the outside through the carry look ahead adder 29.

The code transmission unit 23 includes a shift / inversion unit 24, first to third partial product generators 25 and 26,
The partial products of the expanded sign bit of the multiplier B and the multiplicand A output from 27 are accumulated and added, and the addition result is output to the fourth partial product generator 28.

Carry Look-Ahead Adder 29
Is the sum and carry generated in the fourth partial product generator 28 and the carry output from the shift / inversion unit 24 and the first to third partial product generators 25, 26, 27, and the inputs are input in order. Add to produce a 16-bit output. Such a carry look ahead adder 29 speeds up the overall operation speed of the circuit.

In the multiplier according to the present invention, the selector 21
Can select multiplication between unsigned numbers and multiplication between signed numbers. For example, if the selection signal sel is “1”, it is a multiplication between signed numbers, and if the selection signal sel is “0”, it is a multiplication between unsigned numbers.

In this case, when the selection signal sel is "0", the extended sign bit of the multiplier B and the multiplicand A is always set to "0". That is, A <9>, A <8> and B <9>, B <8> output from the selector 21 become “0”.

On the other hand, if the selection signal sel is "1",
Most significant bit A, which is the sign bit of multiplier B and multiplicand A
The value of the extension sign bit is determined according to the states of <7> and B <7>. That is, when A <7> or B <7> is “1”, A <9> A <8> or B <9> B <8> output from the selector 21 becomes “11”, respectively. , A
When <7> or B <7> is “0”, A <9> A <8> or B <9> B <8> output from the selector 21.
Respectively become "00". Therefore, when the selection signal sel is controlled from the outside, the selector 21 appropriately provides the extension bits to the multiplier B and the multiplicand A according to whether the multiplication is between signed numbers or unsigned numbers, thereby In the multiplier according to the present invention, multiplication between signed numbers and multiplication between unsigned numbers can be processed.

[0047]

As described above in detail, according to the present invention, it is possible to provide a multiplier which selectively applies multiplication between signed numbers and unsigned numbers to which the modified Booth algorithm is applied. . In particular, in the present invention, when multiplying between unsigned numbers, it is possible to perform not only multiplication between signed numbers but also multiplication between unsigned numbers by providing an extension bit of an input through a selector. The configuration is simple, does not reduce the operation processing speed, and can occupy a relatively small area when mounted on an integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a signed / unsigned number-use multiplier according to the present invention.

FIG. 2 is a configuration block diagram of a normal 2's complement multiplier.

[Explanation of symbols]

 21 selector 22 encoder 23 code transmission unit 24 shift / inversion unit 25, 26, 27, 28 first to fourth partial product generator 29 carry-look-ahead adder

Claims (4)

[Claims] 1. A multiplier for performing M × N multiplication, wherein: an encoder for coding a bit set of a multiplier to generate a recode digit corresponding to each bit set; and a multiplicand by a recode digit transmitted from the encoder. Shift / inversion unit for performing partial shift and inversion operations of the above, and a corresponding operation on the multiplicand according to the recode digit transmitted from the encoder, and the operation result is output from the shift / inversion unit. A first partial product generator for adding the generated partial product to generate a predetermined partial product, and an output data of the first partial product generator, which is connected to the output of the first partial product generator in accordance with the transmitted decoding digit of the preceding stage. Second to fourth partial product generators for generating partial products by adding the calculation results for the multiplicands, respectively, A code transmission unit connected to the unit and the first to fourth partial product generators, for accumulating and adding partial products for the extended code bits of the multiplicand, and multiplying between signed numbers by an input selection signal A signed / unsigned number combined multiplier comprising: a selector that determines whether or not multiplication is between unsigned numbers and provides an extension sign bit to a multiplier and a multiplicand based on the determination result. 2. The signed / unsigned number-combined multiplier according to claim 1, wherein the partial product comprises a sum and a carry. 3. The carry output from the shift / inversion unit and the first to third partial product generators and the sum and the carry output from the fourth partial product generator are input, and accumulated and added. 3. The signed / unsigned number multiplier as claimed in claim 2, further comprising a carry look ahead adder. 4. The signed / unsigned number-combined multiplier according to claim 1, wherein the M × N multiplication is an 8 × 8 multiplication.