JP2734438B2 - Multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication device, and more particularly, to obtaining a product of two data, obtaining some partial products, obtaining the product by adding the partial products, and obtaining one product from the product. The present invention relates to a product-sum operation device that adds data to obtain a final product-sum operation value.

[0002]

2. Description of the Related Art FIG. 7 is a diagram for explaining a conventional general multiplication logic using a second-order Booth algorithm.

When multiplying the multiplicand X and the multiplier Y, the multiplier Y is divided into combinations of three bits, and a partial product Pn (i = 0 to 8) is obtained according to the conversion rule shown in FIG. ,
Next, a method is used in which addition is performed on each partial product Pn according to the respective weights to obtain a product of the multiplicand X and the multiplier Y. As shown in FIG. 7 (B), according to the logical values of three consecutive bits (y _{2n + 1} , y _2n , y _2n-1 ) of the multiplier Y, 0, ± X, ± A value of 2X is selected. In order to facilitate understanding of the multiplication logic, the outline of the multiplication logic will be described briefly.
(= “01010” in 5-bit binary notation), the multiplier Y is “2”
To explain with a simple example of (= “00010”), first, one “0” is added to the lower digit of the LSB (least significant bit) of the multiplication Y, and (y _{2n + 1} ) is added according to FIG. , Y _2n , y _2n-1 )
= (Y ₁ , y ₀ , y ₋₁ ) is taken as (1,0,0) (where y ₋₁ = 0), and the partial product P0 for this combination
Is set to −2X, and then the multiplicand Y overlaps the previous combination (y ₁ , y ₀ , y ₋₁ ) by 1 bit, so that (y ₃ , y ₂ , y ₁ ) = (0, The partial product P1 for the combination of 0, 1) is set to + X, which is quadrupled (4X) corresponding to a right shift of 2 bits, added, and 4X + (-2X) is added to obtain the multiplication result 2X (= “1010
0 ").

FIG. 8 further shows that the addend Z is added to the product obtained by the partial product for the multiplicand X and the multiplier Y,
A procedure for obtaining the final product-sum operation value X * Y + Z is schematically shown.

When the multiplication inputs X and Y using this theory are 16
FIG. 6 shows an example of a conventional configuration of a multiplication device having 32 bits and an addend input Z of 32 bits.

Referring to FIG. 6, this conventional multiplication device comprises:
Eight-stage carry save adder (referred to as "CSA") 202, 204, 206, 208, 210, 21 for performing signed 16-bit multiplication
2, 214, 216 and a selector 20 for selecting a partial product to be input to the 8-stage carry save and add circuit (CSA)
1, 203, 205, 207, 209, 211, 21
3 and 215, a carry save and add circuit (CSA) 218 for calculating a partial product of the sign bit portion, and a carry save and add circuit (CSA)
A partial product operation circuit for a sign bit part by a selector 217 for selecting a partial product to be input to 218;
Carry save addition circuit (CSA) for adding bit data
219 and a carry propagation addition circuit (Carry Propagation A) for converting the product-sum operation result into a two's complement representation.
dder, “CPA”) 220 and booth (Bo)
booth (B) for obtaining a partial product by the method of
o) decoder circuit 222.

The multiplication device shown in FIG. 6 multiplies the input data X and Y with the 16-bit sign and adds the 32-bit data resulting from the multiplication and the 32-bit input data Z as follows.

First, the input data X is sign-extended to 18 bits, and the selectors 201, 203, 2
05, 207, 209, 211, 213, 215, 21
It is sent to 7.

Further, data twice as large as the input data X (2
* X) is zero-extended to 18 bits and the selectors 201, 203, 205, 207, 209, 2
11, 213, 215, and 217.

[0010] The input data Y is sign-extended to 18 bits and then divided into combinations of 3 bits each.
, A control signal for obtaining the partial product Pn is generated, and the selector units 201, 203,
205, 207, 209, 211, 213, 215, 2
It is sent to 17. The selector signals 201, 203, 205, 207, 209,
The partial product Pn is determined by 211, 213, 215, and 217.

Next, the obtained partial product Pn is used as a carry save adder (CSA) 202, 204, 206, 20.
8, 210, 212, 214, 216 and 218 are added according to the weight.

Further, the result of addition of the partial product Pn is 3
2-bit data Z is carried and stored and added (CSA) 2
The result output of the carry save and add circuit (CSA) 218 is converted to complete two's complement data by a carry propagation adder (CPA) 220.

[0013]

The conventional multiplier shown in FIG. 6 includes a plurality of stages of carry save and add circuits (CSAs) each having a data bit width, and performs high-speed operations.

However, the conventional multiplier has a problem that the proportion of the multiplier in the chip area is increased due to the provision of the carry save adder circuit (CSA) of a plurality of stages. ing.

Currently, the function required for the product-sum operation is to add signed data to the signed multiplication result.

However, when such a configuration is used, the partial product of the sign part is always zero (0) during the product-sum operation. This is because, in this product-sum operation, since the signed data is handled, the combination of bits (y _{2n + 1} , y _2n , y _2n-1 ) used for the operation of the sign part is “000”,
Or, it is "111", and in this case, the partial product becomes 0 as shown in FIG. Therefore, the carry save and add circuit (CSA) 218 becomes unnecessary.

The present invention has been made by paying attention to this point, and it is possible to reduce the circuit scale by selectively using the carry save addition circuit (CSA) of the code section in limited LSI resources. It is an object of the present invention to provide a multiplication circuit.

[0018]

In order to achieve the above object, the present invention comprises a plurality of carry save and add circuits (CSAs) for calculating a partial product of a multiplicand (X) and a multiplier (Y); Carry save addition circuit (CS
A) and a carry propagation addition circuit (CPA) for adding the output of the partial operation circuit, the carry for calculating the partial product of the sign bit portion. A selector capable of selecting data (Z) in addition to the partial product (Pn) is added to the input to the save addition circuit (CSA) so that the product-sum operation can be performed without adding a new adder. A multiplication device is provided.

According to the present invention, a CSA circuit and a CPA
CS of the last stage in the multiplication circuit constituted by the circuit
The input to the A circuit is provided with a selector for selecting a multiplicand X at the time of unsigned multiplication and an addition number Z at the time of the product-sum operation. In addition to calculating the product, the final stage CS
A circuit is used to add the addend Z to obtain the final sum-of-products operation value, and the circuit size and chip area are reduced by using a common CSA circuit for multiplication and product-sum operation. It was done.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram for explaining an operation process in the multiplier according to the embodiment of the present invention. Multiplicand X,
When performing the multiplication by the multiplier Y, the multiplier Y is divided into a combination of three bits, a partial product Pn is obtained according to the Booth's conversion rule shown in FIG. A corresponding addition is performed to obtain a product of the multiplicand X and the multiplier Y.

FIG. 3 is a diagram for explaining the operation process when the product-sum operation is performed. The addend Z is added to the partial product Pn other than the partial product of the sign part, and the final product-sum operation value (X * Y + Z)
Ask for.

FIG. 1 shows a configuration example of a multiplication device according to an embodiment of the present invention, in which a multiplication input is 16 bits each and an addend input is 32 bits.

Referring to FIG. 1, the multiplication apparatus according to the present embodiment includes an eight-stage carry save adder (Carry Save Adder, "CS") for performing signed 16-bit multiplication.
A ") 102, 104, 106, 108, 11
0, 112, 114, 116 and selectors 101, 103, 105, 107, 109, 111, which select partial products to be input to the 8-stage carry save and add circuit (CSA).
And a carry-save adder (CSA) 11 for calculating a partial product of the sign bit portion during multiplication and adding 32-bit data during multiplication and accumulation.
8 and a selector 117 for selecting data to be input to the carry save and add circuit (CSA).
And a carry propagation addition circuit (Carry Pr) for converting the operation result into a two's complement representation.
oppagate Adder (referred to as “CPA”) 11
9 and B for obtaining a partial product by the method of Booth
and an oth decoder circuit 121.

In the multiplication device according to the present embodiment shown in FIG. 1, for example, input data X and Y with a 16-bit code
, And the multiplication result of 32-bit data and 32 bits
The addition of the bit to the input data Z is performed as follows.

First, the input data X is sign-extended to 18 bits, and the selectors 101, 103, 1
05, 107, 109, 111, 113, 115, 11
It is sent to 7.

Further, data twice as large as the input data X is 1
Selector 1 of the partial product operation circuit, which is zero-extended to 8 bits
01, 103, 105, 107, 109, 111, 11
3, 115.

The input data Y is sign-extended to 18 bits and then divided into combinations of 3 bits each. In the Booth decoder circuit 121 shown in FIG. 1, the partial product Pn is calculated according to the Booth method. A control signal to be obtained is generated, and the selector units 101, 103, 105, 107, 109, 111, 1 of the partial product generation circuit are generated.
13 and 115.

The selectors 101, 103, 105, 107, 109, and 11 of the partial product generating circuit are controlled by the control signal.
The partial product Pn is obtained at 1, 113 and 115.

Next, the obtained partial product Pn is used as a carry save adder (CSA) 102, 104, 106, 10
8, 110, 112, 114, and 116 are added according to the weight.

The selector 117 selects 32-bit data Z as an input to the carry save and add circuit (CSA) 118.

The result of adding the partial products P0 to P7 and 32
Bit data Z is a carry save and add circuit (CSA) 11
The output result of the carry save addition circuit (CSA) 118 is converted by the CPA 119 into complete two's complement data.

The multiplication of the input data X and Y without the 16-bit sign by the multiplication device shown in FIG. 1 is performed as follows.

First, the input data X is sign-extended to 18 bits, and the selectors 101, 103, 1
05, 107, 109, 111, 113, 115, 11
It is sent to 7. Further, data twice as large as the input data X is zero-extended to 18 bits, and the selectors 101, 103, 105, 107, 109, 111, 1
13 and 115. After the input data Y is sign-extended to 18 bits, it is divided into combinations of 3 bits each, and the Booth (Booth) decoder circuit 12 shown in FIG.
In step 1, a control signal for obtaining the partial product Pn is generated according to the Booth's method, and the selector units 101, 103, 105, 107, and 10 of the partial product generation circuit are generated.
9, 111, 113, and 115. The selector signals 101, 103, 1
05, 107, 109, 111, 113 and 115 determine the partial product Pn.

Next, the obtained partial product Pn is used as a carry save adder (CSA) 102, 104, 106, 10
8, 110, 112, 114, and 116 are added according to the weight. The selector 117 selects X or 0 as the partial product P8 of the sign part as an input to the carry save addition circuit (CSA) 118. The result of addition of the partial products P0 to P7 and the partial product P8 are added by a carry save and add circuit (CSA) 118, and the output result of the carry save and add circuit (CSA) 118 is added to the carry propagation adder (C
PA) 119 to complete two's complement data.

FIG. 4 is a circuit diagram showing a selector (a selector 1 in FIG. 1) of a partial product generator in a multiplication circuit according to an embodiment of the present invention.
FIG. 2 is a diagram showing a circuit configuration of the circuit of FIG.

A combination of three bits of the multiplier Y (y _{2n + 1} , y
_2n , y _2n-1 ) are decoded by a Booth (Booth) decoder 701, and one of X, -X, 2X, -2X, and 0 is selected as a partial product Pn. That is, one of 2X and X is selected by the first-stage selector, and one of the inverted signal and the non-inverted signal of the output selected by the first-stage selector is selected by the second-stage selector.
Either the output from the second selector or 0 is selectively output by the selector at the stage.

FIG. 5 is a diagram showing a circuit configuration of a selector 117 for an addend Z at the time of multiply-accumulate operation and a partial product of a sign part at the time of multiplication in a multiplying circuit according to an embodiment of the present invention.

At the time of multiplication, a 3-bit combination (y ₁₇ , y ₁₆ , y ₁₅ ) of the sign bit part of the multiplier Y is decoded by the Booth decoder 701, and one of X and 0 is set as a partial product P8. Selected.

At the time of product-sum operation (when the product-sum operation command signal is in an active state), data Z is selected as an output P8 by this selector circuit, and the carry save addition circuit (CS
A) Output to 118.

[0041]

As described above, according to the present invention,
A carry save and add circuit (CAS) for adding signed data to a signed multiplication result at the time of a product-sum operation, and a carry save and add circuit (C) for adding a partial product of a sign part during multiplication.
By using SA) properly, there is an effect that the circuit scale of the multiplication circuit can be reduced with limited LSI resources.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a multiplication operation process according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a product-sum operation according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a circuit configuration of a selector of a partial product generation unit according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a circuit configuration of a selector of a partial product generation unit of a coding unit according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional multiplication device.

FIG. 7 is a diagram for explaining multiplication processing in a conventional multiplication device.

FIG. 8 is a diagram for explaining a product-sum operation in a conventional multiplication device.

[Explanation of symbols]

101, 103, 105, 107, 109, 111, 1
13, 115, 117, 201, 203, 205, 20
7, 209, 211, 213, 215, 217 partial product generator selector circuit 102, 104, 106, 108, 110, 112, 1
14, 116, 118, 202, 204, 206, 20
8, 210, 212, 214, 216, 218, 219
Carry saving and adding circuit 119, 220 Carry propagation adding circuit 120, 221 Result storage register 121, 222, 701, 801 Booth decoder circuit

Claims (4)

(57) [Claims] 1. A plurality of carry save and add circuits (CSA) for calculating a partial product of a multiplicand (X) and a multiplier (Y), and a carry save and add circuit (CSA) for calculating a partial product of a sign bit part.
And a carry propagation addition circuit (CPA) for adding the output of the partial operation circuit, and a carry save addition for calculating the partial product of the sign bit portion. A selector that can select data (Z) in addition to the partial product (Pn) is added to the input to the circuit (CSA) so that the product-sum operation can be performed without adding a new adder. Multiplying device. 2. A multistage carry save and add circuit (CSA) for calculating a partial product of a multiplicand (X) and a multiplier (Y), and a carry save and add circuit (CSA) for calculating a partial product of a sign bit part. In the multiplication device provided with the following, the multiplicand (X) at the time of unsigned multiplication and the addition number (Z) at the time of the product-sum operation are selected as inputs to the carry-save addition circuit (CSA) at the last stage. For carrying out the multiplication operation, the carry save addition circuit (CS
A) is used to add the partial product (Pn) to obtain the final product, and at the time of the product-sum operation, the carry-save addition circuit (CS
A) A carry-save addition circuit (CSA) is shared in the process of calculating the partial product and the product-sum operation value so that the final product-sum operation value is obtained by using A) for the addition of the addend (Z). A multiplication device characterized by the above-mentioned. 3. The carry save addition circuits (CSA) other than the last stage each perform multiplication (X) according to a combination of signal values of predetermined bits of a multiplier (Y) input to a decoder circuit during multiplication. And a selector circuit for outputting a predetermined value of the multiplicand as a partial product to the corresponding carry save and add circuit (CSA) in response to a selection signal output from the decoder circuit for selecting a predetermined value. The multiplication device according to claim 1 or 2, wherein 4. The selector receives a selection signal from the decoder circuit and outputs a partial product to the corresponding carry-save addition circuit (CSA) at the final stage. At the time of a product-sum operation, the adder (Z) is used. Is output to the carry save addition circuit (CSA).