JP2675087B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a microcomputer, a first operation mode in which an input partial product is output as it is for the purpose of increasing the multiplication speed, and a multiplicand is added to the partial product and output. Of a plurality of calculation modes including a second calculation mode in which the multiplicand is doubled and output to the partial product, and a fourth calculation mode in which the multiplicand is subtracted from the partial product and output. A microcomputer provided with a multiplication unit for selecting and executing one mode according to a predetermined mode control signal and storing the execution result in an output latch, wherein an n-bit multiplier set in an accumulator is right-shifted by 2 bits. Along with
A predetermined mode control signal for setting the shift-out data of the output latch in the bit vacated by the shift and for selecting and executing at least the first to fourth operation modes according to the value of the right-shifted 2 bits. A mode control signal output circuit for outputting is provided, and the mode control signal output circuit selects the first operation mode if the addition value of the lower 2 bits of the accumulator and a predetermined flag is 0 or 4. If it is 1, the second operation mode is selected, if it is 2, the third operation mode is selected, and if it is 3, the fourth operation mode is selected, and the first to third When the operation mode is selected, the flag is set to 0.
Is set, the flag is set to 1 when the fourth operation mode is selected, and when a carry or borrow occurs as a result of executing the first to fourth operation modes, the high order of the output latch It is characterized in that the logic of the dummy data put in 2 bits is inverted.

[Industrial applications]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to improving the operation speed of a microcomputer that performs repeated addition / shift operations.

2. Description of the Related Art Recently, microcomputers play an important role in fields such as high-speed automatic control (for example, engine control of automobiles), and there is a demand for even higher calculation speeds.
Especially, this demand tendency is strong for the multiplication speed.

[Conventional technology]

In the multiplication in the microcomputer, it is basically necessary to repeatedly add the multiplicands by the number of multipliers, but in this case, the number of additions is required by the number of multipliers, and therefore the operation speed is slow. Therefore, the actual calculation is often performed as follows.

In the present specification, numerical values are represented by a subscript 10 in the case of a decimal expression, and no particular subscript is added in the case of a binary expression.

Multiplication in decimal representation is performed by multiplying the value of each digit of the multiplier and the multiplicand to obtain the partial product for each digit of the multiplier, then shifting each partial product according to the digit of the multiplier, and then Although the added value of the partial product is used as the multiplication result, in the case of binary operation, the multiplicand is shifted and added to the answer only when the value of each bit of the multiplier is "1", and the result of "0" Sometimes it's a simple operation like only shifting. That is, it suffices to determine whether to perform shift / addition or only shift according to each bit (only "0" or "1" can be taken) of the binary representation number that is a multiplier. According to this method, the multiplier bit
You will be adding.

[Problems to be solved by the invention]

However, in such a conventional multiplication method, it is necessary to perform shift / addition corresponding to the number of bits of the multiplier, and particularly when handling multi-bit data, there is a problem of increasing the multiplication speed.

Therefore, an object of the present invention is to increase the speed of multiplication by reducing the total number of shifts and additions required for one multiplication process by enabling shifts and additions for every 2 bits of the multiplier. There is.

[Means for solving the problem]

In the present invention, in order to achieve the above object, a first operation mode in which an input partial product is output as it is, a second operation mode in which a multiplicand is added to a partial product and the result is output, and a multiplicand that is double the partial product A third operation mode for adding and outputting, and a fourth operation mode for subtracting the multiplicand from the partial product and outputting
Is a microcomputer provided with a multiplication unit that selects and executes one of a plurality of operation modes including a plurality of operation modes in accordance with a predetermined mode control signal, and stores the execution result in an output latch, wherein n is set in an accumulator. The bit multiplier is right-shifted by 2 bits, the shift-out data of the output latch is set in a bit vacated by the shift, and at least the first to fourth operations are performed according to the right-shifted 2-bit value. A mode control signal output circuit for outputting a predetermined mode control signal for selectively executing a mode is provided, and the mode control signal output circuit is configured such that when the value of the lower 2 bits of the accumulator and the predetermined flag are 0 or 4. If there is, the first operation mode is selected, if it is 1, the second operation mode is selected, and if it is 2, the third operation mode is selected. Mode is selected, and if it is 3, the fourth operation mode is selected, and when the first to third operation modes are selected, the flag is set to 0 and the fourth operation mode is selected. When the flag is set to 1
And a carry or borrow is generated as a result of executing the first to fourth operation modes, the logic of the dummy data to be put in the upper 2 bits of the output latch is inverted by 4. .

[Action]

In the present invention, the multiplier is divided into 2 bits each.
The operations necessary for the shift / addition from the first operation mode to the fourth operation mode are performed according to the bit values (0 _{10 to} 3 ₁₀ ).

Therefore, the number of shifts / additions executed is reduced corresponding to the number of divisions of the multiplier, and as a result, the multiplication speed is increased.

In addition, the size of the accumulator is set to the number of bits of the multiplier (n
It is not necessary to make more than (bit), and the hardware scale can be reduced.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 3 are diagrams showing an embodiment of a microcomputer according to the present invention, in which an arithmetic precision length of n bits (for example, n
= 16) applied to a microcomputer.

First, the configuration will be described. In FIG. 1, reference numeral 1 is a microcomputer, and the microcomputer 1 is an RA.
A storage device 2 such as an M or a ROM and a register group 3 having a large number of registers R _{1 to} Rn are provided, and an accumulator 4, an ALU 5, first to third flags 6 to 8 and a control signal output circuit 9 are provided. It includes a multiplication unit 10 including the same. In addition, 11 is an n-bit data bus, 12 is an n-bit address bus, 13 is a resource bus, 14 is an I / O, and 15 is a resource.
The 1 and the address bus 12 are connected to the storage device 2, the register group 3 and the multiplication unit 10 described above, and also to the resource bus 13.

FIG. 2 is a configuration diagram of the multiplication unit 10. The multiplication unit 10 is the first
As shown in the figure, it is configured to include an accumulator 4, an ALU5, first to third flags 6 to 8 and a control signal output circuit 9, and the ALU5 has an n + 1 bit first and second bit. Input latch 5a, 5b and n + 1 bit output latch
5c is equipped. ALU5 is a mode control signal S _M described later.
According to at least one of the following four operation modes:

That is, the first operation mode (hereinafter M1) is a mode in which data 0 is added to the content of the first input latch 5a and the output latch 5c is latched, and the second operation mode (hereinafter M2) is the first input latch. A mode in which the contents of the second input latch 5b are added to the contents of 5a to be latched in the output latch 5c, the third operation mode (hereinafter M3), the contents of the first input latch 5a are combined with those of the second input latch 5b. A mode in which the contents doubled (shifted to the left by 1 bit) are added and latched in the output latch 5c. ・ Fourth operation mode (M4 below) From the contents of the first input latch 5a to the contents of the second input latch 5b In this mode, the contents are subtracted and latched in the output latch 5c.

The first input latch 5a latches the partial product in the middle of the calculation, and the second input latch 5b latches the multiplicand. Partial products are bus 20, data bus 11, bus 21
The contents of the output latch 5c taken in via the data bus 5 and the multiplicand are taken from the storage device 2 and the register group 3 via the data bus 11.

The third flag 8 is a 1-bit binary gate.
The contents of the flag 8 (the initial value is logical "1", for example) is ALU5.
Is inverted every time there is a carry (or borrow) input from the (n + 1) th bit of the output latch 5c. The contents of the third flag 8 are transferred to the upper 2 bits of the output latch 5c via the bus 22 as required. For example, the output latch 5c is on the right 2
When bit-shifted, it is transferred so as to be stored in the empty bit.

On the other hand, the accumulator 4 has a data capacity of n bits, and a multiplier is stored in the accumulator 4. This multiplier is stored in the storage device 2 and the register group 3 via the data bus 11.
And the sign bit SB is stored in the first flag 6. The data (multiplier) in the accumulator 4 is shifted right by 2 bits at a predetermined timing, and the output latch 5c is placed in the empty 2 bits (upper 2 bits).
The shift-out value (data shifted out by right 2 bit shift of the output latch 5c) is stored.
The lower 2 bits of the accumulator 4 are monitored by the control signal output circuit 9, and the control signal output circuit 9
Is a binary value (M1, M2) that varies depending on the value of the lower 2 bits of the accumulator 4 and the mode (M1 to M4) of the ALU5.
→ "0", M3, M4 → "1") Content of second flag 7 F _A
And are added, and the mode control signal S _M is generated according to the addition result. For example, if the addition result is "0 ₁₀ " or "4 ₁₀ ", M1
S _M that prompts _{M 2} is generated, and if the addition result is “1 ₁₀ ”, S _M that prompts _{M 2}
If the addition result is “2 ₁₀ ”, S _M that prompts M3 is generated, and if the addition result is “3 ₁₀ ”, S _M that prompts M4 is generated.

 Next, the operation will be described.

Here, the multiplication process of B × A is considered, where the multiplier is B and the multiplicand is A. However, both B and A have a data length of n bits. Now, when B is set in the accumulator 4 and A is set in the second input latch 5b of the ALU5, the partial product C (however,
At this point, the calculation is in the initial stage, so that C = 0 ₁₀ ) is simultaneously set. The sign bit of B is the first flag 6
Is stored in A and C are the first input latch 5
a, sign extension is performed according to the bit length (n + 1) of the second input latch 5b. However, in the case of unsigned multiplication, "0" extension.

The control signal output circuit 9 adds the lower 2 bits of B and the content F _A of the second flag 7 (at this time, F _A is “0”) to obtain B
The operation mode (M1 to M4) corresponding to the value of the lower 2 bits of is determined.

For example, if the value of the lower 2 bits of B is 0 ₁₀ , M1 is determined, S _M that prompts this M1 is generated, and output to ALU5. ALU5
Performs processing according to this S _M , resulting in output latch
The value (C = 0 ₁₀ ) of the first input latch 5a is set in 5c. That is, if the value of any digit of the multiplier is 0 _10, then
The partial product at that digit is set in the first input latch 5a. The lower 2 bits of the B determines the M2 if 1 _10, and outputs the ALU5 to generate S _M prompting the M2. AL
U5 executes processing according to this S _M, and as a result, the value (A) of the second input latch 5b is set in the output latch 5c. That is, any digit value of the multiplier is 1 if _10, the partial product that digit is set in the output latch 5c. Further, if the value of the lower 2 bits of B is 2 ₁₀ , the partial product at that digit is set in the output latch 5c, and if the value of the lower 2 bits of B is 3 ₁₀ , the partial product at that digit is Set in output latch 5c.

Note that if the sum of the contents F _A lower 2 bits and the second flag 7 of the accumulator 4 that contains the B is 3 _10, F _A logic "1" of the second flag 7, Also, 1 ₁₀
Alternatively, in the case of 2 ₁₀ , it becomes a logical “0”. And ALU5
When a carry or borrow is output from the ALU5 as a result of the operation in, the logic of the third flag 8 is inverted.

After that, the output latch 5c of ALU5 and accumulator 4
Performs a 2-bit right shift, the inverted value of the third flag 8 is input to the upper 2 bits of the output latch 5c vacated by this shift, and the vacant upper 2 bits of the accumulator 4 are output from the output latch 5c. The shift-out value is input. The above operation is repeated n / 2 bits times.
For example, in the case of n = 16 bits, the process is repeated 8 times, and the multiplication process of B × A is completed in 8 times except for the correction process described below.

The correction process is performed by first storing the sign bit SB of the multiplier.
The content of the flag 6 and the content of the second flag 7 F _A are related to each other. That is, if SB → “0” and F _A → “0”, the result of M1 is set in the output latch 5c, and SB → “0”.
If F _A → “1”, the result of M2 is set in the output latch 5c. If SB → “1”, F _A → “0”, the output latch 5c is set.
The result of M4 is set, and if SB → “1” and F _A → “0”, the result of M1 is set in the output latch 5c. As a result, the upper n bits of the product appear in the output latch 5c of ALU5,
The lower n bits of the product appear in the accumulator 4.

FIG. 3 is a flowchart showing the series of processing operations described above. It is to be noted that the reference numerals in parentheses in FIG. 3 are the same as the reference numerals used in FIG. 2 and indicate the same components.

As described above, in the present embodiment, when multiplying B × A, the multiplier is divided into two bits, various operation modes are determined according to the value, the partial product in the divided two-bit digit is obtained, and this is divided. Iterate the number of times to find the product.
Therefore, the number of shifts / additions required for the multiplication of B × A is n / 2 bit times, and even if correction processing is added, n / 2 bit times + 1 time is required and the multiplication speed can be increased. it can.

〔The invention's effect〕

According to the present invention, the multiplier is divided into 2 bits, and 2
It is possible to perform shift / addition with one bit.
Therefore, the total number of shifts / additions required for one multiplication can be reduced, and the multiplication speed can be increased.

In addition, the size of the accumulator is set to the number of bits of the multiplier (n
It is not necessary to increase the number of bits) or more, and the hardware scale can be reduced.

[Brief description of the drawings]

1 to 3 are diagrams showing an embodiment of a microcomputer according to the present invention. FIG. 1 is an overall configuration diagram thereof, FIG. 2 is a configuration diagram of its essential parts, and FIG. 3 is its processing operation. It is a flowchart showing. 9: Control signal output circuit, 10: Multiplier, S _M: Mode control signal.

Claims (1)

(57) [Claims] 1. A first that directly outputs an input partial product
Operation mode, a second operation mode for adding the multiplicand to the partial product and outputting, a third operation mode for adding the double multiplicand to the partial product and outputting, a second operation mode for subtracting the multiplicand from the partial product and outputting 4 is a calculation mode in which one of a plurality of calculation modes including a calculation mode is selected and executed according to a predetermined mode control signal, and the execution result is stored in an output latch. The n-bit multiplier set in step 1 is right-shifted by 2 bits, the shift-out data of the output latch is set in a bit vacated by the shift, and at least the first bit is shifted according to the value of right-shifted 2-bit
A mode control signal output circuit for outputting a predetermined mode control signal for selectively executing the fourth operation mode, wherein the mode control signal output circuit is a value obtained by adding a value of the lower 2 bits of the accumulator and a predetermined flag. Is 0 or 4, the first operation mode is selected, 1 is the second operation mode, 2 is the third operation mode, and 3 is the above operation mode While selecting the fourth operation mode, the flag is set to 0 when the first to third operation modes are selected, and the flag is set to 1 when the fourth operation mode is selected, In addition, when a carry or borrow occurs as a result of executing the first to fourth operation modes, the logic of dummy data to be put in the upper 2 bits of the output latch is inverted. Computer.