JPS5968058A - Floating point multiplier - Google Patents

Abstract

PURPOSE:To obtain a single-precision data multiplication result speedily with high precision eventually as the multiplication result of double-precision data, by arraying addition results and multiplication results in double-precision data format. CONSTITUTION:Multiplication data is inputted to a multiplier 10 by a 32-bit multiplier left input signal bus 14 and a 32-bit multiplier left input signal bus 15. The 32 upper bits of the multiplication result is outputted to an adder left input signal bus 12 and a register file through buses 16, 21, and 18, and the 32 lower bits, on the other hand, are outputted to an adder 11 through a signal line 22 as the 32 left input bits. Input to the adder 11 performed through buses 12 and 13. The 32 upper bits of the addition result are sent out to the register file and an adder left input signal bus 13 through the bus 16 and signal lines 17 and 20, and the 32 lower bits are inputted as a left input directly to the adder 11 through a signal line 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a floating arithmetic circuit, and in particular to a floating arithmetic circuit that is suitable for high-speed execution of vector arithmetic that outputs the multiplication result of single-precision data in a data format of times N degrees. It concerns multipliers.

[Prior art]

When multiplying floating data using a computer, it is often necessary to obtain the result as double-precision data in order to ensure accuracy, even if the input data is single-precision data, such as in function operations or inner product operations. However, the reality is that with conventional methods, results cannot be obtained quickly, or even if results can be obtained quickly, the accuracy is not sufficient.

For example, in a computer that uses a data format in which the exponent part is expressed as a hexadecimal power and the number of bits in the exponent part is the same for single precision and double precision, the multiplication is carried out as single precision data and the result is It is easy to obtain double precision data.

However, if the exponent is expressed as a hexadecimal power, O may occur in the first 3 bits of the mantissa even if the mantissa is normalized, so the bits that represent the mantissa It is not possible to obtain an accuracy of only a few minutes. For this reason, the exponent part is expressed as a power of 2, and in the case of double precision, a format with a larger bit length than the single precision exponent part is adopted in order to expand the range of numbers that can be expressed. is being carried out. An example of this is IEEE Computer marCh 19
8L I) I) 51-62"A propoaed 5
standard for BinaryFloatin
One example is the IEEE standard format disclosed in "g-point Arithmetic".However, in these formats, the bit lengths in the exponent part of single precision and double precision are different, so single precision data cannot be converted into double precision data. In other words, in order to obtain the result of an operation on single-precision data as double-precision data, the single-precision data must first be converted to double-precision data before the operation. After that, double-precision arithmetic is performed.

However, when performing calculations in this manner, a lot of time is required for conversion processing and double precision multiplication processing, resulting in a significant drop in performance.

[Purpose of the invention]

Therefore, an object of the present invention is to perform floating multiplication in which, when the number of bits in the exponent parts of single precision and double precision differ, the multiplication result of single precision data can be obtained as double precision data quickly and with good accuracy. It's about offering the utensils.

[Summary of the invention]

For this purpose, the present invention performs an addition operation on the exponent part and a multiplication operation on the mantissa part in single-precision data.
At that time, the addition result is corrected depending on the multiplication result, and by arranging the addition result and multiplication result obtained in this way in double precision data format, the result is the single precision data multiplication result. is obtained as the result of multiplication of double precision data.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 13.

First, an overview of the processor according to the present invention will be explained with reference to FIGS. 1 to 4. FIG. 1 shows its overall configuration, and according to this, a host (HO8T) computer 1 is connected to an arithmetic unit 3, a register file 4, a memory section 5, an address arithmetic section 6, and a microprocessor via an interface section 2. The microprogram controller 7, which is connected to a program controller 7 and whose microprogram contents are variable, sends control timing signals to the arithmetic unit 3, address arithmetic section 6, etc. by executing the microprogram under the control of the host computer 1. It outputs address signals, etc. Although the configuration of a processor constructed in this manner is not particularly new, the present invention relates to a multiplier that constitutes a part of the arithmetic unit in this configuration.

Figure 2 shows the configuration of the calculation unit.
As shown in the figure, a 32-bit multiplier 1o and a 64-bit adder 1
It is mainly composed of 1. Of these, the multiplier 1o is configured as a pipeline multiplier consisting of four stage circuits 10-1 to 10-4, and the adder 11 is configured as a pipeline multiplier consisting of four stage circuits 11-1 to 11-3. For example, U.S. Pat.
, No. 075.704. The multiplier 1o will be described in detail later, but the multiplication data input to the multiplier 1o is
A 2-bit multiplier right input signal bus 14 and a 32-bit multiplier left input signal bus 15 are provided. In addition, the upper 32 bits of the multiplication result are sent to the 32-bit adder right input signal bus 12 and the register file by signal lines 21 and 18 in addition to the 16-bit data bus 16. The lower 32 bits are signal line 22
This input signal is input to the adder J1 as the lower 32 bits of the pressure input. On the other hand, addition data is input to the adder 11 not only in the case of single-precision data, but also in the case of double-precision data being input in two steps.
This is done via a right input signal bus 12 and a 32-pit plus X6 left input signal bus 13. However, in the case of double precision data, the lower 32 bits input from the multiplier 10 are input to the adder 11.
When the lower 32 bits of the pressure input are given, only the upper 32 bits of the right input and the upper 32 bits of the left input are input from the adder 6 right input signal bus 12 and the adder input signal bus 13.

In addition, the upper 32 bits of the addition result that is the output are sent to the register file and the adder input signal bus 13 by signal lines 17 and 20 in addition to the data bus 16, while the lower 32 bits are sent to the signal line 17 and 20, respectively. 19, it is directly input to the adder 11 as a left input.

Next, to explain the register file with reference to FIG. 3, the register file 4 is mainly FIFO (1; "1rst
-(n, first-Qut) v raster 31 and 2
It is composed of a port register 33. Ii' Data is written to the IFO register 31 using the signal i.
17. Select either the adder output or the multiplier output from 18 with the selector 30, and then set the 1-bit write signal WE to 1"
By placing the FIFO register 3 in the state of
Reading of data from 1 to the adder right input number bus 12 and adder present input signal bus 13 is performed by setting the 1-bit read signal R1E to the 1'' state. Also, data is written to the 2-port register 33 by selecting either the adder output or multiplier output from the signal lines 17 and 18, or the data on the data bus 16 by the selector 32, and then writing 5 bits. Address signal W
It is written to the address specified by A. The successive output of data from the 2-port register 33 is triggered by a 5-bit read address signal RA1. By FtA2. The data read by the read address signals R, AI is sent to the adder left input signal path 13 and the multiplier piece input signal bus 15, and the data read by the read address signals R, A2 is sent to the adder 6 right input signal bus 12. and the multiplication 6 right input signal bus 14.

Finally, the fourth section regarding the memory section 5 and address calculation section 6.
To explain with reference to the figure, the memory unit 5 is composed of two identically configured memories (I) 41 and 45, and their peripheral circuit configurations are also exactly the same.

That is, writing data to the memo 1J41.45 transfers the data on the data bus 16 to the memory data write register 42.
46, the memory address register 43.
This is done by applying a write address signal from 47.

The memory address registers 43 and 47 hold address signals from the address calculation section 6, which will be described later, and increment or decrement the held address signals when necessary. Further, successive output of data from the memo 1J41, 45 is performed by applying an [output address signal] to the memory address registers 43, 47. The data read from the address specified by the address signal is sent to the address calculation unit 6 via the memory data read registers 40 and 44.
In addition to being output to the signal buses 12 to 15 and the signal line 4 mentioned above,
The data can be output onto the data bus 16 via the 8°49. Next, the address calculation section 6 will be explained. The address calculation section 6 includes a two-vote register 51 and an ALU (numerical logic operation section) 53. Of these, the 2-vote register 51 has two successive votes corresponding to the 4-bit address signals WKI and WK2. Also, data is written to the 2-vote register 51 via the ALU 53 output and the data bus. The selector 50 selects one of the data and the address signal WKI is used in the second half of one machine cycle. The read data from either read port of the 2-boat register (10) 51 is directly input to A, LU51 as the right input, but the left input is either the memory successive data from the memory data read register 40 or 44. , it is assumed that the successive data from the other read port of the 2nd port register 51 is selected by the selector 52. The ALU 51 performs predetermined calculations based on the left and right input data, and the results of the calculations are set in the memory address registers 43, 47 and the 2-board register 51.

Note that the operations in the arithmetic unit, address arithmetic section, etc. are defined by one word of the microprogram stored in the microprogram controller. Furthermore, only one of the data outputs from the arithmetic unit, register file, etc. to the signal bus is selected.

Now, the floating multiplier according to the present invention will be explained with reference to FIG. FIG. 5 specifically shows the configuration of the multiplier in FIG. 2, and according to (11), the entire multiplier consists of a sign operation section, an exponent operation section, and a mantissa operation section. First, before specifically explaining FIG. 5, the data formats of single-precision data and double-precision data will be explained using FIGS. 6(a) and (b). Figures 6(a) and Φ) show the formats of single-precision data and double-precision data, respectively. According to these, single-precision data consists of 32 bits as a whole and has a sign of 81 and an exponent E.
8. 1 bit, 8 bits, and 23 bits are assigned to the mantissa Fg, respectively, and the single-precision data represents the data shown in equation (1).

F! g-Bg Single precision data mi (-1,)'・2 ・1 piece Fs・
・(1) However, Bs is the bias of index E8, and
The value of S is 1" or 0", and when it is "1", it indicates that the single-precision data is negative data, and when it is 0", it indicates that it is positive data. There is.

Also, double-precision data is entirely a 64-bit code S.
1 bit, 11 bits, and 52 bits are assigned to 1 exponent ED and mantissa Fn, respectively, and the double precision data represents the data shown in equation (2) as in the case of single precision (12) data. .

BD-BD double precision data = (-1) 8・2 ・1. FD
...(2) However, BD indicates the bias portion of the index ED.

If we consider the aspect of data multiplication here, three cases can be considered. One of these cases is when two pieces of single-precision data are multiplied and the result is obtained as single-precision data. The second case is when the multiplication result of single-precision data is obtained as double-precision data, and the third case is when two double-precision data are multiplied and the result is made into double-precision data. In any multiplication mode, whether the multiplication result is negative data or positive data can be immediately known depending on whether the symbols S are in the same pit state or not. That is, if the codes S are in the same pit state, the multiplication result will indicate positive data, and if they are not in the same pit state, the multiplication result will indicate negative data.

The problem is the exponent and mantissa in the multiplication result. Here, assuming that the exponents of the two single-precision data are bound to E81 z Es and the multiplication result is obtained as single-precision (13) degree data, the exponent in the multiplication result is calculated and transformed as follows. It turns out.

(EsI Bs) + (E82-Bs) = Est + Esx -2Bs = (Esl+Esz Els) - Bs
-(3) That is, it is necessary to subtract Bs from the sum of E81 and E82. Similarly, when multiplying double precision data and obtaining the result as double precision data, it is necessary to subtract BD from the sum of the two exponents. The problem is when you multiply single-precision data and get the result as double-precision data. In this case, since equation (3) can be transformed into equation (4), it is sufficient to subtract (2Bs BD) from the sum of E81 and E82.

(BslBS)+(E112 Bs)=(Esl+E
s2-2BB+Bn) BD - (4) Therefore, in any case, the sign of the multiplication result can be immediately determined, and the exponent can also be determined as described above, but the problem is that the exponent (14) determined in this way is not necessarily This is not correct and needs to be corrected depending on the result of mantissa calculation.

For example, the mantissas of two single-precision data are each 1°F s
+, 1. When F82 is set, the multiplication result (((1
.

F's, )x(1,F'82))) is expressed in binary.
Less than 100", more than '1", and the multiplication result is 111
,......" or 10,...
...”, the mantissa in the multiplication result is
,...'', and at the same time, it is necessary to add '1' to the exponent that was calculated separately. Although the bias component B s r Bo is not directly related to the present invention, when the number of bits of the exponent is fixed, the range of data that can be expressed is expanded by the bias component B81 BD. It has become a thing.

Now, if the configuration of an example of the floating multiplier according to the present invention is explained with reference to FIG. 5, the configuration is generally in accordance with the above explanation. The two single-precision data or double-precision data to be multiplied are input to the floating multiplier 10 in units of 32 bits from the multiplier right input signal bus 14 and the multiplier left input signal bus 15, and are then multiplied. , the sign operation will be explained first as follows.

That is, since the sign S of the two single-precision data or double-precision data to be multiplied is shown as the bit state of the 0th bit position, as can be seen from FIG. 6(a), Φ), that bit state It is clear that this can be easily determined by comparing the values using the exclusive OR gate 111. The comparison result is stored in register 114 via registers 112 and 113. register 11
How the operation result of the code stored in 4 is processed will be described later.

Next, to explain the exponent calculation part, Fig. 6(a)
The bit states from the first bit position to the 11th bit position of the data format shown in (b) are taken into the exponent part input control circuits 101 and 102, arranged in a predetermined manner, and then stored in registers 103 and 104 with an 11-bit capacity.
The barley is set to be set. In this case, the exponent part input control circuits 101° (16) and 102 have the same configuration, and the specific configuration is shown in FIG. 7. According to this, the input data is single precision data or double precision data. Sequence control differs depending on the type. That is, when single-precision data is input, the output gate is controlled in a predetermined manner by a signal S (note that it is different from the one in FIG. 6) indicating that The bit state is 0” in the th bit position, and
From the th bit position to the 11th bit position #L, the bit states from the 1st bit position to the 8th bit position are input in a form shifted by 3 bits to the right, and then set. It is something. Furthermore, when double-precision data is input, the bit states from the 1st bit position to the 11th bit position @ are set as they are in the corresponding bit positions of the registers 103 and 104. This allows only the exponent to be extracted, regardless of whether the data is single or double precision, and the M
SB can be aligned. The exponents set in the registers 103 and 104 in this way are then added by the adder 105, but the bias amount for the exponents is subtracted by the adder 107 from this added value. The bias component referred to in this section is the already mentioned Bs = Bn or 2BsBo, and the selector 106
One of them is selected depending on the multiplication mode. The added value from which the bias has been subtracted in this manner is set in the register 109 via the register 108, and the subsequent steps will be described later as in the previous case.

Now, finally, to explain the mantissa calculation part, in this part, the mantissa F8°FD shown in Fig. 6(a), Φ)
is 1. Fs, 1. -The data is returned to the FD form, and the mantissas of the two single-precision data or double-precision data are multiplied. First, multiplier right turn signal bus 1
4 and multiplier input signal bus 15 in units of 32 bits, only the mantissa thereof is extracted by mantissa input control circuits 115 and 116. FIG. 8 shows the configuration of the mantissa input control circuits 115 and 116 (18). According to this, the signal S * I) L IDt
r is the upper 3 bits of double precision data when single precision data is input, the lower 32 bits of double precision data are input, respectively.
Only when 2 bits are input, the output gate is set to '1' and the output gate is controlled in a predetermined manner depending on each case.First, when single-precision data is input, the Oth bit is The bit states from the 7th bit position to the 7th bit position are all 0'', the bit state of the 8th bit position is '1', and the bit status from the 9th bit position to 31
The bit states up to the th bit position are set in registers 117 and 118 as they are. In this case, the bit state at the 8th bit position is set to 1'' because Fs alone does not serve as a mantissa, but by setting it to 1.Fs, it becomes meaningful as a mantissa. Similarly, when 32 bits of double-precision data are input, the bit state from the θth bit position to the 10th scan bit position is set to 1″0, and the bit state of the 11th (19th) bit IffM is 1'', the bit states from the 12th bit position to the 31st bit position are set as they are in registers 117 and 118, but when the lower 32 bits of double precision data are input, they are set as they are in registers 117 and 118. It is now possible to do so. The 32-bit data thus set in registers 117 and 118 are multiplied by multiplier 119, and FIG. 9 shows the circuit configuration thereof. According to this, the multiplier 119 is a 16-bit input 32-bit output multiplier [201 to 204], each of which multiplies the upper 16 bits of the input data, multiplies the lower 16 bits of the left input data and the upper 16 bits of the right input data, and multiplies the left input data by the upper 16 bits of the right input data. Upper 16 bits of data and lower 1 of right input data
Multiplication by 6 bits and multiplication by the lower 16 bits of the input data are performed, and these four results are set in registers 120, respectively. The result set in the register 120 is then added to the output of the selector 121 in an adder 122. The adder 122 (20) is made by five people, and the addition of the above four multiplication results is performed in a 64-bit width using the combination shown in FIG.
Bit width. The addition result from the adder 122 is set in the register 124, but if the data to be multiplied is single precision data, the addition result will be obtained as the final multiplication result. however,
32 if the data to be multiplied is double precision data
Since there are four combinations of multiplication of bit data, it takes three machine cycles more time than multiplication of single precision data. In the case of multiplication of double precision data, the lower 3
2-bit multiplication, multiplication of lower 32 bits and upper 32 bits,
Multiplying the upper 32 bits by the lower 32 bits and multiplying the upper 32 bits are performed sequentially, and the results of each multiplication are added by the adder 122. In order to obtain the final multiplication result, each addition result must be added in a predetermined manner. It is necessary to do so. A shifter 123 which receives the output of the register 124 as an input is provided for this purpose. In the case of single-precision data multiplication (21), the output of the selector 121 is of course "O", but
In the case of multiplication of double precision data, the output of the shifter 123 can be input to the adder 122 as a 1 addition input via the selector 121. shifter 123
outputs the output of the register 124 as it is, or shifts it 32 bits to the right and outputs it.

That is, when the lower 32 bits are first multiplied, the selector 121 output is set to g'0'' and the adder 122
Addition is performed at Next, when the lower 32 bits are multiplied by the upper 32 bits, the register 124 output is 3.
It is added to the output of the register 120 after being shifted to the right by 2 bits. The reason for shifting 32 bits to the right is for digit alignment. This nukijo 32
The bit is multiplied by the lower 32 bits, and in this case, the output of the selector 121 is the output of the register 124 itself. This is because the digits have already been aligned in the previous multiplication. Finally, multiplication of the upper 32 bits is performed, but in this case the output of register 124 is shifted to the right by 32 pits and added to the output of register 10 in order to perform digit alignment (22) again. The result of this addition is obtained as the final multiplication result of the mantissa in double precision data multiplication.

Now, the multiplication result of the mantissa is obtained as described above, and FIGS. 11(a) to 11(d) show the data format of the final multiplication result of the mantissa set in the register 124. Of these, Figures 11(a) and (b) relate to single-precision data multiplication, and Figure 11(C)
, (d) show those related to double-precision data multiplication.

As shown in the figure, it can be seen that in the case of single-precision data multiplication, 1'' appears for the first time at the 16th bit position or the 177th bit position.

Incidentally, since the data after the 188th bit position is the data below the decimal point, when @1'' appears at the 16th bit position as shown in Figure 11(a), the multiplication result is 1.
It is necessary to shift the bits to the right and at the same time add 1 to the result of the exponent calculation. Similarly, in the case of double-precision data multiplication (23), the data after the 24th bit position is the decimal point, so in a case like Figure 11(C), the same operation as above is performed. Is required. Selectors 125, 127 and adder 110 in FIG. 5 are provided for this operation.

The selector 125 selects the result of mantissa multiplication when the bit state at the 16th bit position is 1'' in single-precision data multiplication, and when the bit state at the 229th bit position is 1'' in double-precision data multiplication. It functions to shift one bit to the right. Also, the selector 127 selects the bit at the 16th bit position when performing single-precision data multiplication, and selects the bit at the 22nd bit position when performing double-precision data multiplication. The selected output bits are added to the exponent operation result from the register 109 in an adder 110.

This is how the index is corrected.

Therefore, the sign operation result from the register 114, the exponent operation result from the adder 110, and the mantissa operation result from the selector 125 are rearranged in a predetermined manner according to the current multiplication (24) mode and output. Then, a multiplication result corresponding to the multiplication mode can be obtained in a predetermined format.

FIG. 12 is a book showing the configuration of an output control circuit 126 for obtaining multiplication results in a format according to the multiplication mode. According to this, the signal S (Fig. 6).

(Note that it is different from those in Figures 7 and 8)
, S'I'D, and D are '1' only when it is normal single-precision data multiplication, when the multiplication result of single-precision data is obtained as double-precision data, and when it is normal double-precision data multiplication, respectively.
Further, only when the signal OE is at 1'', output of the multiplication result to the outside of the multiplier 10 is allowed.

First, when S is 1'', the signal, the 1-bit sign operation result from lj!128, is output as the 0th bit position bit through the output gate. Part 4 of the 11-bit exponent calculation result of
The bits from the 1st bit position to the 11th bit position are output as the bits from the 1st bit position to the 8th bit position.

(25) Furthermore, the bits from the 181st bit position to the 40th bit position of the mantissa operation result from the signal line 130 are output as bits from the 9th bit position to the 31'4th bit position, and the remaining 32nd All bits from the bit position to the 63rd bit position # are output as 0". Also, if STD is 1", the signal line 128
The sign operation result from 1i! is output as the bit at the 0th bit position as in the previous case, and the signal 1i! The bits from the 1st bit position to the 11th pit position of the exponent operation result from 129 are output as the bits from the 1st bit position to the 11th bit position.

The bits from the 188th bit position to the 699th bit position of the mantissa operation result from the signal line 130 are output as the bits from the 12th bit position to the 63rd bit position. Furthermore, D is '1''
In this case, the second part of the mantissa operation result from the signal line 130
STD is 1 except that the bits from the 4th bit position to the 75th bit position are output as the bits from the 12th bit position to the 63rd bit position (26).
This is the same as in the case of .

FIG. 13 shows the processing steps when the STD is 11'' as 1 step/machine cycle, but as can be seen from this figure, the result is obtained in 4 machine cycles after the calculation data is input. Conventionally, there was no function to output the multiplication result of single-precision data as double-precision data, so it was necessary to convert the single-precision data to double-precision data before multiplying the double-precision data.
In this case, for example, it takes as much as 13 machine cycles to obtain the desired result.

Adder (1
In case 1), it takes 6 machine cycles to convert two single-precision data to double-precision data, and further 7 machine cycles to multiply the double-precision data. However, in the case of the present invention, the result can be obtained in 4 machine cycles, so the speed can actually be increased by more than three times.

For example, when performing an inner product operation on single-precision data, for example, data is simultaneously supplied to the multiplier 10 from the multiplier input signal buses 14 and 15 one by one per machine cycle in FIG. By performing single-precision data multiplication, obtaining the result as double-precision data, and repeating double-precision addition with data from signal lines 19 and 20 via signal lines 21 and 22 in adder 11, inner product operation can be performed. This makes it possible to perform the following without reducing accuracy.

〔Effect of the invention〕

As explained above, in the present invention, the addition result of the exponent part in single-precision data is corrected according to the multiplication result of the mantissa part, and the corrected exponent part addition result, sign operation result, and mantissa part multiplication result are It can be output as a double-precision data format. Therefore, according to the present invention, even if the number of bits of the exponent part of single-precision data is different from that of the exponent part of double-precision data, the multiplication result of single-precision data can be quickly obtained in the double-precision data format,
This has the effect (28) that even when operations on single-precision data and double-precision data are mixed, operations can be executed at high speed.

[Brief explanation of drawings]

FIG. 1 shows the overall configuration of the processor according to the present invention, and FIGS. 2, 3, and 4 show the configurations of the arithmetic unit, register file, memory section, and address arithmetic section in that configuration, respectively. FIG. 5 is a diagram showing the configuration of the floating multiplier according to the present invention as a pipeline configuration, FIG. 6(a). (b) is a diagram showing the format of single-precision data and double-precision data, respectively; FIGS. 7 and 8 are diagrams showing the configurations of the exponent input control circuit and the mantissa input control circuit, respectively, in FIG. 5; FIG. 9 is a diagram showing the configuration of the multiplier in FIG. 5, FIG. 10 is a diagram for explaining the addition operation in the adder, and FIG. The data format of the exponent multiplication result in
Figure 11 (C). (d) is a diagram showing the data format of the multiplication result of the exponent in double-precision data, FIG. 12 is a diagram showing the configuration of the output control circuit in FIG. 5, and FIG. 29) is a diagram showing the flow of processing when outputting as double precision data. 101.102...Exponent input control circuit, 103゜1
04.108,109.112-114,117゜11
8.120,124...Register, 105°107.
110.122...Adder, 106,125°127
...Selector, 111...Exclusive OR gate, 1
15.116... Mantissa input control circuit, 119...
Multiplier, 126...output control circuit. Agent Patent Attorney Masami Akimoto (30) Moq (2) Plan I1

Claims (1)

[Claims] 1. Multiplication is performed between two pieces of the same precision data based on single precision data and double precision data with different bit lengths of the exponent part, and the single precision data multiplication result is converted into single precision data format or double precision data. The data format is a floating multiplier that obtains the double-precision data multiplication result as a double-precision data format, and a circuit that compares the signs of two same-precision data and only the exponent part of each of the above-mentioned same-precision data are selected in a predetermined state. a circuit that selects only the mantissa part in each of the same precision data, a circuit that adds the selected exponent parts, a circuit that multiplies the selected mantissa parts, and a circuit that selects only the mantissa part in each of the same precision data, a circuit that multiplies the selected mantissa parts, and a circuit that calculates the result of adding the exponent part by the mantissa multiplication result. 1. A 70-ting multiplier comprising a circuit for correcting and a circuit for controlling output of a sign comparison result, a corrected exponent addition result, and a mantissa multiplication result in the form of single precision data or double precision data. 2. The floating multiplier according to claim 1, wherein a register for holding the results of comparison, selection, addition, and multipliers is provided at the final stage of each stage to form a vibe line configuration. 3. The claim that the circuit for adding the exponent part consists of a circuit for adding only the exponent part, and a circuit for adding the addition result from the circuit and a bias value selected according to the multiplication result output format. 70-Ting multiplier according to item 1 or 2.