JPS61289422A - Shift control system - Google Patents

Abstract

PURPOSE:To use shift data for the correcting operation of an exponential part as they are after shift control for normalization by adjusting the display format of the number of bits to be shifted for shift control of normalization or digit adjustment to the least significant bit (LSB) of the exponential part of floating point data to be operated. CONSTITUTION:The titled system is constituted so that the least significant bit (LSB) of a counting area 21 in a shift counting register 2 is adjusted to the LSB of an exponential part in each accuracy using accuracy information stored in a microinstruction shifting mode. The display format of the number of bits to be shifted for the shift control of normalization or digit adjustment is adjusted to the LSB of the exponential part in accordance with the accuracy of floating point data to be operated. After shift control for normalization, the shift data can be used for the correctory operation of the exponential part as they are. At the time of shift control for digit adjustment, difference data obtained by comparing the exponential parts can be written in the shift counting register as the specified number of digits to be shifted for digit adjustment.

Description

[Detailed Description of the Invention] [Summary] In a floating point arithmetic unit controlled by a microprogram, the display format of the shift amount for performing shift control for normalization or digit alignment is changed to the floating point number of the operation target. Depending on the accuracy of the data, it is adjusted to the lowest bin (LSB) of the exponent part.

[Industrial application field]

The present invention provides a shift control method in a floating point arithmetic unit controlled by a microprogram. With the recent remarkable development of microprocessor technology, floating point arithmetic is now required even in small computer systems at the personal computer level. A floating point arithmetic unit is connected to a system bus, and a central processing unit (CPU) accesses the floating point arithmetic unit through the system bus to perform floating point arithmetic operations.

In the above floating point operation, for example, the mantissa part.

Digit alignment when performing addition/subtraction between two floating point data consisting of an exponent part and a sign part.

Addition and normalization of the mantissa part are performed.

To do this, first, we need two operands (source).

The exponent parts of destinations) are compared, and the difference is stored in advance in a shift count register as a shift amount.

Thereafter, when the shift microinstruction is executed, the mantissa part of the floating point data with the smaller exponent part, which is set in the shifter in advance, is shifted to the right, and the mantissa part is stored in the shift count register. The set shift amount is counted down, and when the shift amount reaches all "0",
When the shift is completed, another microinstruction adds the shift amount to the exponent part.

In the above digit alignment operation, when the exponent parts match, the mantissa parts are added algebraically and an intermediate sum is output. If there is an invalid bit (ie, a 0° bit) in the upper bits of this intermediate sum, it is necessary to perform a left shift for normalization.

In this case, a microinstruction for performing the left shift is prepared, and each time a 1-bit shift is performed, the shift count register is counted up until there are no more invalid bits.

Thereafter, the exponent part is subtracted by the shift amount.

In this way, digit alignment in floating point arithmetic.

Shift control for normalization requires a shift count register that counts down during digit alignment and counts up during normalization.

However, in general, the data length and format of the floating point data differ depending on its precision, for example, single precision, 9 double precision, etc., and as a result, the shift amount also differs. In order to perform shift control, it is necessary to prepare a shift count register corresponding to the accuracy.

Conventionally, as a shift count register for this purpose, a shift count register that can be applied to double precision with a large shift amount (for example, 64 bits) is provided, and the same register is used when calculating single precision floating point data. It was being used.

Therefore, for floating point data with different precision in a shift count register that has only one display format,
When attempting to perform the shift operation for the above digit alignment and normalization processing, the count area of the shift count register is
It is necessary to process the floating-point data according to the exponent part of the calculation target, and an effective shift control method for handling floating-point data with different precision has been awaited.

[Conventional technology]

FIG. 3 is a diagram schematically showing the main part of shift control in a floating point arithmetic unit provided in a small computer system, and shows shift mode 11 of microinstruction 1. Depending on the shift content indicated by the shift amount 12, the mantissa part of the floating point data set in advance in the shifter 3 is shifted, and the shift count register 2 counts up (+
1), or countdown (-1).

At this time, depending on the contents of shift mode 11 of microinstruction 1, whether the shift is for ``digit alignment'' or ``normalization'' is determined.
The distinction between whether the shift is for be done.

Note that the shift amount specified by the shift amount 12 of the microinstruction 1 is used, for example, in the case of a logical shift.

FIG. 4 is a diagram schematically showing an example of the above shift operation, where (a) shows the shift operation during normalization, and (b) shows the shift operation other than normalization, for example, during digit alignment. It shows.

(a) Shift operation during normalization: Assuming that the contents of shift mode 11 of microinstruction l instructs a shift operation during normalization and specifies floating-point data precision or double precision, then , shift amount 12
Since the contents of are all 0's, the count area 21 of the shift count register 2 is set to all 0's.

In this state, every time the upper invalid bit of the aforementioned intermediate result data set in shifter 3 is shifted to the left,
The +1 counter operates to count up the normalized shift amount, and when the invalid bit disappears, the shift operation ends.

At this time, the value counted up in the count area 21 of the shift count register 2 is the normalized shift amount,
By subtracting this value from the value of the exponent part of the normalized floating-point data, the exponent part at the time of normalization can be obtained.

(b) Shift operation during digit alignment: The contents of shift mode 11 of microinstruction 1 specify a shift operation for digit alignment and precision or double precision of floating point data, and the contents of shift amount 12 are invalid. At this time, the contents of the shift amount 12 are ignored and the count area 2 of the shift count register 2 is specified in advance.
The specified shift amount set to 1 is used for the digit alignment shift.

In this state, each time the mantissa part of the floating point data to be aligned is shifted to the right, the -1 counter operates and the count area 21 of the shift count register 2 is shifted to the right. When the designated shift amount reaches 0°, the shift operation ends.

In the operations (a) and (b) above, the count area 21 in the shift count register 2 is the same even if the floating point data is single precision.

[Problem that the invention seeks to solve]

Therefore, in the conventional method, when calculating with the exponent part of the floating point data, depending on the contents of the count area 21 of the shift count register 20, the count area 21
has a single display format (i.e., in the above example, it is compatible with double-precision floating-point operations), so for example, when the floating-point data is single-precision, the single-precision floating-point In order to match the exponent part of the data, the contents of the count area 21 of the shift count register 2 had to be processed, for example, shifted to the left.

In view of the above-mentioned drawbacks of the conventional art, the present invention provides a shift count register with a count amount display format based on the precision of floating point data (for example, the lowest bin of the count area 21).
The purpose of this invention is to provide a method for providing a function to change (LSB).

[Means for solving problems]

FIG. 1 is a principle block diagram of the display format of the shift count register of the present invention.

In this figure, (a) shows the case of single precision, and (b) shows the case of double precision.

In this way, in the present invention, for example, the accuracy information built in the shift mode 11 of the microinstruction 1 is used to calculate the count value of the shift count register 2. fJf area 2
The least significant bit (LSD) of 1 is configured to match the least significant bit (LSB) of the exponent part of each precision.

[Effect]

That is, according to the present invention, in a floating point arithmetic unit controlled by a microprogram, the display format of the shift amount for performing shift control for normalization or digit alignment is changed to the display format of the floating point data to be operated on. Depending on the accuracy,
Since it is designed to match the least significant bit (LSB) of the exponent part, after the shift control for normalization, the shift data can be used for the correction calculation of the exponent part.
When performing shift control for digit alignment, the difference data obtained by comparing the exponent parts can be written into the shift count register as the specified shift amount for digit alignment.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram schematically showing an embodiment of the present invention, in which the same symbols as in FIGS. 3 and 4 indicate the same objects, and depending on the precision of floating point data, the shift count register The lowest bin I-(LSB
) is a necessary function to implement the present invention.

In Figure 2, (a) shows the case of single precision, and (b)
indicates the case of double precision.

+l) In the case of a shift operation for digit alignment: First, by executing a microinstruction (not shown), 2
The exponent parts 4 of the two operands (source, destination) are compared, and the difference is used as the shift amount in the count area (shift amount) 21 of the shift count register 2.
The number is placed in .

At this time, the precision of floating point data ((a), (b)
), the lowest order of the exponent part 4 (LSB
) Although the location is different, in the present invention, the result of the operation is placed in the shift count register 2.

As a result, the count area (shift amount) 21 matches the least significant bit (LSB) of the exponent part 4 of the floating point data, as shown.

After that, the aforementioned shift microinstruction 1 is executed, but by instructing to invalidate the contents of the shift amount 12 in the shift mode 11 of the shift instruction 1, the contents of the shift amount 12 can be changed. , is never set in the count area (shift amount) 21 of the shift count register 2.

When such a shift instruction 1 is executed, each time the mantissa part of the floating point data having the smaller exponent part, which is set in advance in the shifter 3, is shifted to the right, the shift count register 2 The shift amount 21 set in is counted down (-1), and the shift operation is continued until the value of the shift amount 21 becomes all "O".

During this shift operation, the count area (shift amount) 21 of the shift count register 2 is set to (a) according to the accuracy information set in the shift mode 11 of the microinstruction l.
, are selected as shown in (b).

(2) In the case of normalized shift operation: In this case, the microinstruction 1 for performing the left shift described above is prepared, and by executing the shift instruction 1,
After the value of the shift amount 12 of the shift instruction 1, all 0, is placed in the count area (shift amount) 21 of the shift count register 2, the count area ( Shift amount) Continue counting up (+1) 21 until there are no invalid bits.

During this shift operation, the count area (shift amount > 21) of the shift count register 2 is determined by the precision information set in the shift mode 11 of the microinstruction 1 (
A) and (b) are selected.

In other words, it functions so that the least significant bit of the 21 area of the 81 area is selected in accordance with the least significant bit (LSB) of the exponent part 4 of the floating point data, depending on the single precision and 9 double precision. .

Therefore, in the subsequent exponent correction calculation in which the exponent part 4 is subtracted by the shift amount 21, the count area (shift amount) 2
The exponent correction calculation can be performed by simply adding the value of 1 and the exponent part 4 of the floating point data.

As described above, in the present invention, the count area (shift amount) 21 of the shift count register 2 is made to match the expression format of the exponent part 4 in accordance with the precision of the floating point data, and exponent correction calculations, etc. The feature is that there is no need to perform special shift processing when

〔Effect of the invention〕

As explained above in detail, the shift control method of the present invention provides a display format for the shift amount for performing shift control for normalization or digit alignment in a floating point arithmetic unit controlled by a microprogram. , is set to match the least significant bit (LSB) of the exponent part of the floating point data to be calculated, so after the shift control for normalization, the shift data is used for the correction calculation of the exponent part. When performing shift control for digit alignment, the difference data obtained by comparing the exponent parts can be written to the shift count register as the specified shift amount for digit alignment. There is.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the display format of the shift count register of the present invention. FIG. 2 is a diagram schematically showing an embodiment of the present invention. FIG. 3 is a diagram schematically showing the main parts of shift control in a floating-point arithmetic unit. FIG. 4 is a diagram schematically showing an example of a conventional shift operation. It is. In the drawing, 1 is a microinstruction and 11 is a shift mode. 12 is the shift amount. 2 is a shift count register. 21 is a count area (shift amount). 3 is shifter. 4 is the exponent part of floating point data. are shown respectively. A (January's shift sword Tsun F register λ) to the straight form 'Lilyfu' Dy7EJ 茅 1 brutal) 1 2 eyes

Claims (1)

[Claims] In a floating point arithmetic unit controlled by a microprogram, the display format (21) of the shift amount for controlling the shift of the floating point operand is determined by the precision of the floating point data. A shift control method characterized by providing means for adjusting to the least significant bit (LSB).