JP3124286B2 - Floating point arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an arithmetic unit for performing addition / subtraction processing on floating-point numerical data.

(Prior Art) In a signed absolute value expression, a floating-point value is represented by a sign of an exponent, a mantissa, and a mantissa. For example
The double precision number D (64 bits) of the IEEE754 standard is expressed as follows.

D = (-1) ^S × 1.f × 2 ^e-1023 s: 0or1 (1 bit) f: 000 ... 00 to 111 ... 11 (52 bits) e: 0 to 2047 (11 bits) where S is the mantissa part The sign is 0 when D is positive and 1 when D is negative. f is the fractional part of the mantissa. The integer part is a hidden bit, and the mantissa part f is only 52 bits below the decimal point. The decimal point is to the left of the MSB of f. The mantissa part is normalized so that the integer part becomes 1. e is an exponent part, which is expressed in a clogging expression obtained by adding 1023 as a bias value to an original exponent.

Conventionally, in a data processing device that handles floating-point values represented in such a format, addition and subtraction have been performed in the following procedure.

Phase 1 Digit alignment: Compare the sizes of the exponents and adjust the digits of the mantissa so that the smaller exponent is the same as the larger exponent.

Phase 2 operation: Addition and subtraction of the mantissa are performed.

Phase 3 Normalization: The mantissa is shifted left so that the integer of the mantissa becomes 1. The exponent is corrected with the shift.

Phase 4 Rounding: Rounding is performed according to the rounding mode and the sign of the solution.

Phase 5 Renormalization: If a carry occurs due to rounding, renormalization is performed.

FIG. 6 is a block diagram of a mantissa operation circuit in general. In FIG. 6, in phase 1, the magnitudes of the exponents are compared, and the mantissa is shifted right so that the smaller exponent is the same as the larger exponent.

Phase 2 actually performs the operation. Here, the true subtraction of the mantissa is performed as follows.

Since the mantissa is represented by the absolute value expression, the mantissa of the reduced number is first complemented and added to the non-decimal number. Here, when the operation result becomes a negative number, it is necessary to perform complementation again in order to represent an absolute value. The complementing process is specifically performed by inverting every bit and incrementing it. Complementation processing before the operation can be omitted by inverting the number of bit inversions and setting the carry input of the adder to 1. However, when the solution becomes a negative number, the normalization process after the operation cannot be omitted. In such subtraction, carry propagation of the mantissa occurs at worst twice in the adder and the complement circuit, and the subtraction process requires a very long time.

In the normalization process of the phase 3, the leading encoder detects a leading "1" from the operation result of the phase 2 using the priority encoder, and shifts to the left so that the integer part of the mantissa becomes "1".
Both the priority encoding process and the shift process require a very long execution time.

In the rounding process of phase 4, when the solution cannot be accurately represented because the mantissa has only finite digits, the value of the exact solution obtained assuming that the mantissa has infinite digits is incremented to the least significant digit of the finite mantissa. Is performed, or the digits below the least significant digit are truncated, and the solution is represented by finite bits. When the increment is performed by the rounding circuit, carry propagation occurs, and the rounding process requires much time.

Such a general procedure can reduce the phase of carry propagation to two places.

FIG. 7 is a block diagram of the mantissa operation circuit. The arithmetic circuit shown in FIG. 7 is configured noting that the operation result becomes negative only in the case of true subtraction.

First, there is a case where the exponents of the two operands are different in size. In such a case, if the smaller exponent is always a true subtraction, the operation result is always a positive number. There is no need for recomplementation.

Next, in the case where the exponents are the same, in this case, comparison of only the exponents does not reveal the magnitude relation of the operands. Therefore, the operation result may be negative, and recomplementation is necessary. However, since the digit alignment before the operation is not performed, the increment by the rounding never occurs. That is, since the increment by the rounding and the increment by the recomplementation do not occur at the same time, the incrementer is shared by the two processes. can do. As described above, the arithmetic circuit shown in FIG. 7 can reduce the number of phases in which carry propagation occurs to two.

(Problems to be Solved by the Invention) As described above, in the conventional addition and subtraction procedure, each phase of the operation is sequentially processed, which is an obstacle to speeding up the operation processing. In particular, in the field of scientific computing,
There is a demand for higher-precision and higher-speed calculations, and the number of bits in the mantissa tends to increase. Therefore, there is a demand for speeding up the arithmetic processing by executing each processing in parallel.

Therefore, the present invention has been made in view of the above, and an object thereof is to provide a part of a phase of an arithmetic procedure, specifically, a rounding process and a normalization process that require a very long execution time. And a floating-point arithmetic device capable of achieving high-speed addition and subtraction processing.

[Structure of the Invention] (Means for Solving the Problem) To achieve the above object, a first means for solving the problem is a first means for comparing the magnitudes of exponent parts in both operand values.
A comparison means, a second comparison means for comparing the magnitudes of absolute values of both operand values, and a value of an exponent part in both operand values based on a comparison result of the first comparison means. A digit exponent part having a smaller exponent part in both operand values is digit-aligned with a mantissa part having a larger exponent part, and this digit alignment is performed in parallel with the comparison operation of the second comparing means; Inverting means for bit-inverting, based on the comparison result of the second comparing means, only the value of the mantissa part having the smaller absolute value among the mantissa parts of both operand values having the same exponent value, the value of the exponent part Among the mantissa parts in both operand values that match, the mantissa part having a large absolute value and the mantissa part having a small absolute value bit-inverted by the inversion means are added or subtracted, and the subtraction is performed. In the case of, subtract the small mantissa from the large mantissa It characterized by having a calculating means for obtaining a calculation result of positive number.

A second means for performing, in the first means, a first normalization process on the operation result of the operation means to obtain a first solution; and a second normalization means for obtaining a first solution. A normalization process and a rounding process are performed in parallel with the normalization unit to obtain a second solution, a normalization rounding process unit, and a first solution obtained by the normalization unit and a normalization rounding process obtained by the normalization rounding unit. Solution selecting means for obtaining a true solution by selecting any one of the second solutions to be obtained.

The third means is the second means, wherein the solution selecting means selects the first solution when a shift of two or more bits is required for the operation result obtained by the operation means, Otherwise, the second solution is selected.

(Operation) In the above configuration, in the case of subtraction, the subtraction result is obtained as a positive number, and the complementing process when the subtraction result is negative is omitted.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing one embodiment of the present invention. In the operation of the floating-point value, the exponent part, the mantissa part, and the sign of the mantissa part can be independently calculated, and FIG. 1 shows a part of the mantissa part arithmetic unit and the exponent part arithmetic unit. This embodiment complies with the IEEE754 standard.

Before describing the configuration of the arithmetic unit, the format of the operand value input to the present unit will be described with reference to FIG.
Although the IEEE754 standard defines a plurality of types of data formats depending on the precision, here, only double precision data will be described for simplicity. The configuration of the present invention can be applied to other formats without any change.

FIG. 2A is a diagram showing a double precision data format in the IEEE754 standard. In FIG. 2A, the operand value is composed of a sign bit of the mantissa, 11 bits of the exponent, and 52 bits of the mantissa. FIG. 2 (b) is a diagram showing the intermediate value format (57 bits) of the mantissa. Second
In FIG. 7B, the most significant bit (MSB, bit 57) is an overflow bit V, the 56th bit is a hidden bit N of an integer part, and the 55th to 4th bits are significant digits. In the mantissa part, a card bit G and a guard bit G each representing a value one bit lower than the least significant digit (fourth bit)
, A rounded bit R representing a value one bit lower than and a sticky bit St representing a value of a logical sum of all bits lower than the rounded bit R are extended.

Next, the configuration of the mantissa arithmetic unit will be described with reference to FIG. In FIG. 1, an exponent part comparison circuit 1 receives an exponent part of a first operand as one operand value and an exponent part of a second operand as another operand value, and
The exponent part E2 of the second operand is subtracted from the exponent part E1 of the operand. The exponent comparison circuit 1 calculates, in the subtraction result, an exponent comparison signal in which the exponent E1 ≦ the exponent E2 becomes “1” and the exponent E1> the exponent E2 becomes “0”, and the difference between the two exponents. The difference signal shown is output.

The mantissa exchange circuit 2 receives the mantissa F1 of the first operand and the mantissa F2 of the second operand, and converts the mantissa having a smaller exponent into a digit matching circuit 3 according to an exponent comparison signal given from the exponent comparator 1. And a mantissa part having a large exponent is provided to the inversion circuit 5a. If the exponents are the same, the mantissas are not exchanged, and the mantissas F1 and F2 pass through the mantissa exchange circuit 2.

The digit matching circuit 3 shifts the mantissa provided from the mantissa exchange circuit 2 to the lower side (right side) by the difference of the exponent part indicated by the difference signal provided from the exponent comparison circuit 1,
The mantissa with a small exponent is digit-aligned with the mantissa with a large exponent so that the exponent E1 and the exponent E2 are the same. At the time of this shift, "0" is shifted into the overflow bit V, and the logical sum of the current St and the rounding bit R is shifted into the sticky bit St. The digit matching circuit 3 provides the mantissa part with the digit alignment to the inverting circuit 5b.

The comparison circuit 4 has 63 bits obtained by bit-combining the exponent part and the mantissa part of the first operand and the second operand, that is,
This is a circuit for comparing the magnitudes of E1 · F1 and E2 · F2 (where “·” represents bit combination). In the comparison result, when E1 · F1 ≧ E2 · F2, the operand comparison signal 4a is “0”, the signal 4b is “1”, and when E1 · F1 <E2 · F2, the operand comparison signal 4a is “1”. , The signal 4b becomes "0". Operand comparison signal 4a and signal 4b are applied to inversion circuits 5a and 5b, respectively.

The inversion rotations 5a and 5b are circuits for bit inversion of the mantissa. The inversion circuit 5a has an exponent comparison signal from the exponent part comparison circuit 1, an operand comparison circuit 4a from the comparison circuit 4, and an operation signal ("1" when performing true subtraction of the mantissa, and when performing true addition. “0”). Also, inverting circuit
5b is supplied with an exponent comparison signal from the exponent comparison circuit 1, an operand comparison signal 4b from the comparison circuit 4, and an operation signal. When subtraction is performed using these signals,
Either of the mantissas is bit-inverted as shown in FIG.

In this embodiment, the above operation is performed using the exponent comparison circuit 1, the mantissa exchange circuit 2, the comparison circuit 4, and the inversion circuits 5a and 5b, so that the smaller mantissa is always subtracted from the larger one. In any case, the difference between the mantissa parts can be quickly obtained in an absolute value.

The adder 6 is provided with mantissa parts from the inversion circuits 5a and 5b and adds these mantissa parts. At this time, the operation signal is provided as a carry input of the adder 6. That is, when performing the subtraction, “1” is further added. Thus, the subtraction result (difference) is always obtained as an absolute value.

The priority encoder 7 receives the operation result from the adder 6, detects the leading "1", and supplies a shift step signal indicating the number of shifts for normalizing the operation result to the normalization circuit 8.

The normalization circuit 8 outputs a calculation result obtained by normalizing the shift number given by the priority encoder 7 by shifting the calculation result to the left by the value of the signal.

The bidirectional one-bit shifter 9 receives the operation result from the adder 6 and performs a normalization shift of only one bit. That is, when the V bit of the operation result is “1”, the bit is shifted to the right by one bit. When the V bit is “0” and the N bit is “1”, no shift is performed, and the V bit is set to “0”. If the N bit is “0” and the MSB of the fraction part of the mantissa is “1”, 1
Outputs the bit-shifted normalized result.

The incrementer 10 receives the normalization result from the bidirectional 1-bit shifter 9 and converts the normalization result into a rounding decision circuit 11.
It outputs an incremented value or a value as it is depending on the value of the rounding determination signal given from the controller.

The rounding determination circuit 11 is provided with a rounding mode signal, a sign of a final solution, and an operation result, and determines whether or not to perform incrementing by rounding based on these values. Rounding circuit 11
Gives a rounding determination signal to the incrementer 10 which becomes "1" when incrementing and "0" when not incrementing. The types of rounding modes are as shown in FIG. 4, and the specific logic of the rounding determination is as shown in FIG. In the logic of the rounding determination, the bits of the calculation result referred to for the rounding determination differ depending on the value of the calculation result. That is, in FIG. 5, when the V bit of the operation result is “1”, L is the fifth bit from the LSB, M is the fourth bit, and S is the fourth bit.
Is the logical sum from the third bit to the LSB. When the V bit is “0” and the N bit is “1”, L is the fourth bit from the LSB, M is the third bit, and S is the logical sum of the second bit and the LSB. When the V bit is “0”, the N bit is “0”, and the MSB of the fraction part of the mantissa is “1”, L corresponds to the third bit from the LSB, M corresponds to the second bit, and S corresponds to the LSB.

The solution selecting circuit 12 selects a true solution from the output of the normalizing circuit 8 or the output of the incrementer 10.

As described above, one embodiment of the present invention is configured, and the rounding processing and the normalization processing are executed in parallel.
This means that "the normalization process and the rounding process for shifting by 2 bits or more in the upper direction (left side) need not be both necessary."
It is based on that. The above is described in detail below.

First, a case where true addition of the mantissa is performed. In this case, even when normalization is required, the shift amount is 1 at most.
Bit shift right. That is, a normalized shift of 2 bits or more is not required. However, rounding may be required.

Next, the true subtraction of the mantissa is performed. In this case, the difference between the exponent of the minuend and the exponent is “1”, and the borrow from the lower end reaches the most significant digit (the 55th bit). Only in the case of propagation, normalization requiring a shift of 2 bits or more is required. In other cases, normalization is not required, or even when normalization is required, the shift amount is at most one bit left shift. Therefore, when the data is normalized-shifted by two or more bits to the left, the G bit, the R bit, and the S bit all become "0", so that the rounding process is not substantially performed. From the above, the normalization process and the rounding process that require a shift of 2 bits or more can be performed independently.

 Next, the operation of this embodiment will be described.

 First, the true addition processing will be described.

Exponent part E1 of first operand and exponent part of second operand
When E2 is supplied to the exponent part comparison circuit 1, the magnitudes of both exponent parts are compared, and the difference between the magnitudes is calculated as a difference signal. The comparison result is supplied to the mantissa switching circuit 2 as an exponent comparison signal.

When the exponent comparison signal is provided to the mantissa exchange circuit 2, the mantissa having a large exponent is provided to the inversion circuit 5a by the exponent comparison signal, and the mantissa having a small exponent among the mantissas of each of the first and second operands. The mantissa is provided to the digit matching circuit 3. However, if the exponents are the same size, each mantissa simply passes through this circuit. Ie mantissa
F1 is provided to the inverting circuit 5a, and the mantissa F2 is provided to the inverting circuit 5b. The mantissa provided to the digit matching circuit 3 is subjected to digit matching according to the difference signal provided from the exponent comparison circuit 1 so as to unify the exponents of both mantissas into the larger mantissa.

The digit-matched mantissa is applied to an inversion circuit 5b. In the case of performing true addition, the mantissas given to the inverting circuits 5a and 5b are given to the adder 6 without being inverted. The two mantissa parts provided to the adder 6 are added, and the operation result is input to a priority encoder 7, a normalization circuit 8, a bidirectional 1-bit shifter 9, and a rounding judgment circuit 11.

When the calculation result is given to the priority encoder 7, the leading "1" is detected, and the number of shifts required for normalization is calculated as a shift step signal.

The normalization circuit 8 normalizes the operation result according to the shift step signal and outputs the normalized result.
However, when true addition is performed, the operation result does not become smaller than 1, so that this circuit does not operate.

On the other hand, the operation result given to the bidirectional 1-bit shifter 9 is not shifted or shifted to the right by one bit depending on the values of the overflow bit V and the hidden bit N. That is, when the V bit is “1”, it is shifted to the right by one bit, and when the V bit is “0” and the N bit is “1”, it is not shifted and is supplied to the incrementer 10. Further, when the calculation result is given to the rounding determination circuit 11, it is determined whether or not to perform the increment based on the logic as shown in FIG. 5 by the calculation signal and the rounding mode signal, and the rounding determination signal is sent to the incrementer 10. give.

The incrementer 10 performs a rounding process on the mantissa part shifted by the rounding determination signal, and outputs a rounding result.

The solution selection circuit 12 selects a true solution from the normalized result and the rounded result. When a true addition is performed, the result of the operation is always 1 or more, and a normalization shift of 2 bits or more is not performed. Therefore, a rounded result is selected as a true solution.

 Next, the true subtraction processing will be described.

When the exponent part E1 of the first operand and the second operand E2 are given to the exponent part comparing circuit 1, the magnitudes of both exponent parts are compared as in the case of true addition, and the difference between the magnitudes is different. It is calculated as a signal. The comparison result is supplied to the mantissa switching circuit 2 as an exponent comparison signal.

When the exponent comparison signal is provided to the mantissa exchange circuit 2, the mantissa having a larger exponent is provided to the inverting circuit 5a by the exponent comparison signal, of the mantissa of each of the first and second operands. The small mantissa is provided to the digit matching circuit 3. However, if the exponents are the same size, each mantissa simply passes through this circuit.

The mantissa supplied to the digit matching circuit 3 is subjected to digit matching in accordance with the difference signal provided from the exponent comparison circuit 1 so as to unify the exponents of both mantissas into the larger mantissa.
The digit-matched mantissa is applied to the inverting circuit 5b.

On the other hand, when the exponent part of the first operand, the mantissa part and the exponent part of the second operand and the mantissa part are given to the comparison circuit 4, both operands are compared in magnitude, and the result is inverted as operand comparison circuits 4a and 4b. It is provided to circuits 5a and 5b.

The mantissas given to the inverting circuits 5a and 5b include an operation signal, an exponent comparison signal, and an operand comparison signal as shown in FIG.
According to 4a and 4b, only the mantissa having the smaller absolute value is bit-inverted.

The mantissa parts given to the adder 6 from the respective inversion circuits 5a and 5b are added. At this time, "1" is given to the carry input to the adder 6. By the above operation, the mantissa part having a small absolute value is subtracted from the mantissa part having a large absolute value, and the difference can be obtained by the absolute value. The operation result is input to a priority encoder 7, a normalization circuit 8, a bidirectional 1-bit shifter 9, and a rounding judgment circuit 11.

When the calculation result is given to the priority encoder 7, the leading "1" is detected, and the number of shifts required for normalization is calculated as a shift step signal. The normalization circuit 8 normalizes the operation result according to the shift step signal and outputs the normalized result.

On the other hand, the operation result given to the bidirectional 1-bit shifter 9 is shifted left by 1 bit or not shifted by the value of the overflow bit V, the hidden bit N, and the MSB of the fraction part in the mantissa. That is, the V bit is “0” and the hidden bit N
Is "0" and the MSB of the fraction part of the mantissa is "1".
If the V bit is “0” and the N bit is “1”, the bit is not shifted and is supplied to the incrementer 10.

Further, when the calculation result is provided to the rounding determination circuit 11, it is determined whether or not to perform the increment according to the rounding mode signal, and the rounding determination signal is provided to the increment 10. The incrementer 10 outputs a rounded result obtained by performing a rounding process on the mantissa part shifted by the rounding determination signal.

The solution selecting circuit 12 selects a true solution from the normalized result or the rounded result. That is, when the V bit is “0”, the hidden bit N is “0”, and the MSB of the fraction part of the mantissa is “0”, the normalization result is selected as a true solution. Is selected as the solution of.

In the present embodiment, the exponent comparison circuit 1, the mantissa exchange circuit 2, the comparison circuit 4, and the inverting circuits 5a and 5b always use the smaller mantissa from the larger mantissa to quickly determine the difference between the mantissas. Finding the absolute value. However, the means for obtaining the difference between the two numbers by the absolute value can be realized in addition to the means shown in the present embodiment, and the generality of the present invention is not lost even if realized by other methods.

As described above, in the present embodiment, since the rounding process and the normalizing process, which require an extremely long processing time, are performed in parallel, the addition / subtraction process can be performed at a higher speed than the conventional arithmetic device. . In particular, in the field of scientific and technological calculations, the number of bits in the mantissa tends to increase in order to increase the calculation accuracy, and the effect of the present invention on speeding up the calculation is great.

[Effects of the Invention] As described above, according to the present invention, since the rounding process and the normalizing process, which require an extremely long processing time, are executed in parallel, addition and subtraction are performed as compared with the conventional arithmetic unit. A floating-point arithmetic device capable of achieving high-speed processing can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a floating-point arithmetic device according to an embodiment of the present invention. FIG. 2 is a format diagram of a mantissa part operated by the device shown in FIG. 1, and FIGS. FIG. 1 is a diagram for explaining the operation of the apparatus shown in FIG. 1, and FIGS. 6 and 7 are block diagrams showing the configuration of a conventional floating point arithmetic unit. 1 exponent comparison circuit 2 mantissa exchange circuit 3 digit alignment circuit 4 operand comparison circuit 5 mantissa inversion circuit 6 adder 7 priority encoder 8 normalization circuit 9 Bidirectional 1-bit shifter 10 Incrementer 11 Rounding decision circuit 12 Solution selection circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/00 G06F 7/38 G06F 7/50

Claims (3)

(57) [Claims] A first comparing means for comparing the magnitudes of exponent parts in both operand values; a second comparing means for comparing magnitudes of absolute values in both operand values; On the basis of the comparison result, in order to unify the values of the exponent parts in both operand values, the mantissa part having a small exponent part in both operand values is digit-aligned with the mantissa part having a large exponent part. Digit alignment means for performing the comparison operation in parallel with the comparison means; and, based on the comparison result of the first and second comparison means, the absolute value of the mantissa parts of the two operands whose exponent values match. Means for inverting the value of only the mantissa with a small bit, and of the mantissas in both operands whose exponent values match,
In response to the mantissa part having a large absolute value and the mantissa part having a small absolute value bit-inverted by the inversion means, both mantissa parts are added or subtracted. In the case of subtraction, the small mantissa part is subtracted from the large mantissa part. And a calculation means for obtaining a calculation result of a positive number. 2. A normalizing means for performing a first normalization process on an operation result in said operation means to obtain a first solution, and a second normalization process and a rounding process on the operation result in said operation means. A normalizing and rounding processing means for obtaining a second solution in parallel with the normalizing means; and either a first solution obtained by the normalizing means or a second solution obtained by the normalizing and rounding processing means 2. The floating point arithmetic unit according to claim 1, further comprising: a solution selecting means for selecting one of the solutions to obtain a true solution. 3. The solution selecting means selects a first solution when a shift of 2 bits or more is required for the operation result obtained by the operation means, and selects a second solution otherwise. 3. The floating-point arithmetic device according to claim 2, wherein the solution is selected.