JPH0383126A - Floating-point multiplier - Google Patents

Abstract

PURPOSE:To reduce the circuit scale to increase the arithmetic processing speed by providing an OR circuit which operates OR between the carry signal of a fixed-point operation circuit and that of a rounding processing control circuit and incrementing the exponential part based on the output signal of the OR circuit. CONSTITUTION:In a floating-point multiplier, an OR circuit 43 which operates OR between a carry signal OF1 of a fixed-point operation circuit 10 and a carry signal OF2 of a rounding processing control circuit 17 is provided to increment the exponential part based on the output signal of the OR circuit 43. Thus, the normalization processing of the operation result of floating-point multiplication is performed with the simple circuit constitution.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an arithmetic circuit of an information processing device such as a microprocessor, and particularly relates to a floating point multiplier, and provides a floating point multiplier that has a small circuit scale and improves arithmetic processing speed. In a floating-point multiplier, the floating-point multiplier includes a fixed-point arithmetic circuit that performs fixed-point arithmetic operations, and a rounding control circuit that performs rounding processing, wherein the carry signal of the fixed-point arithmetic circuit and the rounding control circuit Equipped with an OR circuit that takes the logical sum of the carry signals of
The exponent part is incremented based on the output signal of the OR circuit.

[Industrial application field]

The present invention relates to an arithmetic circuit for an information processing device such as a microprocessor, and more particularly to a floating point multiplier.

Floating-point arithmetic has a wider dynamic range and higher accuracy than fixed-point arithmetic, so it can meet advanced arithmetic demands. In order to realize a lower cost floating point arithmetic unit, it is necessary to downsize the arithmetic circuit.

[Conventional technology]

FIG. 1 shows a block diagram of a conventional floating point multiplier.

The multiplier A and the multiplicand B input to the floating-point multiplier are normalized numbers according to the 1EEE754-1985 standard (hereinafter referred to as the IEEE standard), and have the following format.

A = (1) ilx m1x2 el-biasB
= (-1) '2 be.

Next, the operation will be explained.

The codes xi and s2 of the multiplier A and the multiplicand B are input to an EOR (exclusive OR) circuit 30, and the result of the operation is output as code data SN. The exponent parts el and e2 of the multiplier A and the multiplicand B are input to the first addition circuit 20 and added together, and then subjected to bi++ correction by the second addition circuit 21, that is, the (-b part is added), and the exponent data TE The mantissa Kmm2 of multiplier A and multiplicand B is output as
is calculated by the fixed-point multiplication circuit 10, and the result is output to the shifter 16 as fixed-point multiplication data TMI. Here, the fixed-point multiplication data TMI belongs to the range 1≦TMI<4, so the fixed-point multiplication data TMI is 2
If this continues, there is a possibility that the number will not be the normalized number according to the IEEE standard. Therefore, a bit of the first power of 2 of the fixed-point multiplication data TMI is used as a carry flag, and a carry signal OFI is output. When the carry signal OFI is 1, the mantissa is shifted to the right by the shifter 16, and the incrementer 22 Increments the exponent part. In other words, divide the mantissa by 2 and add 1 to the exponent.
Add. For example, if the value of fixed-point multiplication data TMI before normalization processing is TM 1 = (10,01+)2X 2, then the value of fixed-point multiplication data TMI after normalization processing is TM2. The value is T M 2 = (1,0011) X 2 '.

The normalized fixed-point multiplication data TM2 output by the shifter 16 has twice the number of bits as the operand. For example, if the number of bits of each operand is 16 bits, the number of bits of normalized fixed-point multiplication data TM2 is 3.
It is 2 bits. Therefore, it is necessary to approximate this with a number having the same number of bits as the operand. For this reason, an approximation process called rounding process is performed. The rounding process is performed using the half bits on the LSB side of the normalized fixed-point multiplication data TM2 (
For example, in the case of the above example, the 16 bits on the LSB side), the code data SN, and the control signal RM for determining the rounding mode are input to the rounding process control circuit 17 to generate the rounding process signal RD. The remaining half bits on the MSB side of the normalized fixed-point multiplication data TM2 (for example, 16 bits on the MSB side in the above example) are input to the incrementer 18, and whether or not to be incremented is determined by the rounding signal RD. It is decided. At this time, the output data of the incrementer 18, that is, the fixed-point multiplication data TM3 is (10,000)
2, and may not be the normalized number of the IEEE standard. Therefore, fixed-point multiplication data TM3
A carry signal OF2 is output using the bit of 2 to the 1st power as a carry flag. When the carry signal OF2 is 1, the shifter 19 shifts the mantissa part to the right, and the output data of the incrementer 23 is selected by the multiplexer 24, and the exponent part is incremented and normalized.

Finally, the exponent part is input to the exception handling circuit 40, and the IEEE
It is determined whether or not an exception defined in the standard has occurred, and if an exception has occurred, the constant generation circuit 41 and selector 42 output a corresponding bit pattern.

As described above, floating point multiplication of the multiplier A and the multiplicand B is performed.

[Problem to be solved by the invention]

Conventionally, when an arbitrary multiplication number A and non-multiplication number B of LM are input, the carry signal OFI and the carry signal OF2 do not become 1 at the same time, and the incrementer 2
2 and incrementer 23 never operated at the same time. Therefore, there is a problem that the circuit is redundant with respect to the function, and the circuit scale becomes unnecessarily large. Additionally, there is a problem in that the arithmetic processing speed decreases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a floating point multiplier that has a small circuit scale and improves arithmetic processing speed.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a floating-point multiplier including a fixed-point arithmetic circuit (10) that performs fixed-point arithmetic and a rounding control circuit (17) that performs rounding. an OR circuit (43) that takes the logical sum of the carry signal (OF1) of the arithmetic circuit (10) and the carry signal (OF2) of the rounding control circuit (17);
), and is configured to increment the exponent part based on the output signal of the OR circuit (43).

[Effect]

According to the present invention, O
By incrementing the exponent part calculation result based on the output signal of the R circuit, the floating point multiplication result can be normalized with a simple circuit configuration.

〔Example〕

Next, an embodiment of the present invention will be described in detail with reference to FIG. In FIG. 1, the same parts as in the conventional example shown in FIG. 2 are given the same reference numerals, and detailed explanations will be omitted.

The difference from the embodiment shown in FIG. This is a point that has the following features.

When a set of arbitrary multipliers A and non-multipliers B are input, the carry signal OFI and the carry signal OF2 will never become 1 at the same time. Therefore, the normalization process of the calculation result is performed only once for the input of any multiplication number A and non-multiplication number B of the upper string. That is, there are three combinations of output of the carry signal OF↓ and the carry signal OF2 as shown in FIG. 2, and if any of the carry signals becomes 1, the exponent part can be incremented. Therefore, the OR circuit 43 calculates the logical sum of the carry signal OFI and the carry signal OF2. Based on this output result, the multiplexer 24 selects either the incremented data or the non-incremented data, thereby incrementing the exponent part data.

〔Effect of the invention〕

Since the present invention is configured as described above, it has the advantage that the circuit configuration of the floating point multiplication circuit can be simplified. Furthermore, since the circuit configuration is simple, the processing speed is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram explaining the state of a carry signal, and FIG. 3 is a block diagram of a conventional example. 10...Fixed point multiplication circuit 16...Shifter 17...Rounding control circuit 18...Incrementer 19...Thick 20...Addition circuit 21...Addition circuit 22...Incrementer 23... Incrementer 24... Multiplexer 30... EOR circuit 40... Exception processing circuit 41... Constant generation circuit 42... Selector 43... OR circuit SN... Code data OFI. ...Carry signal OF2...Carry signal RD...Rounding signal RM...Control signal

Claims (1)

[Claims] A fixed-point arithmetic circuit (10) that performs fixed-point arithmetic, and a rounding control circuit (17) that performs rounding.
A floating point multiplier comprising: an OR circuit (43) for calculating the logical sum of a carry signal (OF1) of the fixed point arithmetic circuit (10) and a carry signal (OF2) of the rounding control circuit; The OR circuit (43)
A floating point multiplier characterized in that an exponent part is incremented based on an output signal of the floating point multiplier.