JPH0283728A - Floating point multiplier - Google Patents

Abstract

PURPOSE:To improve multiplying speed by attaining the multiplication with only a final normalization without normalizing a multiplier and a multiplicand and simultaneously deciding the overflow and underflow states via a 1-byte addition/subtraction unit. CONSTITUTION:A multiple of an appropriate multiplicand is selected 50 out of a register 30 based on the value of the least significant 4 bits of a register 40 and added 21 with the value obtained by shifting right a register 10 by 4 bits. These added values are set at the register 10. The value obtained by shifting right the register 10 by 4 bits via a shift circuit 20 is set at a register 11 with the least significant 4 bits of the register 10 used as a right shift carry. The multiplier of the register 40 is shifted right by 4 bits by a shifter 60. This process is applied to all digits of the multiplier and the mantissas of the intermediate products are stored in the registers 10 and 11. The multipliers and multiplicands stored in the registers 70 and 80 undergo the addition 90 and the correction of -64 via an exponent part. The results of these addition and correction are set at the register 80 and corrected with normalization. Then the product exponent part of the register 80 is merged with the product mantissa parts of the registers 10 and 11 for acquisition of a product.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a floating point multiplication device for a digital computer;
In particular, the present invention relates to a multiplication device that quickly detects overflow or underflow of an exponent and calculates a product.

[Conventional technology]

In conventional floating-point multiplication, the multiplier and multiplicand, both expressed as floating-point numbers, are shifted to the left by digits until the most significant digit of the mantissa contains a non-zero value, and the number of shifted digits is subtracted from the exponent. After normalization, floating-point multiplication, that is, addition of exponents and multiplication of mantissas, is performed, and if the most significant digit of the mantissa of the resulting intermediate product is zero, it is moved to the left. A 1-digit shift is performed, and the exponent part of the intermediate product is decreased by 1. Therefore, a maximum of three shift operations and subtraction of the exponent part are required.

In addition, when determining exponent overflow or underflow of the multiplication result, the exponent part is expanded by 2 bits to the ``] place of the exponent part of 1 to 7 bits 1-, and the exponent part is calculated as 9 bits I~ width. The determination is made using the values for the top two hiso1 of -. For this reason, the exponent part calculation of multiplication is performed using a 4-hide width arithmetic unit, which is sufficient for 1 byte width, which incurs various overheads. A specific example will be explained below.

Normalization 7. % The floating decimal point is a sword symbol for political opponents, defeat or defeat,
It consists of an exponent part and a mantissa part. Above, the sign is l bit and O is stop, ] indicates negative, and the exponent part is 7 hino I ~ and Fcess is 64.
Let us take as an example a floating point number represented by the following expression, whose mantissa is 24 pinots. FIG. 2 is a specific example of FCS64 expression.

In the exponent operation, the multiplier and multiplicand are each shifted to the right by 24 bits and stored in work registers WKO and WK1. By doing this, the exponent part is stored at the right end of the work register, and a cello is stored in the 1st place 3by1~. Thereafter, WKO+WK is performed using a 4-by-1 width adder, and the result is stored in WN2. On the other hand, multiply the mantissa parts, check whether normalization is necessary for the result, shift the mantissa of the product by one digit to the left if necessary, and execute WN2-1. FIG. 3 shows possible values of the exponent part (ie, the value of WN2) at this time. From Figure 3, it is determined that there is an exponent underflow when the 233rd bit of WN2 is 0, and when the 23rd bit is O and the 24th bit is 1, it is determined that there is an exponent overflow3. In addition, floating point arithmetic Related publications include, for example, Japanese Patent Laid-Open No. 62-49540. 1 [Problem to be solved by the invention]: The prior art described in 3-4- has the following problems in floating point multiplication processing:
Since normalization is performed up to three times and a 4-byte wide adder is used to determine exponent overflow and exponent underflow, it is necessary to shift the exponent part by, for example, 24 pips to the right, which improves calculation speed. This is the bottleneck for 1-.

An object of the present invention is to improve the calculation speed in floating point multiplication.

[F stage for solving problems]

In order to achieve the object described in (1), the present invention provides an exponent part calculation having a length of an exponent extension part of 1 pixel I to the upper part of each exponent part of a multiplier and a multiplicand. A mantissa operation that takes an adder/subtractor and the mantissa parts of the multiplier and multiplicand as input, and outputs the product of the multiplier and multiplicand without rounding, with an output width that is greater than or equal to the sum of the data widths of the mantissa parts of each of the multiplier and multiplicand. a shifter having an arithmetic width equal to or greater than the output width of the multiplier for -1- storage mantissa operations, and -1-
A circuit for detecting the number of consecutive zero digits from the beginning of the output of the triple multiplier for calculating the mantissa part, and a circuit for detecting the number of consecutive zero digits from the beginning of the output of the triple multiplier for calculating the mantissa part, and the value for the Oth bit and the first bit 1 of the output of the adder/subtractor for calculating the exponent part. A circuit that outputs exclusive OR is provided.

[For production]

When adding the extended exponent part to 1 bit 1 to the 1-place of the exponent part of the multiplier and multiplicand, after setting the bin 1~ to zero, manually input the exponent part to the adder/subtractor for exponent part calculation. 1
, in the exponent calculation adder/subtractor, when both input exponent parts are added, if the exponent value is expressed by adding a deviation (for example, Fcess 64 expression), the added value is subtracted by that deviation. Sign. On the other hand, the mantissa parts of the multiplier and the multiplicand are manually input to a mantissa calculation multiplier without being normalized, and the product is output without being rounded. Since both the multiplier and the multiplicand are not normalized to 1, there are generally several consecutive zero digits in the upper part of this product.

Next, the number of consecutive zero digits from the -1- place of this product is detected using a circuit that detects the number of consecutive zero digits from the beginning of the output of the mantissa calculation multiplier. 1- Input the product and the number of digits, and normalize the product by shifting the product to the left by the number of digits. The exponent part is corrected by normalization by inputting it to an adder/subtractor for calculating the exponent part and subtracting the above-mentioned number of digits from the exponent part. It can be seen that when the Oth bit of the exponent part after correction is 1, exponent overflow or exponent underflow occurs. Furthermore, whether exponent overflow or exponent underflow is likely to occur can be determined by the value of the exclusive OR of the values of the O-th bit and the first bit of the exponent part before exponent correction. That is, when the value of the exclusive OR is 1, it can be determined that there is a possibility that an exponent overflow will occur. This is because correction of the exponent part by normalization can only occur in the direction of decreasing the exponent part, and.

The correction value is also 27 at most even when the multiplier and multiplicand have good precision, so when it is determined that there is a possibility of exponent overflow occurring before correction (i.e., the value of the exclusive OR above is 1). When it is determined that there is a possibility of exponent underflow (i.e., when the value of the above exclusive OR is O ), it is impossible for exponential overflow to occur due to correction by normalization.

As a result of the above, multiplication is possible without normalizing the multiplier and multiplicand by just one final normalization, and overflow and underflow can be determined using a 1-byte adder/subtractor. Since it is known which of these may occur before the final product is determined, the speed of the multiplication process can be greatly improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. 10 and 11
is an intermediate product storage mantissa storage register; 20 is a shift circuit;
21 is a mantissa calculation unit; 30 is a group of registers for storing the multiplicand and its multiples before normalization; 40 is a multiplier storage register; Multiple selection circuit to select, 6
0 is a shifter that shifts a number to the right by 4 bits, 70 is an 8-bit wide register with a 1-bit 0 added to the upper part of the exponent part of the multiplier, and 80 is a 1-bit O bit added to the upper part of the exponent part of the multiplicand. 8-bit wide register with .

90 is an exponent part arithmetic unit, 100 is a leading zero digit counting circuit, and 110 is an exclusive OR circuit.

As an initial setting, registers 10 and 11 are set to all zeros. A multiple selection circuit 50 selects an appropriate multiple of the multiplicand from the register 30 based on the value of the lowest 4 bits of the multiplier storage register 40, and the arithmetic unit 21 adds it to the value of the intermediate product storage register 10 shifted to the right by 4 bits. The addition result is set in register 10. Further, the value obtained by shifting the register 11 to the right by 4 bits in the shift circuit 20 is transferred to the register 11 by using the lowest 4 bits of the register 10 as a right shift carry.

The multiplier in the multiplier storage register 40 is shifted 4 bits to the right by the shifter 60. By performing the above processing for all digits of the multiplier stored in register 40, the mantissa part of the intermediate product is stored in registers 10 and 11. If the mantissa parts of the multiplier and the multiplicand are each N bytes, this product has a maximum of 2N bytes. However, since both the multiplier and the multiplicand are not normalized, there are generally several consecutive zero digits in the upper part of this product. FIG. 5 shows a specific example of the mantissa calculation.

The exponent parts of the multipliers and multiplicands stored in registers 70 and 80 are added and corrected by -64 (in the case of Fcess 64 expression in Fig. 2) by the 1-byte arithmetic unit 90, and the resulting intermediate product is The exponent part is set in register 80. At this time, the 0th bit 1-th and the 1st bit of the exponent part are 1
When the value is 0 or 01, the EXPOV flag is set. FIG. 4 shows the possible values of the output when performing the exponent calculation, taking the FCS64 expression as an example.

Thereafter, the contents of the intermediate product storage register 10.11 are checked by the leading zero digit counter 1 to circuit 100. The count obtained by the count circuit 100 is sent to the shift circuit 2.
0, and the contents of intermediate product storage registers 10.11 are shifted to the left digit by digit until there are no leading 0 digits. Further, the count obtained by the leading zero digit count circuit 100 is sent to a 1-byte width arithmetic unit 90, and the value of the exponent part of the intermediate product stored in the register 80 is corrected by normalization. FIG. 6 shows possible values of the exponent part after correction, assuming that the multiplicand and the multiplier each have good precision (sign 1 bit, exponent part 7 bits 1~, mantissa part 5 G bits).

When bit 0 (EXI)O) of the exponent part after correction is 1, it indicates that either an exponent overflow or an exponent underflow has occurred, and if (EXPO=1) & (EXPOV=1), an exponent overflow has occurred. , (EXP◯=1) & (EXI)OV=O) indicates that an index underflow has occurred.

The product can be obtained by merging the contents of the other stored product sign bit, product exponent storage register 80, and product mantissa storage register 10.11.

According to this embodiment, by omitting the normalization of the multiplier and the multiplicand and quickly determining exponent overflow and underflow, it is possible to significantly improve the performance of floating point multiplication.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, normalization processing of multipliers and multiplicands is not required in floating point multiplication, and exponent part calculations and determination of exponent overflow and exponent underflow can be performed using 1 pie 1 to 1 calculation. It can be executed on a single device, does not require shift processing, and can significantly speed up floating-point multiplication processing.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram showing a specific example of F-S64 expression, Fig. 3 is a diagram showing a conventional example of exponent operation, and Fig. 4 is an exponent in the present invention. FIG. 5 is a diagram showing an example of the calculation before normalization, FIG. 5 is a diagram showing a specific example of the mantissa calculation of the present invention, and FIG. 6 is a diagram showing an example of the exponent calculation after normalization. 10.11. Intermediate product mantissa storage register, 80... Intermediate product exponent storage register, 100... Intermediate product leading zero digit counter I-circuit, FIG.

Claims (1)

[Claims] (1) An adder/subtractor for exponent part calculations having a calculation width equal to the length of the exponent part of each of the multiplier and the multiplicand with a 1-bit exponent extension added to the upper part of the exponent part, and the mantissa part of each of the multiplier and the multiplicand as input, A multiplier for mantissa calculation that outputs the product of the mantissa parts of each of the multiplier and the multiplicand, a shifter that receives the product as input, and a zero digit that detects the number of consecutive zero digits from the beginning of the mantissa part of the final intermediate product. It is equipped with a detection circuit and a decoder circuit which inputs the output bits 0 and 1 of the adder/subtractor for exponent part calculation, and without normalizing the above multiplier and multiplicand, 1 bit is added to the upper part of each exponent part. At the same time as adding the extended exponent part, set that bit to zero, add the exponent part and multiply the mantissa part, and input the mantissa part of the final intermediate product found to the above zero detection circuit, and then The mantissa part of the final intermediate product is shifted to the left by the number of zero digits in the shifter, and the number of digits is subtracted from the exponent part of the final intermediate product in the exponent part calculation adder/subtractor to calculate the product. The exponent part and the mantissa part are determined, and overflow and underflow of the exponent part are detected based on the value of bit 0 of the exponent part of the product obtained and the values of bit 0 and bit 1 of the exponent part of the final intermediate product. floating point multiplier.