CN1086816C - Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication - Google Patents
Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication Download PDFInfo
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- CN1086816C CN1086816C CN95120595A CN95120595A CN1086816C CN 1086816 C CN1086816 C CN 1086816C CN 95120595 A CN95120595 A CN 95120595A CN 95120595 A CN95120595 A CN 95120595A CN 1086816 C CN1086816 C CN 1086816C
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- multiplication
- partial product
- multiplier
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
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- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
A multiplier for selectively performing an unsigned magnitude multiplication or a signed magnitude multiplication with a modified Booth algorithm for a multiplication operation. It includes a selection unit which provides an extension bit for performing an unsigned magnitude multiplication in a signed magnitude multiplication which is expressed by a two's complement format, and a partial product generator for performing a sign digit operation increased by the extension bit. It preferably also includes a carry look-ahead adder for generating and propagating a look-ahead carry.
Description
The present invention relates to multiplier, particularly utilize this (Boolh) algorithm of improved cloth to carry out the multiplier that unsigned value multiplication or signed magnitude multiplication carry out multiply operation selectively.
Multiplication is the main operation during the digital signal processing (after this being called DSP) of processing pictorial data is operated.
When the design multiplier, for example the such operating unit needs of the ALU (after this being called ALU) of CPU (central processing unit) (after this being called CPU) can carry out the multiplier of unsigned value multiplication or signed magnitude multiplication selectively.
Realize that in ALU the method that unsigned value multiplies each other or signed magnitude multiplies each other is not only to use the unsigned value multiplier but also use the signed magnitude multiplier.But, because used two multipliers, so this method needs more circuit area.
Realize that in ALU unsigned value multiplies each other or signed magnitude multiplies each other other method is to compensate the long-pending and unsigned value of signed magnitude poor between long-pending with adjunct circuit.When the highest significant position of a certain operand is " 1 ", this method with except the highest significant position of remaining position-another operand-with last long-pending addition.But, be difficult to obtain be considered to the square layout of the advantage of array multiplier with this method.
The United States Patent (USP) 5,153,850 that is entitled as " improving the method and apparatus that the two's complement multiplier is carried out the unsigned value multiplication " that authorize August 24 nineteen ninety has been described the multiplier of carrying out unsigned value multiplication or two's complement multiplication.The described multiplier of this United States Patent (USP) is carried out two's complement multiplication or unsigned value multiplication selectively, proofreaies and correct two's complement with adjunct circuit and amasss, and it is long-pending to obtain unsigned value then.
About the algorithm of multiplication, " digital CMOS circuit design " (211-221 page or leaf) that Macro Annaratone is shown described improved Booth.
This improved Booth is a kind of record algorithm, it is right that it is divided into predetermined position with first operand, after each right operation of having carried out corresponding to second operand, obtained partial product as intermediate result, each right partial product corresponding to another operand that summation generates is utilized two operands to multiply each other and is obtained end product.In addition, improved Booth thinks that " 0 " does not act on multiplication, has improved the operating speed of multiplication.
Fig. 1 is the block scheme that utilizes the ordinary binary complement multiplication device of Booth.
As shown in Figure 1, general two's complement multiplier comprises scrambler 1, symbol transfer unit 2, and displacement and rp unit 3, the first are to third part product generator 4,5 and 6, and carry lookahead adder 7.The multiplier of Fig. 1 is 8 * 8 multipliers, and " A " is defined as 8 multiplicand, and " B " is defined as 8 multiplier.
Operand " B " input coding device 1.The position of scrambler 1 encoding operation number " B " is right, and form corresponding to the right group of coded digital again in position (promptly-2x ,-1x, 0x ,+1x ,+2x).
Again each of coded digital group again coded digital send in unit 3 and three partial product generators 4,5 and 6 one respectively to.Unit 3 and three partial product generators 4,5 and 6 are carried out operation accordingly with respect to operand " A ".
The P as a result that obtains＜15: 0〉outwards export by carry lookahead adder 7.The purposes of symbol transfer unit 2 is sign bits of expansion multiplicand.
This multiplier is carried out and is represented as the signed magnitude multiplication of two's complement, but can not carry out the unsigned value multiplication.
The purpose of this invention is to provide and utilize improved Booth to carry out the multiplier that unsigned value multiplication or signed magnitude multiplication carry out multiply operation selectively, this multiplier can solve the problem in the prior art.
In order to realize this purpose, the present invention includes: the position that receives first operand, this operand of encoding is to also forming the scrambler corresponding to each right coded digital again; The coded digital again that is used to the own coding device after second operand is carried out shifting function and operated in anti-phase forms the displacement and the rp unit of intermediate result; Form selectively corresponding to from the service data of the second operand of the coded digital again of scrambler and by utilize displacement and rp unit respectively with service data and partial product mutually Calais's generating unit divide long-pending first's product generator, sequentially connect and by second to the 4th partial product generator that amasss of Calais's generating unit branch mutually between the output data of previous stage and corresponding service data with the output terminal of first product generator; Be connected so that provide signal and the symbol transfer unit of the extended operation of DO symbol position in second operand with rp unit and first to fourth partial product generator (hereinafter to be referred as the partial product maker) with displacement; Utilize input select signal to judge that multiplication is unsigned value multiplication or signed magnitude multiplication and the selected cell that the extension bits of two operands is offered scrambler and displacement and rp unit when multiplication is the unsigned value multiplication.
Multiplier of the present invention also comprises with the output terminal of the 4th partial product maker and being connected so that produce and transmit the carry lookahead adder of carry lookahead.
Fig. 1 is the block scheme of the common two's complement multiplier of prior art;
Fig. 2 is the block scheme of the multiplier of carrying out unsigned value multiplication or signed magnitude multiplication selectively of most preferred embodiment of the present invention.
Read following detailed description referring to accompanying drawing and will understand most preferred embodiment of the present invention.
Before the multiplier of describing most preferred embodiment of the present invention shown in Figure 2, at first explanation is applied to the multiply operation process of most preferred embodiment of the present invention, for example 8 * 8 multiplication.
An operand be " A " and another operand under the situation of " B ", following formula is described as signed number, unsigned number and binary number with (4) * (2).
A×B
(4) * (2) ... the signed number form
+ 252 *+254 ... unsigned number form 1,111 1100 * 1,111 1110 ... binary number formats
Above-mentioned signed magnitude multiplication process is described in the Table A below.
Table A
In above formula, be respectively operand " B " coded digital again center left side (2x) and (0x) 3 positions making operand " B " and 1 position to relevant and definite this right respective symbol numeral.
Table B
| Bit(i+1) | Bit i | Bit(i-1) | recoded |
| 0 | 0 | 0 | 0x |
| 0 | 0 | 1 | +1x |
| 0 | 1 | 0 | +1x |
| 0 | 1 | 1 | +2x |
| 1 | 0 | 0 | -2x |
| 1 | 0 | 1 | -1x |
| 1 | 1 | 0 | -1x |
| 1 | 1 | 1 | 0x |
Referring to table B, sign digit 0x makes " 0 " and partial product addition, sign digit 1x makes operand " A " and partial product addition, sign digit 2x make twice operation " A " (promptly 2 * A) with the partial product addition, sign digit-1x deducts operand " A " from partial product, sign digit-2x deducts the operand " A " (promptly 2 * A) of twice from partial product.
Therefore, from the high-order position centering of operand " B " sequentially obtain again coded digital (be 0x, 0x, 0x and-2x).In order to realize " subtracting-2 * A " operation, just carry out anti-phase A, add 1 and to shifting left 1 operation.
In addition, utilize the above multiplication that produces the decimal number 8 of the last product term P of conduct to obtain four partial products.
For the unsigned value multiplication, should before the incoming symbol position, add two " 0 ", shown in following table C.
Table C
As show shown in the C, coded digital to producing, is that 4 signed magnitude multiplication compare with the partial product number by the position of operand " B " again, the number of part product term becomes 5.The position of operand " B " is to being used as illustrating with comultiplication of example.With comultiplication operand " B " (promptly 001111111110) is divided into 5 positions to (i.e. (001), (111), (111), (111), (110)).Each is to use wanting superimposed 1 respectively, if last position to having only two, will this position internal the 3rd of this multiplication thinks " 0 ".
Compare with general multiplication, the unsigned value multiplication has the accurate and effective characteristics of processing of result.General multiplication is shown in following table D.
Table D
As show shown in the D, the general multiplication of two operand A and B is decimal numeral 252 to multiply by 254.Therefore, its end product is decimal numeral 64008.
Below referring to Fig. 2 the multiplier of carrying out unsigned value multiplication or signed magnitude multiplication selectively of most preferred embodiment of the present invention is described.
The multiplier of most preferred embodiment of the present invention comprises selected cell 21, scrambler 22, symbol transfer unit 23, displacement and rp unit 24, first to fourth partial product maker 25,26,27 and 28 and carry lookahead adder 29.
The multiplier of Fig. 2 is 8 * 8 multipliers, and " A " is defined as 8 multiplicand, and " B " is defined as 8 multiplier.
Operand " B " input coding device 22.The position of scrambler 22 encoding operation numbers " B " is right, and form corresponding to the right group of coded digital again in position (promptly-2x ,-1x, 0x ,+1x ,+2x).The method that forms sign digit takes advantage of 8 the method for multiplication identical with 8.
Each sign digit of sign digit group sends in unit 24 and four partial product makers 25,26,27 and 28 respectively to.Unit 24 and four partial product makers 25,26,27 and 28 are carried out operation accordingly with respect to operand " A ".
Displacement and rp unit 24 and first to fourth partial product maker 25,26,27 and 28 are linked in sequence each other.In when operation, previous stage and and carry send next stage respectively to.Therefore, make again the partial product addition of the service data and the previous stage of coded digital when prime.
As for corresponding to each operation of coded digital again, when coded digital again be-during 2x, in order to utilize operand " A " realization " to subtract-2 * A " operation, just carry out the data that will obtain by anti-phase A and previous stage the partial product addition, add 1 and to shifting left 1 operation.
When sign digit be-during 1x, " subtract-1 * A " operation in order to utilize operand " A " realization, the partial product of just carrying out the data that will obtain by anti-phase A and previous stage adduction mutually adds 1 operation.
When sign digit was 0x, with " 0 " the partial product addition with previous stage, sign digit 0x did not have the practical operation effect.
When sign digit be+during 1x, with the partial product addition of operand " A " with previous stage.
When sign digit be+during 2x, " add+2 * A " operation, just with the partial product addition of operand " A " to the data and the previous stage of 1 acquisition of shifting left in order to utilize operand " A " realization.
The P as a result that obtains＜15: 0〉outwards export by carry lookahead adder 29.Symbol transfer unit 23 is connected so that signal transmits with 28 with displacement and rp unit 24 and first to fourth partial product maker 25,26,27 respectively.The result is exactly that this symbol transfer unit 23 had not only transmitted symbol but also receiving symbol.
Carry lookahead adder 29 is connected with the output terminal of the 4th partial product maker 28, utilize from 28 outputs of the 4th partial product maker and and carry produce and transmit carry lookahead, improve the operating speed of signed magnitude multiplication thus.
The signal se1 that utilization inputs to selected cell 21 carries out the unsigned value multiplication.If utilize signal se1 to select the unsigned value multiplication, selected cell 21 just will be exported to scrambler 22 and displacement and rp unit 24 by the position (1) and (2) that sign bit is expanded.
The operation subsequently of unsigned value multiplication is identical with the operation of signed magnitude multiplication.
As mentioned above, according to most preferred embodiment of the present invention, the present invention can provide and utilize improved Booth to carry out the multiplier that unsigned value multiplication or signed magnitude multiplication carry out algorithm operating selectively.
Particularly, the present invention utilizes selected cell to import extension bits in the unsigned value multiplication.Therefore, the present invention not only can carry out the signed magnitude multiplication, and can carry out the unsigned value multiplication.In addition, because circuit structure of the present invention is simple, so it does not reduce operational processes speed, it occupies quite little area when making integrated circuit.
Claims (3)
1, a kind of unsigned value multiplication of two operands or multiplier of signed magnitude multiplication carried out selectively, it comprises:
Scrambler, receive in the operand one, the position of this operand of encoding to and form corresponding to each right coded digital again;
Displacement and rp unit are connected with described scrambler output terminal, utilize the sign digit of scrambler output to form intermediate result after another operand is carried out shifting function and operated in anti-phase;
The first partial product maker, form respectively corresponding to the service data of another operand of the coded digital again of scrambler output and by utilize displacement and rp unit respectively with service data and partial product mutually Calais's generating unit divide long-pending, second, third, the 4th partial product maker connects with the output terminal of first, second, third partial product maker respectively and by between the output data of previous stage and corresponding service data mutually Calais's generating unit branch amass;
The symbol transfer unit is connected with rp unit and first to fourth partial product maker with displacement, so that provide signal and the extended operation of DO symbol position in another operand; And
Selected cell utilizes input select signal to judge that multiplication is that unsigned value multiplication or signed magnitude multiplication also offer scrambler and displacement and rp unit with the extension bits of two operands when multiplication is the unsigned value multiplication.
2,, also comprise with the output terminal of the 4th partial product maker being connected so that produce and transmit the carry lookahead adder of carry lookahead according to the multiplier of claim 1.
3, according to the multiplier of claim 1, wherein, settle by 8 * 8 multipliers.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR12754/95 | 1995-05-22 | ||
| KR1019950012754A KR0158647B1 (en) | 1995-05-22 | 1995-05-22 | Multiplier using both signed number and unsigned number |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1136680A CN1136680A (en) | 1996-11-27 |
| CN1086816C true CN1086816C (en) | 2002-06-26 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95120595A Expired - Fee Related CN1086816C (en) | 1995-05-22 | 1995-12-11 | Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH08314697A (en) |
| KR (1) | KR0158647B1 (en) |
| CN (1) | CN1086816C (en) |
| DE (1) | DE19545900B4 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944009B (en) * | 2009-07-06 | 2012-04-18 | 北京中电华大电子设计有限责任公司 | Device for processing quotient of divider in integrated circuit |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004092946A1 (en) * | 2003-04-17 | 2004-10-28 | Zhizhong Li | Digital engineering method and processor of the mixed q n-ary and carry line |
| WO2007094223A1 (en) | 2006-02-15 | 2007-08-23 | Matsushita Electric Industrial Co., Ltd. | Multiplier, digital filter, signal processing device, synthesis device, synthesis program, and synthesis program recording medium |
| US7797366B2 (en) * | 2006-02-15 | 2010-09-14 | Qualcomm Incorporated | Power-efficient sign extension for booth multiplication methods and systems |
| US7809783B2 (en) * | 2006-02-15 | 2010-10-05 | Qualcomm Incorporated | Booth multiplier with enhanced reduction tree circuitry |
| US8495125B2 (en) * | 2009-05-27 | 2013-07-23 | Microchip Technology Incorporated | DSP engine with implicit mixed sign operands |
| CN106897046B (en) * | 2017-01-24 | 2019-04-23 | 青岛专用集成电路设计工程技术研究中心 | A kind of fixed-point multiply-accumulator |
| CN113656751B (en) * | 2021-08-10 | 2024-02-27 | 上海新氦类脑智能科技有限公司 | Method, apparatus, device and medium for realizing signed operation by unsigned DAC |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4831577A (en) * | 1986-09-17 | 1989-05-16 | Intersil, Inc. | Digital multiplier architecture with triple array summation of partial products |
| US4868778A (en) * | 1987-05-19 | 1989-09-19 | Harris Corporation | Speed enhancement for multipliers using minimal path algorithm |
| US4926371A (en) * | 1988-12-28 | 1990-05-15 | International Business Machines Corporation | Two's complement multiplication with a sign magnitude multiplier |
| US5226003A (en) * | 1990-07-17 | 1993-07-06 | Kabushiki Kaisha Toshiba | Multi-path multiplier |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153850A (en) * | 1990-08-24 | 1992-10-06 | Mass Microsystems | Method and apparatus for modifying two's complement multiplier to perform unsigned magnitude multiplication |
| JPH05150950A (en) * | 1991-11-29 | 1993-06-18 | Sony Corp | Multiplier circuit |
| TW421757B (en) * | 1996-06-06 | 2001-02-11 | Matsushita Electric Ind Co Ltd | Arithmetic processor |
-
1995
- 1995-05-22 KR KR1019950012754A patent/KR0158647B1/en not_active IP Right Cessation
- 1995-12-08 DE DE19545900A patent/DE19545900B4/en not_active Expired - Fee Related
- 1995-12-11 CN CN95120595A patent/CN1086816C/en not_active Expired - Fee Related
-
1996
- 1996-05-13 JP JP8117487A patent/JPH08314697A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4831577A (en) * | 1986-09-17 | 1989-05-16 | Intersil, Inc. | Digital multiplier architecture with triple array summation of partial products |
| US4868778A (en) * | 1987-05-19 | 1989-09-19 | Harris Corporation | Speed enhancement for multipliers using minimal path algorithm |
| US4926371A (en) * | 1988-12-28 | 1990-05-15 | International Business Machines Corporation | Two's complement multiplication with a sign magnitude multiplier |
| US5226003A (en) * | 1990-07-17 | 1993-07-06 | Kabushiki Kaisha Toshiba | Multi-path multiplier |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944009B (en) * | 2009-07-06 | 2012-04-18 | 北京中电华大电子设计有限责任公司 | Device for processing quotient of divider in integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19545900B4 (en) | 2005-08-25 |
| CN1136680A (en) | 1996-11-27 |
| DE19545900A1 (en) | 1996-11-28 |
| JPH08314697A (en) | 1996-11-29 |
| KR0158647B1 (en) | 1998-12-15 |
| KR960042336A (en) | 1996-12-21 |
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