JPH1115641A - Multiplier using redundant binary adder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate multiplying processing by adding two partial products with the same code weight as the code of a multiplier encoding result and two partial products with a reverse code weight at a partial product adding means. SOLUTION: A first partial product generating means 110 generates a partial product from a multiplicand X so as to have the same code weight as the code of the encoding result of a multiplier encoding means 100. A second partial product generating means 111 generates a partial product from the multiplicand X so as to have a code weight reverse to the code of the encoding result of a multiplier encoding means 100. Then a first partial product adding means 120 adds two of the respective partial products generated by the means 110 and 111 and outputs one redundant binary number data. A second partial product adding means 130 adds plural outputted redundant binary number data to output one redundant binary number data and a redundant binary/binary transformation means 140 transforms this data to binary number data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication device using a redundant binary adder.

[0002]

2. Description of the Related Art A conventional multiplier using a redundant binary adder generates a partial product according to a Booth's algorithm, performs addition of the partial product by a redundant binary adder, and expresses the result by a redundant binary number. The final sum of the obtained partial products is converted into a binary number and output. Of these, a redundant binary adder is used to add a redundant binary number expression by expressing it as two bits of a sign bit and an absolute value bit, and to add a redundant binary number expression to a bit having a weight of value “1” and a value. It has been proposed to add two bits together with a bit having a weight of “−1” to perform addition. For example, Japanese Patent Application Laid-Open Nos.
See 214755.

[0003]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. 63-1827
In the first conventional example described in JP-A-39-39, when generating partial products, the first partial product addition is performed at high speed by generating a pair of partial products in which the signs of the bits are different from each other. However, there is a problem that a logic circuit is required which reverses the sign of one partial product according to the sign of the other partial product.

In the second conventional example described in Japanese Patent Application Laid-Open No. 6-214755, a redundant binary adder constituting a multiplier has a weight of a value "1" as an expression of a value "0". Since the expression in which both the bit and the bit having the weight of the value “−1” are both set is prohibited, there is a problem that a numerical expression conversion unit is required.

[0005] That is, both examples require a means for making preparations from the generation of partial products to the execution of partial product addition.

Therefore, an object of the present invention is to achieve a high-speed multiplication process by adopting a configuration that does not require the above-mentioned preparation means.

[0007]

In order to achieve the above object, a multiplication apparatus according to the present invention is characterized in that the partial product adding means includes two partial products having the same code weight as the code of the multiplier encoding result, and a multiplier encoding unit. The result is added with two partial products having opposite sign weights to the sign of the result, and one redundant binary data is output as an addition result.

[0008]

FIG. 1 is a block diagram showing a configuration example of a multiplication device according to the present invention. In FIG. 1, 100
Is a multiplier encoding means for encoding the multiplier by the Booth algorithm. Reference numeral 110 denotes first partial product generation means for outputting the output of the multiplier encoding means 100 and the multiplicand in binary notation in which the sign of each bit is not inverted. Reference numeral 111 denotes a second partial product generation unit for outputting a binary representation in which the sign of each bit is inverted from the output of the multiplier encoding unit 100 and the multiplicand.
120 adds two of the partial products generated by the first partial product generation means 100 and two of the partial products generated by the second partial product generation means 111 to generate one redundant binary data As a result of addition. 130 is an output of the first partial product addition means 120 and the first partial product addition means 12
The second term for obtaining the product of the redundant binary representation from the correction term KH of the first partial product generation means 110 that could not be added by 0 and the correction term JH of the second partial product generation means 111. It is a partial product addition means. Reference numeral 140 denotes a redundant binary / binary conversion unit for converting the product of the redundant binary number expression obtained by the second partial product adding unit 130 into a product of the binary number expression.

[0009] The operation of the multiplication device configured as described above will be described. First, the multiplicand X [15: 0] and the multiplier Y [1
5: 0] is a 16-bit binary number expressed in a two's complement system. First, the multiplier is encoded by the multiplier encoding means 100 using a secondary Booth algorithm. When the encoding result of the multiplier encoding means 100 is any positive number other than zero, the first partial product generating means 110 outputs an arbitrary multiple of the multiplicand, and the encoding result of the multiplier encoding means 100 is other than zero. If it is an arbitrary negative number, a logical inversion of each bit is output for any multiple of the multiplicand, and a correction term for 2's complement is output at the position of the least significant bit of the partial product. When the encoding result of the multiplier encoding means 100 is zero, 0 is output to each bit, so that the multiplier encoding means 10
A partial product is generated from the multiplicand X so as to have the same code weight for the code resulting from the encoding of 0. When the encoding result of the multiplier encoding means 100 is any positive number other than zero, the second partial product generating means 111 outputs a logical inversion of each bit for an arbitrary multiple of the multiplicand, and Is output at the position of the least significant bit of the partial product, and when the encoding result of the multiplier encoding means 100 is any negative number other than zero, an arbitrary multiple of the multiplicand is output. When the encoding result of the multiplier encoding means 100 is zero, 0 is output to each bit, so that the code of the encoding result of the multiplier encoding means 100 is subjected to partial product from the multiplicand X so as to have the opposite sign weight. Generate

[0010] The partial product generated by the first partial product generating means 110 and the partial product generated by the second partial product generating means 111 are the correction term KH of the first partial product generating means 110 and the second partial product. Are input to the first partial product addition means 120 except for the correction term JH of the partial product generation means 111. The first partial product adding means 120 adds data having two positive weights and data having two negative weights for each bit, and adds the addition result to two redundant binary data L [22:
0] and M [30: 6].

The second partial product adding means 130 outputs the output data L [22: 0] and M of the first partial product adding means 120.
[30: 6], the correction term KH output from the first partial product generation means 110, and the correction term JH output from the second partial product generation means 111 are added, and the addition result N [ 3
1: 0] in redundant binary notation.

The PG generating means 150 constituting the redundant binary / binary converting means 140 has a carry generating function G [31: 0] for each bit from the output N [31: 0] of the second partial product adding means 130. ] And carry propagation function P [31: 0] are generated and output. The final adding means 160 constituting the redundant binary / binary converting means 140 obtains the multiplicand X [1] from the outputs G [31: 0] and P [31: 0] of the PG generating means 150.
5: 0] and the multiplier Y [15: 0] are obtained as a product Z [31: 0].

FIG. 2 shows a multiplier encoding means 10 shown in FIG.
FIG. 3 is a block diagram showing an internal configuration of the ０0 ’. 200 in FIG.
Indicates a circuit per encoding result. The multiplier is encoded by a second order Booth algorithm. The encoding result BEi has five values of -2, -1, 0, 1, and 2, and 1Ei indicating that the value is "1", 2Ei indicating that the value is "2", and It is expressed by 3 bits of SEi indicating a code when 1 is set. Here, NSEi is an inverted signal of SEi and is used when generating a partial product. Where i is 0, 2, 4, 6,
8, 10, 12, and 14, and Y-1 is 0.

FIG. 3 shows the first partial product generating means 1 shown in FIG.
FIG. 2 is a block diagram showing an internal configuration of the ten. 30 in FIG.
0 indicates a circuit per bit, and 301 indicates a circuit for generating a correction term. When the encoding result is positive, the multiplicand is selected as it is, and when the encoding result is negative, bit inversion of the multiplicand is selected. The composite gate outputs the selected value of each bit when the encoding result is 1 or −1, and outputs the selected value one bit lower when the encoding result is 2 or −2. In this case, 0 is output. The output of the composite gate becomes the output 1PPOn of the bit n of the generated partial product. The correction term 1PPH for two's complement is generated by taking the logical AND of the control signals NSEi, 2Ei and 1Ei. This holds when the encoding result is -1 or -2, and is output at the position of the least significant bit of the generated partial product.

FIG. 4 shows the second partial product generating means 1 in FIG.
It is a block diagram which shows the internal structure of No. 11. 30 in FIG.
0 indicates a circuit per bit, and 301 indicates a circuit for generating a correction term. When the encoding result is negative, the multiplicand is selected as it is, and when the encoding result is positive, bit inversion of the multiplicand is selected. The composite gate outputs the selected value of each bit when the encoding result is 1 or −1, and outputs the selected value one bit lower when the encoding result is 2 or −2. In this case, 0 is output. The output of the composite gate becomes the output 2PPOn of bit n of the partial product to be generated. The correction term 2PPH for two's complement is generated by taking the logical AND of each of the control signals SEi, 2Ei, and 1Ei. This holds when the encoding result is 1 or 2, and is output at the position of the least significant bit of the generated partial product.

FIG. 5 is a diagram for explaining a multiplication process in the multiplication device of FIG. In FIG. 5, a symbol having a negative line indicates that the symbol indicating data is underlined. Second partial product generating means 111
Is sign-extended to the position of the most significant bit of the partial product generated by the first partial product generating means 110, which forms a pair, and the respective correction terms are shown in FIG.
Arrange as shown. Then, it can be divided into a combination of data of which upper limit is two with a negative weight for each bit and data of which the upper limit is two with a positive weight. Here, the value “1” added to the bit 0 is a correction term necessary to take the two's complement of negative weight data when performing data conversion from redundant binary data to binary data.

FIG. 6 shows the first partial product adding means 1 in FIG.
FIG. 2 is a block diagram showing an internal configuration of the device 20; 60 in FIG.
0 is a first redundant binary adder having four data inputs and one data output, and outputs the addition result in a redundant binary representation.

FIG. 7 is a block diagram showing the internal configuration of the first redundant binary adder 600. In FIG. 7, reference numeral 700 denotes a positive / negative determination unit, 701 denotes a quasi-intermediate carry generation unit,
Reference numeral 2 denotes a quasi-intermediate sum generation unit, and 703 denotes a sum generation unit. FIG. 8 is a circuit diagram showing a detailed configuration of the first redundant binary adder 600. Here, ZSi is a sign bit of the output sum Zi, and ZAi is an absolute value bit of the output sum Zi.

FIG. 9 shows the intermediate sum and Wi, Vi, Qi in FIG.
The following shows the selection rule. The intermediate sum takes a value of -2 to +2. At this time, depending on whether the value lower by one digit does not take a positive value or a negative value, Ci and Si representing the intermediate sum are selected as shown in FIG.

FIG. 10 shows the value of the intermediate sum according to the combination of the input data.

FIG. 11 shows the Wi selection rule. The hatched area in FIG. 11 indicates that when Wi is 1, the intermediate sum is not positive. Positive / negative determination means 7 in FIG.
In the case of 00, a circuit is formed so as to satisfy the selection rule of FIG.

FIG. 12 shows the selection rule of Vi. Vi is defined by the sum of Wi and Ci. Looking at the selection rule of Vi according to FIG. 9, it can be seen that Vi takes the value "1" in the hatched area. Further, when the intermediate sum takes the value "± 1", Wi-
It can be seen that the value of 1 selects the value of Ci. The hatched area in the lower right direction indicates an area where Vi takes the value "1" when the value of Wi-1 is "1". The quasi-intermediate carry generation means 701 in FIG. 7 is formed with a circuit so as to satisfy the selection rule in FIG.

FIG. 13 shows the selection rule of Qi. Qi is defined by subtracting Si from Wi-1 which is one digit lower. As shown in FIG. 9, Si takes a value "1" or "0" when Wi-1 is 1, and takes a value "-1" or "0" when Wi-1 is 0. FIG. 13 shows the selection rule of Qi. The quasi-intermediate sum generation means 702 in FIG. 7 is configured with a circuit so as to satisfy the selection rule in FIG.

FIG. 14 shows a selection rule of the output sum. Output sum Z
i is defined as the sum of Si and one digit lower Ci-1. Here, from the definitions of Qi and Vi, Zi is Q
It can be seen that it is also obtained by subtracting i. Therefore, FIG. 14 shows the selection rule of Zi. The circuit of the sum generation means 703 in FIG. 7 is formed so as to satisfy the selection rule of FIG.

The first redundant binary adder 600 is constructed so that the circuit of the sign determining means 700, the quasi-intermediate sum generating means 701, the quasi-intermediate carry generating means 702, and the sum generating means 703 share a common part. FIG. 8 is a circuit diagram.

FIG. 15 is a block diagram showing an internal configuration of the second partial product adding means 130 in FIG. Second redundancy 2
It is configured by assembling the hexadecimal adder 900 in a tree configuration. Note that the second redundant binary adder 900 can be realized with a configuration equivalent to that shown in the first conventional example.

FIG. 16 is a block diagram showing the internal configuration of the PG generating means 150 constituting the redundant binary / binary converting means 140 in FIG. Reference numeral 1000 in FIG. 16 indicates a circuit per bit. The carry generation function G is generated by the logical product of the inversion of the sign bit lower by one bit and the absolute value bit, and the carry propagation function P is generated by the logical sum of the inversion of the sign bit lower by one bit and the absolute value bit. I have. Here, the sign bit is inverted to obtain the two's complement of the bit having a negative weight in the redundant binary number, and the correction term at that time is determined by the value “1” of bit 0 shown in FIG. It is added.

FIG. 17 is a block diagram showing the internal configuration of the final addition means 160 constituting the redundant binary / binary conversion means 140 in FIG. The final addition means 160 calculates a carry look-ahead adder (CL) from the carry generation function G and the carry propagation function P output from the PG generation means 150.
A) is used to determine the product of the multiplicand and the multiplier. FIG.
Reference numeral 1100 denotes an 8-bit CLA. FIG. 18 is a circuit diagram showing a detailed configuration of one 8-bit CLA. FIG.
1200 in 8 is a 4-bit CLA, and its circuit is shown.

As described above, by employing the multiplication device shown in FIG. 1, when the partial product is generated with respect to the first conventional example, the sign of the pair of partial products is used to calculate each bit of the other partial product. A logic circuit having signs opposite to each other is not required, so that multiplication can be speeded up and circuits corresponding to PG generation can be reduced.

FIG. 19 is a block diagram showing another example of the configuration of the multiplication device according to the present invention. In the example of FIG. 19, the first partial product adder 170 and the second partial product adder 180 are configured by a third redundant binary adder, and the third redundant binary adder has a value A redundant binary number represented by two bits of a bit having a weight of “1” and a bit having a weight of “−1” is output.

As shown in FIG. 14, Qi is a bit having a weight of "-1", and Vi-1 is a bit having a weight of "1". Therefore, the first redundancy 2 shown in FIG.
The output Vi of the quasi-intermediate carry generation means 701 of the hexadecimal adder 600 is output as a bit having a weight of the value of the upper bit of the digit "1", and the output Qi of the quasi-intermediate sum generation means 702 is output as By outputting as a bit having a weight, it is possible to realize a redundant binary expression represented by two bits, a bit having a weight of “1” and a bit having a weight of “−1”.

FIG. 20 is a block diagram showing the internal configuration of the first partial product adding means 170 in FIG. Reference numeral 1400 in FIG. 20 is a third redundant binary adder.

FIG. 21 is a block diagram showing an internal configuration of the third redundant binary adder 1400 in FIG. FIG.
FIG. 27 is a circuit diagram showing a detailed configuration of the third redundant binary adder 1400.

FIG. 23 is a block diagram showing the internal configuration of the second partial product adding means 180 in FIG. 19, and the third redundant binary adder 1400 is configured in a tree shape.

The configuration per bit of the PG generation means 150 in FIG. 19 is the same as that shown in FIG. 16, and the output Qi is input to Si-1 in FIG. 16, and the output Vi-1 is output in FIG. Ai
Should be entered.

As described above, by employing the multiplier shown in FIG. 19, the number representation conversion means can be omitted from the maximum delay path as compared with the second conventional example, and multiplication can be executed at high speed.

FIG. 24 is a block diagram showing still another example of the configuration of the multiplication device according to the present invention. The example of FIG.
Partial product adding means 190 and second partial product adding means 195
And the redundant binary adder forming the final stage of the partial product addition is a carry generation function and a carry propagation function obtained from the addition result. . From the above, the PG generation means 150 in FIG. 1 can be omitted.

As shown in FIG. 14, Qi is a bit having a weight of value "-1", and Vi-1 is a bit having a weight of value "1". Therefore, Vi-
The carry generation function Gi is generated by taking the logical product of 1 and the inverse of Qi, and Vi-1 and Qi input from the lower digit are input.
Of the carry propagator P
i can be generated.

FIG. 25 is a block diagram showing the internal configuration of the first partial product adding means 190 in FIG. In FIG. 25, reference numeral 1900 denotes a fourth redundant 2 of 4 data input and 1 data output.
A hexadecimal adder generates and outputs a carry generation function and a carry propagation function from the addition result.

FIG. 26 is a block diagram showing the internal configuration of the fourth redundant binary adder 1900 in FIG. FIG.
FIG. 27 is a circuit diagram showing a detailed configuration of the fourth redundant binary adder 1900.

FIG. 28 is a block diagram showing the internal configuration of the second partial product adding means 195 in FIG. 2200
Is a conventional redundant binary adder that generates and outputs a carry generation function and a carry propagation function from the addition result.

As described above, by employing the multiplying device shown in FIG. 24, a carry generation function and a carry propagation function are generated when the carry look-ahead adder is used for redundant binary / binary conversion of data. This eliminates the need for any means, and can increase the speed of multiplication and reduce the number of circuits corresponding to PG generation.

In each of the above examples, in order to generate a partial product, the first partial product generation means 110 selects the non-inverted multiplicand when the sign bit of the multiplier encode result is 0, and sets the sign bit. Is 1, inversion of the multiplicand is selected. Further, the second partial product generation means 111 selects inversion of the multiplicand when the sign bit of the multiplier encoding result is 0, and selects normal rotation of the multiplicand when the sign bit is 1. However, multiplier encoding means 1
Sign inversion multiplier means for inverting the sign bit of 00 and setting the sign bit to 1 when the encoding result can take a positive value, and setting the sign bit to 0 when the encoding result can take a negative value. By using this, the second partial product generating means 111 can be replaced with the first partial product generating means 110. That is, in the first partial product generating means 110, when the sign bit of the encoding result of the sign inverting multiplier encoding means is 0, the inversion of the multiplicand is selected, and when the sign bit is 1, the inversion of the multiplicand is selected. By doing so, it is possible to generate the same partial product as the partial product generated by the multiplier encoding means 100 and the second partial product generating means 111.

[0044]

As described above, according to the present invention, two partial products having the same code weight as the code of the multiplier encoding result in the partial product adding means, and a code opposite to the code of the multiplier encoding result are obtained. Since addition with two partial products having weights is performed and one redundant binary number data is output as an addition result, a means for preparing for partial product addition becomes unnecessary, and the multiplication process is speeded up. Is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a multiplication device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of multiplier encoding means in FIG. 1;

FIG. 3 is a block diagram showing an internal configuration of a first partial product generation unit in FIG.

FIG. 4 is a block diagram showing an internal configuration of a second partial product generation unit in FIG.

FIG. 5 is a diagram for explaining a multiplication process in the multiplication device of FIG. 1;

FIG. 6 is a block diagram showing an internal configuration of a first partial product adding means in FIG. 1;

FIG. 7 is a block diagram showing an internal configuration of one redundant binary adder in FIG. 6;

FIG. 8 is a circuit diagram showing a detailed configuration of a redundant binary adder of FIG. 7;

FIG. 9 is a diagram showing a selection rule of Wi, Vi, and Qi in FIG. 7;

FIG. 10 is a diagram illustrating a value of an intermediate sum according to a combination of input data.

FIG. 11 is a diagram illustrating a Wi selection rule.

FIG. 12 is a diagram illustrating a selection rule of Vi.

FIG. 13 is a diagram showing a selection rule of Qi.

FIG. 14 is a diagram illustrating a selection rule of an output sum.

FIG. 15 is a block diagram showing an internal configuration of a second partial product adding means in FIG. 1;

FIG. 16 is a block diagram showing an internal configuration of a PG generation unit in FIG.

FIG. 17 is a block diagram showing an internal configuration of a final adding means in FIG. 1;

18 is a circuit diagram showing a detailed configuration of one 8-bit CLA in FIG.

FIG. 19 is a block diagram illustrating another configuration example of the multiplication device according to the present invention.

FIG. 20 is a block diagram showing an internal configuration of a first partial product adding means in FIG. 19;

21 is a block diagram showing the internal configuration of one redundant binary adder in FIG.

FIG. 22 is a circuit diagram showing a detailed configuration of a redundant binary adder of FIG. 21.

FIG. 23 is a block diagram showing an internal configuration of a second partial product adding means in FIG. 19;

FIG. 24 is a block diagram showing still another configuration example of the multiplication device according to the present invention.

FIG. 25 is a block diagram showing an internal configuration of a first partial product adding means in FIG. 24;

26 is a block diagram showing the internal configuration of one redundant binary adder in FIG.

FIG. 27 is a circuit diagram showing a detailed configuration of a redundant binary adder of FIG. 26;

FIG. 28 is a block diagram showing an internal configuration of a second partial product adding means in FIG. 24;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Multiplier encoding means 110 First partial product generating means 111 Second partial product generating means 120 First partial product adding means 130 Second partial product adding means 140 Redundant binary / binary converting means 150 PG generating means 160 Final addition means 170 First partial product addition means 180 Second partial product addition means 190 First partial product addition means 195 Second partial product addition means 200 Multiplier encoding circuit per encoded value 300 Part per bit Product generation circuit 301 Correction term generation circuit 600 First redundant binary adder 700 Positive / negative determination means 701 Semi-intermediate carry generation means 702 Semi-intermediate sum generation means 703 Sum generation means 900 Second redundant binary adder 1000 PG per bit Generation circuit 1100 8-bit CLA 1200 4-bit CLA 1400 Third redundant binary addition 1900 4th redundant binary adder 2000 PG output means 2200 5th redundant binary adder

Claims (14)

[Claims] 1. A multiplication device for multiplying a multiplicand and a multiplier each having a plurality of digits, wherein a plurality of partial products are generated from the multiplicand and the multiplier so that each bit has a predetermined positive and negative weight. And adding two data having a positive weight and two data having a negative weight among a plurality of partial products generated by the partial product generating means, and First partial product addition means having a plurality of means for outputting binary data as an addition result; and generating and outputting a multiplication result converted from output of the first partial product addition means into binary data. A multiplication device, comprising: 2. The multiplication apparatus according to claim 1, wherein the partial product generation means includes: a multiplier encoding means for encoding the multiplier for each of a plurality of bits; and a code of an encoding result of the multiplier encoding means from the multiplicand. A first partial product generating means for generating a partial product having the same code weight as: and a partial product having a code weight opposite to the sign of the encoding result of the multiplier encoding means from the multiplicand. Second partial product generation means for generating the first partial product addition means, wherein two of the partial products generated by the first partial product generation means and the second partial product addition means, A plurality of means for performing addition with two of the partial products generated by the partial product generation means, and outputting one redundant binary data as an addition result. Serial first partial product adding means multiple redundant 2 output from
Second partial product addition means for adding binary data and outputting one redundant binary data, and converting the redundant binary data output from the second partial product addition means into binary data. A redundant binary-to-binary converting means for the multiplication. 3. The multiplication device according to claim 2, wherein the first partial product generation means is configured to output an arbitrary number of the multiplicand when an encoding result of the multiplier encoding means is any positive number other than zero. If the encoding result of the multiplier encoding means is an arbitrary negative number other than zero, a logical inversion of each bit is output for an arbitrary multiple of the multiplicand, and a two's complement number is output. A multiplication device for outputting a correction term for the least significant bit to the position of the least significant bit of the partial product, and outputting 0 to each bit when the encoding result of the multiplier encoding means is zero. 4. The multiplication apparatus according to claim 2, wherein the second partial product generation means is configured to output an arbitrary number of the multiplicand when an encoding result of the multiplier encoding means is any positive number other than zero. For the double, a logical inversion of each bit is output, and a correction term for 2's complement is output at the position of the least significant bit of the partial product. The multiplication device has a function of outputting an arbitrary multiple of the multiplicand when the number is multiplied, and outputting 0 to each bit when the encoding result of the multiplier encoding means is zero. 5. The multiplication device according to claim 2, wherein said first partial product addition means adds data having two positive weights and data having two negative weights to the same digit. A plurality of first redundant binary adders for outputting a result as a redundant binary number, wherein each of the plurality of first redundant binary adders includes two data P1 and P2 having positive weights; Positive / negative determining means for outputting a signal Wi indicating that the sum of the two data N1 and N2 having negative weights is not positive; and a sum signal Si of the result of adding the four data P1, P2, N1 and N2. And a quasi-intermediate sum generating means for outputting a signal Qi defined as the difference between the output Wi-1 of the one-digit lower sign determining means and the sum signal Si. And the carry signal Ci.
And a quasi-intermediate carry generating means for outputting a signal Vi defined as the sum of the following: The difference between the output Vi-1 of the quasi-intermediate carry generating means one digit lower and the output Qi of the quasi-intermediate sum generating means. A sum generating means for outputting the added result as a redundant binary number expressed by two bits of a sign bit and an absolute value bit. 6. The multiplication apparatus according to claim 5, wherein said second partial product addition means adds two redundant binary numbers each represented by two bits of a sign bit and an absolute value bit, and generates a sign bit. A multiplication apparatus comprising: a plurality of second redundant binary adders for outputting one redundant binary number expressed by two bits of a binary number and an absolute value bit as an addition result in a tree shape. 7. The multiplication device according to claim 6, wherein said redundant binary / binary conversion means includes: a PG generation means for generating a carry generation function and a carry propagation function for each bit from redundant binary data. And a final addition unit for generating a multiplication result to be obtained from a carry generation function and a carry propagation function output from the PG generation unit, wherein the PG generation unit includes an absolute value bit and 1 for each bit. Calculating the carry generation function by logical product of the logical inversion of the sign bit of the lower bit, and obtaining the carry propagation function by logical sum of the absolute value bit and the logical inversion of the sign bit of the lower bit for each bit. Multiplying device characterized. 8. The multiplication apparatus according to claim 2, wherein said first partial product addition means adds data having two positive weights and data having two negative weights to the same digit. A plurality of third redundant binary adders for outputting a result as a redundant binary number, wherein each of the plurality of third redundant binary adders includes two data P1 and P2 having positive weights; Positive / negative determining means for outputting a signal Wi indicating that the sum of the two data N1 and N2 having negative weights is not positive; and a sum signal Si of the result of adding the four data P1, P2, N1 and N2. And a quasi-intermediate sum generating means for outputting a signal Qi defined as the difference between the output Wi-1 of the one-digit lower sign determining means and the sum signal Si. And the carry signal Ci.
And a quasi-intermediate carry generation means for outputting a signal Vi defined as the sum of the signal Vi and the signal Qi as an addition output indicating a weight of -1. A multiplication device, characterized in that the addition output is as shown below. 9. The multiplication device according to claim 8, wherein said second partial product addition means comprises a plurality of redundant binary adders similar to said third redundant binary adder configured in a tree shape. A multiplication device characterized by the above-mentioned. 10. The multiplication apparatus according to claim 9, wherein said redundant binary / binary conversion means comprises: a PG generation means for generating a carry generation function and a carry propagation function from a redundant binary number; A final addition unit for generating a multiplication result to be obtained from a carry generation function and a carry propagation function output from the unit, wherein the PG generation unit includes a bit indicating a weight of a value “1” for each bit; The carry generation function is obtained by the logical product of the logical inversion of the bit indicating the weight of the value “−1”, and the bit indicating the weight of the value “1” and the bit indicating the weight of the value “−1” are calculated for each bit. A multiplication device for calculating the carry propagation function by a logical sum with a logical inversion. 11. A multiplication device for multiplying a multiplicand and a multiplier each having a plurality of digits, wherein a plurality of partial products are generated from the multiplicand and the multiplier such that each bit has a determined positive / negative weight. And adding two data having a positive weight and two data having a negative weight among a plurality of partial products generated by the partial product generating means, and A plurality of means for outputting binary data as an addition result, and a plurality of means for generating and outputting a carry generation function and a carry propagation function, respectively, or the number of data to be added for each digit When the upper limit is four, a first partial product addition means having only a plurality of means for generating and outputting the carry generation function and the carry propagation function; Output means for generating and outputting a multiplication result converted from the output into binary data. 12. The multiplication apparatus according to claim 11, wherein the partial product generation means includes: a multiplier encoding means for encoding the multiplier for each of a plurality of bits; and a code of an encoding result of the multiplier encoding means from the multiplicand. A first partial product generating means for generating a partial product having the same code weight as: and a partial product having a code weight opposite to the sign of the encoding result of the multiplier encoding means from the multiplicand. Second partial product generation means for generating the first partial product addition means, wherein two of the partial products generated by the first partial product generation means and the second partial product addition means, A plurality of means for performing addition with two of the partial products generated by the partial product generation means, and outputting one redundant binary data as an addition result; A plurality of means for generating and outputting a number and a carry propagation function, or when the number of data to be added at each digit is limited to four, the carry generation function and the carry propagation function Only a plurality of means for generating and outputting, the output means comprising: a plurality of redundant 2 output from the first partial product adding means;
Second partial product addition means for adding binary data and outputting a set of carry generation function and carry propagation function; output from the first partial product addition means and the second partial product addition means A multiplication device comprising: final addition means for generating and outputting a multiplication result converted into binary data from the carried carry generation function and the carry propagation function. 13. The multiplication device according to claim 12, wherein the first partial product addition means adds data having two positive weights and data having two negative weights to the same digit. A plurality of first redundant binary adders for outputting a result as a redundant binary number; adding a data having two positive weights and a data having two negative weights each; A plurality of fourth redundant binary adders for outputting a result as a function, wherein each of the plurality of first redundant binary adders includes two data P1 and P2 having a positive weight and a negative weight Positive / negative determining means for outputting a signal Wi indicating that the sum of the two data N1 and N2 having the following is not positive; and a sum signal Si and a carry signal representing the addition result of the four data P1, P2, N1 and N2. One digit lower when defined with Ci A quasi-intermediate sum generating means for outputting a signal Qi defined as the difference between the output Wi-1 of the positive / negative determining means and the sum signal Si; the output Wi of the same digit positive / negative determining means and the carry signal Ci
And a quasi-intermediate carry generating means for outputting a signal Vi defined as the sum of Sum generating means for outputting the added result obtained as a redundant binary number represented by two bits of a sign bit and an absolute value bit, wherein each of the plurality of fourth redundant binary adders includes the signal Positive / negative determining means for outputting Wi, quasi-intermediate sum generating means for outputting the signal Qi, quasi-intermediate carry generating means for outputting the signal Vi, and output Qi of the quasi-intermediate sum generating means And a logical product of the inverted signal of the quasi-intermediate carry generating means GO and the inverted product of the output Qi of the quasi-intermediate sum generating means and the quasi-intermediate one digit lower. Output V of carry generation means The logical sum of i-1 and carry propagation function PO
And a PG output means for generating the multiplying result. 14. The multiplication device according to claim 13, wherein said second partial product addition means adds two redundant binary numbers each represented by a sign bit and an absolute value bit, and generates a sign bit and an absolute value. A plurality of second redundant binary adders for outputting one redundant binary number represented by two bits of the bits as an addition result, and two redundant binary adders each represented by two bits of a sign bit and an absolute value bit A plurality of fifth redundant binary adders for adding a redundant binary number, obtaining a carry generation function and a carry propagation function from the result of the addition, and outputting the fifth redundant binary adder; A multiplication device comprising: a five-redundant binary adder configured in a tree shape; and the fifth redundant binary adder arranged at the last stage of the tree configuration.