JP2777265B2 - High radix square root arithmetic unit - Google Patents

Description

[Contents] Outline Industrial application field Conventional technology (FIGS. 3 and 4) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Embodiment (FIG. 2) Effects of the Invention [Overview] A high radix square root arithmetic unit is intended to enable high-speed square root arithmetic processing. In a high-radix square root arithmetic device that performs high-radix square root arithmetic processing using a subtraction shift type square root method, a register that stores the approximate value a of the answer, a register that stores the residual R, and an approximate value a and A partial quotient predictor that inputs a residual R and obtains a predicted value r by partial quotient prediction; an adder that inputs an approximate value a and the calculated predicted value r and performs an addition process to obtain a new approximate value; R, approximate value a and the calculated prediction value r are input, and a residue calculation unit for calculating and calculating a new residue is provided. One addition, one partial quotient prediction, and one machine cycle of the residue calculation unit are performed. , N (n ≧ 2) bits of the square root.

[Industrial applications]

The present invention relates to a high radix square root arithmetic unit, and more particularly, to a high radix square root arithmetic unit used in a digital computer, and more particularly, to a high-speed square root calculation.

[Conventional technology]

FIG. 3 is a block diagram of the conventional example, and FIG. 4 is a processing flowchart of the conventional example. In the figure, 1 is a selector, 2 and 3 are registers, 4 is a CSA (carry-save adder), and 5 is an adder. The processing numbers in FIG. 4 are shown in parentheses.

2. Description of the Related Art Conventionally, in a digital computer, a square root operation is a basic operation, and is frequently used in technical calculations.

Among the above square root operations, the basic algorithm of the subtraction shift type square root method used conventionally is as follows.

Now, it is assumed that a square root of a positive number X represented by a binary number is to be obtained. In this case, with an appropriate shift, 1 ≦ X <
4 is set.

Here, first, A = 1 unconditionally as an approximation of the first one bit of. At this time, a ² ≦ X <(a + 1) ² (1) holds.

Also, it is defined residual R as X-a ^2.

Next, an approximate value a of K bits is obtained, and the equation (1) is obtained.
When is composed, obtaining the residual R ₁ which in the following manner corresponding to the approximate value a ₁ of K + 1 bits. However, it is the same even if the square root of 4X is obtained instead of X, so it is considered here. That is, obtaining the a ₁ satisfying ^{_{a 1 2 ≦ 4X <(a}} 1 +1) 2. Equation (1)
More, ^(2a) from ^{2 ≦ 4X <(2a + 2} ) 2 ...... (2) is made up, as a way of taking a _1, R _1, if ^{4X <(2a + 1) 2} , a 1 = 2a, R 1 Assuming that (2a + 1) ² ≦ 4X, a ₁ = 2a + 1 and R ₁ = 4X− (2a + 1) ² = 4R−4a−1. A square root is obtained by repeatedly performing the above processing.

Processing based on the above algorithm is performed as follows.

The processing device includes a selector 1, registers 2, 3, CSA4, and an adder 5, as shown in FIG. The selector 1 uses the code output from the adder 5 as a select signal, and selects either 4R or 4R-4a-1. The register 2 is a register for storing the residual R, and the register 3 is a register for storing the approximate value a.

No. processing by the processing device, as shown in FIG. 4, first, an a = 1, R = X- a 2 (100).

Then, if the ^{4X <(2a + 1) 2} , (101), a 1 = 2
a, and R ₁ = 4R (102), but if 4X (2a + ^{1) 2} if _{(101), a 1 = 2a} + 1, R 1 = 4X- (2a + 1) 2 = 4R-4a
-1 (103).

When such processes (101) to (103) are repeated m times,
The square root of m bits is obtained.

[Problems to be solved by the invention]

The prior art as described above has the following disadvantages.

That is, the main operation of the processes (101) to (103) shown in the above conventional example is to find 4R-4a-1.

Since this can be realized by one subtraction and one CSA stage in hardware, it can be easily accommodated in one common machine cycle. However, since only one bit can be obtained in one cycle, there is a disadvantage that the square root calculation processing is slow.

SUMMARY OF THE INVENTION It is an object of the present invention to solve such a conventional disadvantage and to enable a square root arithmetic processing to be performed at high speed.

[Means for solving the problem]

FIG. 1 is a diagram showing the principle of the present invention. In the drawing, reference numerals 10 and 11 denote registers, 12 denotes a partial quotient predictor, 13 denotes a residual calculator, and 14 denotes an adder.

In order to achieve the above object, the present invention performs high radix square root arithmetic processing using a subtraction shift type square root method in which the lower bits are sequentially obtained by repeating addition, subtraction and shift starting from the most significant bit. In a high radix square root arithmetic device, a register 10 for entering an approximate value a of a response, a register 11 for entering a residual R, and a partial quotient estimator for inputting the approximate value a and the residual R to obtain a predicted value r by partial quotient prediction 12 and the above approximate value a and the predicted value r are input to perform addition processing to obtain a new approximate value. , And the residual R, the approximate value a, and the calculated predicted value r, and a new residual And a residual calculation unit 13 for calculating the following is obtained. One addition, one partial quotient prediction, and n (n ≧ 2) bits of the square root are obtained in one machine cycle of the residual calculation unit 13. (However, N = 2 ⁿ ).

[Action]

Since the present invention is configured as described above, the following operation is provided.

First, as preprocessing, an approximate value a and a residual R of the answer are obtained, and the respective values are stored in the registers 10 and 11.

Next, as the main process, the following processes (1) to (3) are performed by m
Repeat several times.

(1) The approximate value a in the register 10 and the residual R in the register 11 are input to the partial quotient predictor 12 to obtain a predicted value r.

(2) The residual R in the register 11, the approximate value a in the register 10, and the predicted value r obtained by the partial quotient predictor 12 are input to the residual calculator 13, and a new residual , And the residual R in the register 11 is updated.

(3) The approximate value a in the register 10 and the partial quotient predictor
The predicted value r obtained in step 12 is input to the adder 14, and a new approximate value To update the approximate value a in the register 10.

By doing so, the processing of the above (1) and (3) becomes 1
And n times (n ≧ 2) bits of the square root in one machine cycle of the processing of (2). Therefore, the square root process can be sped up.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention, in which:
The same reference numerals as those in FIG. 1 denote the same components. Reference numeral 15 denotes a squarer, reference numerals 16 to 18 denote CSAs (carry save adders), and reference numeral 19 denotes a CPA (carry propagation adders).

In this example, the residual calculation unit 13 is configured by a squarer 15, three-stage CSAs 16 to 18, and a CPA 19, and the adder 14
Use A. Then, the square root arithmetic processing of a high radix is performed by the subtraction shift type square root method, which will be described in detail below.

In the square root extraction processing, n bits (n ≧
In order to obtain the result of 2), the following is performed. Now, ^assuming N = ²ⁿ , Is obtained with an accuracy 1 / N ^K (where K is
Indicates the number of digits of the approximate value a in N-ary). That is, Is satisfied. Approximation accuracy 1 / N ^K from the a I want to ask.

That is, I want to find an integer r such that

At this time, from equation (3), there should be a solution in the range of -N + 1 ≦ r ≦ N−1.

The residual R _k is _defined as N ^K (X−a ² ). Equation (3)
More, it is ^{-2a + 1 / N K <R} K <2a + 1 / N K.

Next, when equation (4) is transformed, Becomes Where | r | <N, Holds, equation (5) also holds.

By transforming equation (6), Now, assuming that 2aN ^K-1 is known to be greater than or equal to a certain constant C, If r is found that satisfies, then the above equation (7) holds, and the above equation (5) also holds. Therefore, it means that Motoma' approximate value a _1. At this time, the new residual R _{K + 1} is R which satisfies the above equation (8) can be obtained by the number of logic stages that can be sufficiently accommodated in one machine cycle by using a partial quotient prediction technique well known in a high radix non-restoring division circuit.

To summarize the above, the algorithm is as follows.

After applying an appropriate shift in the X, next a ≧ a _0, and obtains the a that satisfies equation (3). R = N ^K (X-
a ² )

R that satisfies the above equation (8) is obtained by partial quotient prediction, When this operation is repeated m times, an approximate expression of mn bits is obtained.

Regarding the updating of a in the _equation , a> a ₀ −1 is satisfied no matter how many times the updating is performed. Therefore, the partial quotient prediction may be performed by setting C = 2a ₀ N ^{K−1 in} the above equation (8).

In the operation of multiplying r, r is at most n bits,
It can be done with the number of CSA stages and adders. Further, since 1 / N times is equivalent to n-bit right shift, a circuit is not particularly required.

FIG. 2 shows a case where n = 2. First, after shifting X so that 64 ≦ X <256, an initial prediction based on Table 1 is performed.
Can be put in.

The prediction in Table 1 is such that (a-1) ² <X <(a + 1) ² . a ₀ = 8, C = 4, K = 0.
The above equation (8) is Becomes

Also, the residual R ₀ = X−a ² is stored in the register 11.

The data in the register 10 is unsigned and the integer part is 4 bits, and the data in the register 11 is signed and the integer part is 6 bits including a sign.

In this case, partial quotient prediction can be performed only with the integer part of R and a. The integer part R, When a, 2 R ≦ 2R <2 R +
2. Since a ≦ a < a + 1, the sufficient condition of the expression (9) is It is.

Table 2 shows that r satisfying the equation (10) is obtained for all a and R.

For each cycle, first, from the upper bits of R and a,
Is performed based on the partial quotient. The result r is here three signed bits. Also, it is put into the squarer 15 in order to obtain r ² . Further, each bit of r is -4 times a, 2
Multiplied by 1 times, and finally R, r ² , -4ar ₂ , 2ar ₁ , ar
o are added (after each being properly shifted) into register R.

〔The invention's effect〕

As described above, according to the present invention, one addition, one partial quotient prediction, and obtaining a square root n (n ≧ 2) bits in one machine cycle including about several stages of CSA Therefore, there is an effect that high-radix square root extraction processing can be performed at high speed.

[Brief description of the drawings]

 FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a processing flowchart of a conventional example. 10, 11 Register 12 Partial quotient predictor 13 Residual calculator 14 Adder

Claims (1)

(57) [Claims] 1. A high radix square root arithmetic device for performing a high radix square root arithmetic process using a subtraction shift type square root method in which lower bits are sequentially obtained by repeating addition, subtraction and shift starting from the most significant bit. A register (10) for storing the approximate value a of the answer, a register (11) for storing the residual R, and a partial quotient predictor (12) for inputting the approximate value a and the residual R to obtain a predicted value r by partial quotient prediction. ), And an adder (14) for inputting the approximate value a and the calculated predicted value r and performing an addition process to obtain a new approximate value (a ₁ = a + r / N ^{K + 1} ); Input the approximate value a and the obtained predicted value r,
A residual calculation unit (13) for calculating and calculating a new residual (R ₁ = RN−2ar−r ² / N ^{K + 1} ) is provided. One addition, one partial quotient prediction, and residual calculation Department (13)
A high-radix square root arithmetic device, wherein n (n ≧ 2) bits of a square root are obtained in one machine cycle of (1).