JP2645422B2 - Floating point processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A floating-point arithmetic processing device, in particular, an arithmetic circuit that performs square root extraction.
Floating-point arithmetic processing unit for realizing high-speed square root arithmetic processing, wherein an integer multiplier, a right shift circuit, and a rounding circuit are used to obtain a multiplied value of two mantissa parts of a binary number to be multiplied. A bit inversion circuit and a multiplexer are provided between the right shift circuit and the rounding circuit, and an output of the bit inversion circuit is supplied to the rounding circuit via the multiplexer only during a part of the square root operation. Then, "1" is added to the least significant digit, and the result is shifted right by one bit, so that the output of the right shift circuit is supplied to the rounding circuit via the multiplexer except for the operation described above.

[Industrial applications]

The present invention relates to a floating-point arithmetic processing device, and more particularly, to an arithmetic circuit that performs square root extraction on a numerical value in floating-point notation. Floating-point arithmetic has a wider dynamic range and higher precision than integer (fixed-point) arithmetic. Above all, high-speed processing related to Kaiping has become important.

[Conventional technology]

In general, as the square root method, not only the floating point method but also a method using a convergence method (for example, Newton-Raphson method) is known. To find the square root of number B, And multiply it by B Is obtained by the convergence calculation by the Newton-Raphson method, the number of repetitions required for convergence decreases as the initial value of the reciprocal is closer to the true value.

Many floating-point arithmetic processing devices that are currently announced perform square rooting using the Newton-Raphson method. In the Newton-Raphson method, if an initial value of the reciprocal is given within a certain precision, a convergence value can be obtained by about three to four convergence calculations. Therefore, square rooting by the Newton-Raphson method can be performed at high speed.

The square root using the Newton-Raphson method will be described. To perform square root, first find the inverse function. For example, Can be expressed in the form of a reciprocal. Using the Newton-Raphson method to obtain an iterative representation of the inverse function gives:

X _{i + 1} = 1/2 * X _i (3-BX _i ² ) where X _{0 for} i = ₀ is the first X _i is the first approximation. Sign *
Is a symbol of multiplication. Initial value X ₀ is inequality When the condition is satisfied, the multiplication ends. A typical method for obtaining the initial value uses the upper 10 bits of B as a pointer of a look-up table (a ROM or the like is used), and the ROM outputs the contents of the address indicated by the value of B as the initial value.
Usually, the number of output bits is almost the same as the number of input bits. Generally, in the case of the square root of the floating point, the reciprocals of the exponent part and the mantissa part are obtained from different lookup tables.

FIG. 4 shows a conventional floating point arithmetic processing unit (multiplier). Floating-point numbers input from two inputs (input 1 and input 2) are expressed as (-1) ^Sa 2 ^Ea-bias (1.Fa) and (−
1) ^Sb 2 ^Eb-bias (1.Fb). This floating point multiplier handles only normalized numbers. The mantissas (1.Fa) and (1.
Fb) is an integer (fixed-point) multiplier (1.Fa) ×
(1.Fb) is executed. The result is 1.xxxx…, or
1x.xxxx ... 1.xxxx ... is already normalized. In the case of 1x.xxxx ..., normalization processing is required. That is, the right shift circuit 5 performs a right shift by one bit. At this time, the exponent part needs to be incremented by one.

Next, a rounding process is performed to match the normalized numerical value to the output data format. Round circuit 12 in rounding circuit 6
Then, the digits below the LSB (minimum digit) in the output data format are rounded down, and it is determined whether or not “1” is added to the LSB according to the rounding mode. Then, the operation of adding “1” to the LSB is executed by the integrator (incrementer) 11. At this time, if the data is all "1", an overflow occurs. In this case, the right shift circuit 13
Bits are shifted right and the final output is a normalized number.

The operation of the exponent will be described. The calculation of the exponent is performed on the left side of the vertical chain line in the figure. 1st stage adder
At 21 Ea + Eb is executed, and the adder 22 at the second stage adds -bias to the result. Therefore, Ea + Eb−bias is calculated by these two adders. Third stage integrator
In 23, when the overflow is corrected by the normalization process, +1 is added. Further, in the integrator 24 at the fourth stage, +1 addition is performed in advance for overflow correction by rounding, and one of them is selected by the multiplexer (MUX) 25 based on the overflow signal V. The calculation of the sign is performed by the exclusive OR of Sa and Sb.

In a conventional floating-point multiplier as shown in FIG.
It can not be the calculation of 2-BX _i, in order to perform the calculation of the 2-BX _i, when using conventional floating-point multiplier, other requires an adder.

[Problems to be solved by the invention]

As described above, iterative calculation of X _{i + 1} = 1/2 * X _i (3-BX _i ² ) is performed by multiplication: B * X _i (hereinafter, referred to as A) multiplication: A * X _i subtraction: 3 − (A * X _i ) Multiplication: X _i * (3- (A * X _i )) Multiplication: Five arithmetic operations of 1/2 * (X _i * (3- (A * X _i ))) are required However, there has been a problem that the entire arithmetic processing time is long and it is difficult to meet the demand for higher speed.

An object of the present invention is to speed up the above iterative calculation by simple improvement in a floating-point arithmetic processing device, and to realize high-speed square root arithmetic processing.

[Means for solving the problem]

In the present invention, as shown in FIG. 1, two mantissa parts of a binary number to be multiplied are multiplied by an integer (fixed point) multiplier 20, and the multiplied value corresponds to the value of the most significant bit. The data is supplied to a rounding circuit 6 through a right shift circuit 5 for right-shifting the data by one bit, and a floating-point arithmetic processing device that obtains a binary mantissa multiplied by the output of the rounding circuit 6 is further provided with a bit inversion circuit 7 And a multiplexer 8.
The bit inversion circuit 7 and the multiplexer 8 are provided between the right shift circuit 5 and the rounding circuit 6, and the bit inversion circuit 7 sets a binary number "10" to a digit above the decimal point and a digit below the decimal point. Is inverted. The multiplexer 8 supplies the output of the bit inversion circuit 7 to the rounding circuit 6 only during a part of the square root operation. Then, the output of the bit inversion circuit 7 is added with "1" to the least significant digit in the rounding circuit,
Shifted one bit to the right. At the time other than the operation, the output of the right shift circuit 5 is directly supplied to the rounding circuit 6 via the multiplexer 8.

In another embodiment of the present invention, as exemplified with reference to FIGS. 1 and 2, two mantissa parts of a binary number to be multiplied are multiplied by an integer (fixed-point) multiplier 20, and the multiplication is performed. The value is supplied to a rounding circuit 36 via a right shift circuit 5 for shifting the value to the right by one bit in accordance with the value of the most significant bit.
A floating point arithmetic processing unit which can obtain a mantissa of a binary number multiplied by the output of 36 is further provided with a bit inversion circuit 37 and a multiplexer 8. The bit inverting circuit 37 and the multiplexer 8 are provided between the right shift circuit 5 and the rounding circuit 36, and the bit inverting circuit 37 inverts the bits of the input numerical value below the decimal point and sets the bit higher than the decimal point to "0". "
To The multiplexer 8 supplies the output of the bit inversion circuit 37 to the rounding circuit 36 only during a part of the square root operation. Then, the output of the bit inverting circuit 37 is added with "1" to the least significant digit in the rounding circuit, shifted right by one bit, and set to "1" at the most significant digit. At times other than the operation, the output of the right shift circuit 5 is directly supplied to the rounding circuit 36 via the multiplexer 8.

(Operation)

If the above-described device is used, in an arithmetic processing device that performs floating-point multiplication, only the bit inverting circuit 7 or 37 and the multiplexer 8 are added, and 1/2 * (3-AX _i ) (where 0 <AX _i ≦ The binary calculation of 1) can be executed in one step using an arithmetic processing device capable of floating point multiplication, and the iterative calculation required for the square root operation can be speeded up.

〔Example〕

Prior to the description of the embodiments, first, the principle of the present invention will be described.

IEEE floating-point data format
The operation of the mantissa part of the square root of the normalized number (1 ≦ B <2) will be described. If C is the square root, X _{i + 1} can be expressed as X _{i + 1} = 1/2 * X _i (3-) BX _i ² ). However, B> 0.

Here, the initial value X ₀ is determined by a look-up table (ROM). When 0 <AX ₀ ≦ 1 (where A = BX ₀ ), 2 ≦ (3-AX ₀ ) <3, so 1 ≦ 1/2 * (3-AX ₀ )
<3/2, and 1/2 * (3-AX _i ) is also a normalized number. Therefore, in general, 1/2 * (3-AX ₀ ) is a normalized number. next
Consider the calculation of 1/2 * (3-AX _i ). 0 <AX _i ≦ _I than AX _i
Assuming that the bit inversion below the decimal point is ▲ ▼, (3
−AX _i ) d = (10. ▲ ▼ + LSB (1)) b Here, 1 is added to LSB (1): LSB (minimum digit),
() D means decimal, () b means binary. Further, by shifting the obtained (10. ▲ ▼ + LSB (1)) b by one bit to the right, 1/2 * (3-AX _i ) necessary for square root using the Newton-Raphson method, where (0 <AX _i
<1) can be performed. As described above, the above-described five repetitive calculations are simplified as follows.

Multiplication: B * X _i, computation according to the invention this is = the A: 1/2 * (3 -A * X i) _{multiplying: X i * (1/2} * (3-A * X i)) This Thus, it can be executed with only three arithmetic operations.

FIG. 1 is a circuit diagram of a floating-point arithmetic processing device according to an embodiment of the present invention. This apparatus is divided into right and left parts by the center chain line in FIG. 1. On the left side, the operation on the exponent is performed using adders 21 and 22, integrators (incrementers) 23 and 24, and a multiplexer 25. The exponent calculation part is the same as that of the conventional calculation processing device, and thus the description is omitted. The sign determination circuit is the same as the conventional one.

The arithmetic circuit of the mantissa is shown on the right side of the center chain line in FIG. Two inputs to be multiplied (input 1 and input 2)
Is output by an integer (fixed-point) multiplier as data indicated by a dashed block. The most significant digit V is supplied to the integrator 23 in the exponent operation and shifts the right shift circuit 5 by one bit. The output of the integer multiplier 20 is supplied to the right shift circuit 5. The output of the right shift circuit 5 is supplied to a bit inversion circuit 7 and a multiplexer 8 newly provided according to the present invention. The bit inversion circuit 7 inverts the bits of the input data in the lower digit than the decimal point, and outputs a numerical value in which the upper bit is “10”, that is, data “10.

The calculation of 1/2 * (3-A * X _i ) will be described below. Since the output AX _i from the integer multiplier 20 is 0 <AX _i ≦ 1, the overflow bit V is 0. Right shift circuit 5
The data after passing is 1.0000 ... 0 or 0.xxxx ...
These are 10.000 ... 10.111 by the bit inversion circuit 7.
1 .., 0.xxx becomes 10 .... Here is the inverted value of x. The multiplexer 8 selects an output from the bit inversion circuit 7 by a control signal (square root) given at the time of a part of the square root calculation, that is, at the time of the calculation of 1/2 * (3-A * X _i ). When there is no signal, the output of the right shift circuit 5 is supplied to an integrator 11 which is an element of the rounding circuit 6. When the square root control signal is given, the integrator 11 further adds "1" to the LSB. The output of the integrator 11 outputs a mantissa output via another right shift circuit 13. The rounding circuit 6 includes an integrator 11, a right shift circuit 13 and a round circuit 12, and receives an output of the multiplexer 8 and outputs an output in the rounding mode.
11 to round the arithmetic output.

When the most significant digit V is "1" in the integrator 11, a signal is sent to the exponent part multiplexer 25, the output from the integrator 23 is selected, and the right shift circuit 13 shifts right by one bit. When Unexamined control overflow bits (i.e. 2 ¹ digit) is 1-bit right shift because it is "1".

Therefore, until the output of the integrator 11 described above, 3-A * X _i operation is performed, it is 1/2 by right shift circuit 13, eventually 1
The calculation of / 2 * (3-AX _i ) is performed in one step (where 0 <AX _i ≦ 1).

A modification of the above embodiment will be described with reference to FIGS. FIG. 2 shows a partial circuit diagram of a modification. That is, a circuit diagram of the right shift circuit 5 and the subsequent circuits in the mantissa operation circuit is shown. The other circuits are the same as the circuits in FIG.

In this circuit, a bit inversion circuit 37 is used in place of the bit inversion circuit 7. In the bit inversion circuit 7, the bit of the lower digit than the decimal point is inverted, and the upper bit is set to “10”. However, in the bit inversion circuit 37, the upper bit is set to “0”. In a modification, a right shift circuit 33 is used instead of the right shift circuit 13. Details of the right shift circuit 33 are shown in FIG. This circuit uses the control signal S
Is "1", the left input of each multiplexer 41 is selected, and if "0", the right input is selected. When the control signal S is “1”, the input of the most significant digit (MSB) is “1”.
Is set. The control signal S is 1/2 in square root operation
* (3-A * X _i ) [where 0 <AX _i ≦ 1] is controlled to be “1”.

〔The invention's effect〕

According to the present invention, by adding a simple circuit in the floating-point arithmetic processing device, the iterative calculation required for the square root calculation can be speeded up, and the square root arithmetic processing can be speeded up.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a floating-point arithmetic processing device as one embodiment of the present invention, FIG. 2 is a partial circuit diagram showing a modification of the embodiment of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a right shift circuit, and FIG. 4 is a circuit diagram of a conventional floating point arithmetic processing device. In the figure, 5 ... right shift circuit, 6 ... rounding circuit, 7 ... bit inversion circuit, 8 ... multiplexer, 11 ... integrator, 12 ... round circuit, 13 ... right shift circuit, 20 ... Integer multiplier, 21,22 Adder, 23,24 Integrator, 25 Multiplexer, 33 Right shift circuit, 36 Rounding circuit, 37 Bit inverting circuit, 41 Multiplexer It is.

Claims (2)

(57) [Claims] 1. A mantissa part of two binary numbers to be multiplied is multiplied by an integer multiplier (20) which is a fixed-point multiplier, and the multiplied value is shifted right by one bit corresponding to the value of the most significant bit. A floating-point arithmetic processing unit which supplies a mantissa part of a binary number which is supplied to a rounding circuit (6) via a right shift circuit (5) and is multiplied by an output of the rounding circuit (6). A binary number "10" is set in a digit above the decimal point between the circuit (5) and the rounding circuit (6), and a bit inverting circuit (7) for inverting a digit below the decimal point and a multiplexer (8) are provided. Only during a part of the square root operation, the output of the bit inversion circuit (7) is output from the multiplexer (8).
Is supplied to the rounding circuit (6), and the least significant digit is "1".
Is added and shifted by one bit to the right, and when the operation is not performed, a floating-point data is output from the right shift circuit (5) to the rounding circuit (6) via the multiplexer (8). Arithmetic processing unit. 2. The multiplication of two mantissa parts of a binary number to be multiplied by an integer multiplier (20), which is a fixed-point multiplier, and right-shifts the multiplied value by one bit corresponding to the value of the most significant bit. A right-point shift circuit (5), which is supplied to a rounding circuit (36) to obtain a binary mantissa multiplied by an output of the rounding circuit (36); Between the circuit (5) and the rounding circuit (36), a bit inverting circuit (37) and a multiplexer (8) for inverting bits below the decimal point of the applied numerical value to set a bit higher than the decimal point to "0" are provided. Only during a part of the square root operation, the output of the bit inversion circuit (37) is supplied to the rounding circuit (36) via the multiplexer (8), "1" is added to the least significant digit, and 1 bit is added. Right shift is performed and the highest digit is set to “1”. When other than a floating point processing unit output of said right shift circuit (5) is to be supplied to the round Me circuit (36) via the multiplexer (8).