JP2000010763A - Division circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify scaling to quickly generate a quotient in a division circuit which adopts a high-base subtraction shift system, where scaling of a divisor is performed, and the redundant binary representation for a partial remainder. SOLUTION: Multiple generation circuits 2 to 9 generate 1/2 to 1/8 and -1/8 multiples of a divisor and a dividend, and scaling of the divisor and the dividend is performed by multiple selection circuits 15 and 17 and multiple generator and address 16 and 18 in accordance with a multiplication coefficient generated by a multiplication coefficient generation circuit 1, and results are preserved in a divisor register 20 and a dividend register 22, and a 2's complement conversion circuit generates upper 5 bits of a partial remainder converted to a 2's complement, and a quotient generation circuit 24 refers to upper 4 bits out of 5 bits to determine a quotient, and a divisor multiple generation circuit 25 generates multiples of the divisor, and the partial remainder in the next cycle is generated by a partial remainder generation redundant binary adder/ subtractor 26. The quotient generated by the quotient generation circuit 24 is preserved in a quotient register 27, and the quotient is converted to a 2' complement by a complement conversion adder to obtain the final quotient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a division circuit,
In particular, it relates to a high radix type digital divider.

[0002]

2. Description of the Related Art Conventionally, this kind of division circuit is, for example, "1".
It is described in a paper by Miura et al. Entitled "Configuration of a radix-4 divider without using a quotient selection table" published on page 154 of the 998 IEICE General Conference Proceedings, Electronics [2]. Thus, the high radix type divider is used as a means for mounting on an LSI.

In the implementation of a divider, a division algorithm called a "subtraction shift method" or a "subtraction separation method" is generally used because of a good balance between the hardware amount and the performance. This division algorithm is a method of performing division by determining a quotient, shifting a remainder (partial remainder), and subtracting a multiple of a denominator (divisor) from the remainder, similarly to performing division by handwriting. Such a division algorithm is described in, for example, “High-speed Computer Operation System, 1980, Kindai Kagaku, pp. 21
4-249 "includes recovery type division, non-recovery type division, SRT
Various division techniques such as division and extended SRT division are described.

[0004] First, a general procedure of division using the subtraction shift method will be briefly described. The bit length of the operation is n
(Arbitrary positive integer), the radix of the operation is r, the divisor is D, the dividend is R (0), j is an integer of 0 or more, the jth partial remainder is R (j), and the jth quotient is q ( j). Here, it is assumed that the divisor D and the dividend R (0) are normalized.

[0005] Here, as the floating point normalization format, 1. xxxx is used, and the divisor and the dividend are both normalized. Even when a data format that does not conform to this format is handled, such a process for the floating-point format can be applied by executing an appropriate shift process before and after the operation.

The quotient and partial remainder used here are represented by a redundant binary expression. That is, in the two's complement representation, where each bit is represented by {0, 1}, it is allowed to take three values of {-1, 0, 1}, and a negative bit is made possible.

Under the condition that the input data is normalized as described above, a quotient and a partial remainder can be sequentially obtained by using a recurrence formula shown in the following formula (1).

R (j + 1) = r × R (j) −q (j + 1) × D (1)

At this time, the quotient q (j + 1) is selected from a set of digits defined by the radix r so as to satisfy the following condition.

0 ≦ | R (j + 1) | <k × D (2)

Here, k is a constant satisfying the following equation (3).

K = m / (r-1) (3)

In the above equation (3), m is a digit having the largest absolute value in a digit set in a radix r number system. In this case, since the minimum value of m is ×× r and the maximum value is r−1, the range of k is as shown in the following equation (4).

1/2 ≦ k <1 (4)

For example, taking a radix-4 number system as an example, digit sets are {-3, -2, -1, 0, 1, 2, 3} and {-2, -1, 0, 1, 2}. There are two possibilities. For the former, k = 1, and for the latter, k = ２. The fact that the value of k becomes smaller means that the value range of the partial remainder in the middle of the calculation is narrower than the expression (2). That is, in the latter case, since the triple cannot be selected as a multiple of the divisor, the range of the partial remainder in the middle of the calculation is restricted so that the division can be performed up to twice the divisor.

In the case of the radix-2 number system, the digit set is only {-1, 0, 1}, which corresponds to the case where k = 1.

When the quotient is obtained by the above equation (1), the number of bits of the quotient obtained by one division is log (2r). Therefore, the desired number of bits can be obtained by repeating the division n / log (2r) times. Quotient can be obtained.

The above-described division algorithm is described in "P-
It can be summarized in a graph called a "D plot". FIG. 4 shows a PD plot of the above-mentioned division algorithm. In FIG. 4, the abscissa indicates the divisor, and the ordinate indicates the partial remainder multiplied by the radix (hereinafter the shifted partial remainder). However, since the PD plot is on the x-axis, only the positive range on the y-axis is shown. When the algorithm represented by the PD plot is implemented, the quotient is determined by referring to the upper 2 bits of the divisor D excluding the MSB (most significant bit) and the upper 5 bits of the shifted partial remainder. Can be. Since the MSB of the divisor is guaranteed to be 1 by normalization, there is no need to refer to it. In this case, since the reference bit of the divisor is 2 bits, it can be divided into four sections according to the range of the divisor. In each section, the value of the upper 5 bits in the complement representation of the shifted partial remainder is expressed as One quotient value can be associated with it.

A set of the upper 2 bits of the divisor (excluding the MSB) and the upper 5 bits of the 2's complement of the shifted partial remainder represent values in a certain range on the PD plot. Assuming that the upper 2 bits (excluding the MSB) of the divisor are Dt, the true divisor D exists in the following range.

1 + Dt ≦ D <1 + Dt + ／ (5)

Further, assuming that the higher-order 5 bits of the two-complement number of the shifted partial remainder are Rt (j), the value rR (j) on the true shifted portion exists in the following range.

Rt (j) − ／ <rR (j) <Rt (j) + ／ (6)

Since the partial remainder takes a redundant binary representation, Rt
There is a possibility that a true value exists in a region in the negative direction with respect to (j).

A rectangular area on the P-D plot represented by the above equations (5) and (6) is a range where a true divisor and a partial remainder exist, and will be hereinafter referred to as an "uncertain area". It is necessary to determine the quotient so that the above equation (2) is satisfied for all the values in the uncertain region. That is, for example, when 3 is selected as the quotient, from the above equations (1) and (2), rR
From the straight line represented by (j) = 4D, a straight line represented by rR (j) = 2D is a region where 3 can be selected as a quotient,
Only when all the uncertain regions fall within this range, 3 can be selected.

In general, increasing the uncertainty area means reducing the number of bits of the divisor and the partial remainder to be referred to, and can simplify the logic for determining the quotient. Therefore, it is important to select the largest uncertainty area while satisfying the above equations (1) and (2). Prior to the determination of the quotient, the reference bits necessary for the quotient determination of the shifted partial remainder need to be converted from redundant binary numbers to two's complement representation.

In the division algorithm described above,
It is necessary to determine the uncertainty area with reference to the next 2 bits of the MSB of the divisor D and the upper 5 bits of the shifted partial remainder. At this time, the divisor and the dividend are multiplied by the same coefficient before the operation,
For example, if the coefficient is selected so that the divisor always falls within the range of 1.00 to 1.25, the divisor is set to 2 when determining the quotient.
There is no need to refer to bits. Also, due to the nature of division,
It will be obvious that even if the divisor and the partial remainder are multiplied by the same coefficient before the operation, the obtained quotient does not change.

The method of speeding up division by multiplying by an appropriately selected coefficient (hereinafter referred to as a multiplication coefficient) before the start of division is called "scaling". Is being developed.

That is, scaling as shown in the following table is performed, and the divisor is scaled in the range of 1.75 ≦ divisor <2.00.

[0029]

[Table 1]

To identify the range of the above divisor, the MSB
May be referred to the upper 3 bits of the divisor excluding. Since the MSB of the divisor is guaranteed to be 1 by normalization, there is no need to refer to it. As a result, the divisor is 1.
It is scaled in the range of 75 ≦ divisor <2.0. FIG. 5 shows a PD plot in this case. Not only does the divisor need not be referred to, but also the uncertainty region can be doubled in the y direction compared to the case where no scaling is performed,
The reference bits of the shifted partial remainder can be set to the upper 4 bits of the two's complement number. Further, the multiplication itself can be realized by shifting and adding, as shown in the combination of multiples for realizing the multiplication. Although it is necessary to add up to four types of multiples, this can be generated by combining a carry save adder or the like with a normal two-input carry propagation adder.

Next, the conventional division circuit will be described with reference to the drawings. FIG. 3 is a block diagram showing an example of a configuration of a conventional division circuit. In this example, the radix of the operation is 4, and the digit set is ｛-3, -2, -1, 0, 1, 2, 2,.
3}, a case where the divisor and the dividend are n-bit length decimal numbers and the division is performed using the extended SRT division algorithm as the operation algorithm will be described.

In FIG. 3, reference numeral 101 denotes a multiplication coefficient generation circuit for generating a multiplication coefficient used for scaling.
Reference numerals 2 to 106 and 107 to 111 denote shift circuits for respectively generating 除, ４, ８, 1/16, and 1/64 multiples of the divisor and the dividend, and 115 and 117 denote multiplication coefficients, respectively. Is a multiple selection circuit that selects a divisor and a multiple of the dividend according to the above and compresses the multiple into two in the carry save adder, and 116 and 118 are final scaled divisors by the carry propagation adder, respectively. A multiple generation adder for generating a dividend. Reference numeral 120 denotes a divisor register for storing the divisor; 122, a partial remainder register;
1 is a selector for selecting either the partial remainder or the input dividend. Reference numeral 123 denotes a two's complement conversion circuit for converting the upper bits of the partial remainder necessary for quotient determination into two's complement numbers.
Is a quotient generation circuit that generates a quotient based on the output of the two's complement conversion circuit 123; 125 is a divisor multiple generation circuit that selects a multiple of the divisor according to the output of the quotient generation circuit 124;
Is a partial remainder generation redundant binary addition / subtraction circuit for generating the next partial remainder from the output of the divisor multiple generation circuit 125 and the output of the partial remainder register. A quotient register 127 stores the output of the quotient generation circuit 124, and a quotient two-complement adder 128 performs two-complement quotient of the quotient.

Next, the operation of this conventional division circuit will be described. The upper 3 bits excluding the divisor MSB are input to the multiplication coefficient generation circuit 101, and the generated coefficients are input to the multiple selection circuits 115 and 117. The divisor and the dividend, which are the outputs of the various multiple generation shifters, are the multiple selection circuit 115,
After the necessary multiple is selected by the multiplication coefficient, it is compressed into a sum with a carry by a carry save adder or the like, and then input to the multiple generation adders 116 and 118. Outputs of the multiple generation adders 116 and 118 are input to a divisor register 120 and a partial remainder register 122. In this conventional division circuit, since the division is repeatedly performed, the input of the partial remainder register becomes the dividend only once at the first time, and thereafter, the partial remainder becomes the selector 121 each time.
Is selected by In the quotient generation cycle, the partial remainder of the number of bits necessary for determining the quotient is read from the partial remainder register 122, and the two-complement conversion circuit 123 generates the upper four bits of the two-complement partial remainder. The quotient generation circuit 124 generates two bits of the quotient using the upper four bits of the partial remainder, and the generated quotient is stored in the quotient register 127. In accordance with the generated quotient, a divisor is generated by a divisor multiple generation circuit, and a partial remainder generation redundant binary adder / subtractor 126 is generated.
Generates a partial remainder to be used in the next cycle. Finally, after the quotient has been prepared for the required number of bits, the quotient is converted to a normal number by the quotient two's complement adder, and the division ends.

In the above method, 1/64 times the divisor is used in scaling. This means an increase in the bit width of the divisor and the dividend after scaling, and L
In mounting the SI, the area increases. In addition, by strictly dividing the range of the divisor, the multiplication coefficient can be further simplified, that is, a simple combination of multiples for realizing multiplication can be obtained.

However, the divisor can be divided into 16 ranges, for example, by increasing the number of reference bits of the divisor by one bit. In this case, however, identification of the divisor range which is a pre-process of scaling becomes complicated, and delay is caused. Getting worse.

[0036]

As described above, in the conventional divider with scaling, 1/16 times, 1/6 times
There is a problem that a multiple of a smaller divisor such as four times is required, and the circuit scale becomes large.

Further, when the reference bits of the divisor are increased and the range division is strict, there is a problem that the identification of the divisor range becomes complicated and the delay becomes worse.

Accordingly, the present invention has been made in view of the above problems, and has as its object to use a high radix subtraction shift method for performing scaling to limit a divisor to a certain range, and to use a redundant binary representation in a partial remainder. It is an object of the present invention to provide a division circuit which simplifies scaling, suppresses an increase in circuit scale, and speeds up quotient generation.

[0039]

In order to achieve the above object, a division circuit according to the present invention, wherein k is a positive integer, is defined as 1/2 ＾ k〜1 / 1 /.
The quotient is calculated by referring to the divisor and the dividend normalized to 2 ＾ (k + 1) (where ＾ indicates a power operation) and the bit length defined by the radix and the maximum digit number of the operation among all bits of the partial remainder. A high radix type division circuit to be determined,
m is a positive integer, ± 1 / １ ／ of the input divisor and dividend
A multiplier generating means for generating a multiple of 2 ＾ m times, a multiplication coefficient generating means for generating a multiplication coefficient for scaling the divisor within a predetermined range according to a value range of the divisor, and a multiple generated by the multiple generation means. It is configured to include scaling means for scaling a divisor and a dividend from the multiplication coefficient generated by the multiplication coefficient generation means, and a division circuit for performing a division by the divisor and the dividend generated by the scaling means.

In the present invention, the multiple generation means includes:
A multiple of 1/2 times, 1/4 times, 1/8 times and-1/8 times is generated, and the scaling means sets the divisor to 3/2 ×
Scaling is performed in a range of not less than 1/2 ＾ k and less than 7/4 × １ ／ ＾ k.

In the present invention, the division circuit refers to the number of higher-order bits of an arbitrary length of the partial remainder and converts the two-complemented 5
An upper bit of the partial remainder is generated, and a quotient is generated with reference to the upper four bits of the partial remainder.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, the input divisor and dividend are preliminarily set to 1.50 (= 3/2) ≦ divisor <1.75 (=
7/4), 1/16, 1/64
This eliminates the need for multiples and makes it possible to suppress an increase in circuit scale. In addition, when the quotient is generated, the upper 5 bits of the partial remainder are binarized to two's complement, while the quotient generation itself is
By referring to the upper 4 bits, quotient generation can be performed at high speed in the above scaling range while guaranteeing the quotient calculation accuracy.

According to the present invention, in a preferred embodiment, 1/2 ＾ k〜1 / 2 ＾ (k + 1) (k is a positive integer,
In the high radix type division circuit which determines the quotient by referring to the divisor and the dividend normalized to the exponentiation and the bit length determined by the radix and the maximum digit number of the operation among all bits of the partial remainder, Multiple generating means (2-9 in FIG. 1) for generating a multiple of ± 1 / 2１ ／ m times (m is a positive integer) the divided divisor and the dividend, and scaling the divisor within a predetermined range according to the value range of the divisor. Multiplication coefficient generation means (1 in FIG. 1) for generating a multiplication coefficient, and scaling means (FIG. 1) for scaling a divisor and a dividend from the multiple generated by the multiple generation means and the multiplication coefficient generated by the multiplication coefficient generation means. Means for selecting multiples of 1, 15, 17;
Multiple generating means 16 and 18), and dividing means (23 to 28 in FIG. 1) for performing division by the divisor and dividend generated by the scaling means. In the embodiment of the present invention, the multiple generating means (2 to 9 in FIG. 1)
Double, 1/4, 1/8, and-1/8 times,
Scaling means sets the divisor to 3/2 × 1 / 2１ ／ k
Scaling is performed in a range less than 7/4 × 1/2 ＾ k. In the division means, two's complement conversion means (2 in FIG. 1)
3) refers to the number of upper bits of an arbitrary length of the partial remainder and generates the upper 5 bits of the 2's complemented partial remainder, and the quotient generation means (24 in FIG. 1) outputs the upper 5 bits of the generated partial remainder. 4
Generate a quotient by referring to the bits.

An embodiment of the present invention will be described below. First, the principle of the division circuit of the present invention will be described using a PD plot. FIG. 2 shows a PD plot corresponding to the embodiment of the present invention. In one embodiment of the present invention, 1.50 ≦ divisor <1.
The scaling is performed in the range of 75.

[0045]

[Table 2]

In a combination of multiples for realizing multiplication, scaling can be realized with a multiple up to 1/8.
The identification of the range of the divisor is the upper three bits of the divisor excluding the MSB, as in the above-described conventional technology. In this case, if the uncertainty area is determined in the same manner as in the related art, the two-complemented upper bits of the shifted partial remainder are expressed as 0100 in binary.
In the case of (4.0 in decimal), the range is exceeded. In this case, the range of the shifted partial remainder rR (j) is 3.0 <rR (j) <5.0 (7), and in the area of 1.5 ≦ divisor <1.75, the quotient is Include both the region of 1 or 2 and the region of 3 or 4, and cannot satisfy the above expressions (1) and (2).

Here, with respect to the shifted partial remainder, conversion is performed from a redundant binary number to a two's complement number including the upper 5 bits in addition to the upper 4 bits to be referred to. By this conversion, the value range of the shifted partial remainder when the reference bit is “0100” is expressed as follows.

3.5 <rR (j) <5.0 (8)

In the range represented by the above equation (8), all the uncertain regions are included in the region having a quotient of 3,
The above equations (1) and (2) can be satisfied. The PD plot in this case is shown on FIG.

[0050]

Next, the operation of the embodiment of the present invention will be described with reference to specific examples. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In this embodiment, the radix of the operation is 4, and the digit set is ｛−3, −2, −1, 0,
A case will be described in which the divisor and the dividend are n-bit decimal numbers and the arithmetic algorithm uses the extended SRT division algorithm.

1 is a multiplication coefficient generation circuit for generating a multiplication coefficient used for scaling, and 2 to 5 are each 1 / divisor.
A shift circuit for generating a multiple of 2, 1/4, 1/8, and-1/8, wherein 6 to 9 represent 1/2, 1/4, 1 /
8, a shift circuit for generating a multiple of-1/8,
Reference numeral 17 denotes a multiple selection circuit which selects a divisor and a dividend according to the multiplication coefficient and compresses the multiple into two in the carry save adder. It is a multiple generation adder that generates a scaled divisor and dividend. Reference numeral 20 denotes a divisor register for storing the divisor, reference numeral 22 denotes a partial remainder register, and reference numeral 21 denotes a selector for selecting either the partial remainder or the input dividend. Reference numeral 23 denotes a two-complement conversion circuit that converts the upper bits of the partial remainder necessary for quotient determination into two's complement, 24 denotes a quotient generation circuit that generates a quotient based on the output of the two's complement conversion circuit 23, and 25 denotes a quotient generation circuit 24 Is a divisor multiple generation circuit for selecting a multiple of the divisor according to the output of, and 26 is a partial remainder generation redundant binary addition / subtraction circuit for generating the next partial remainder from the output of the divisor multiple generation circuit 25 and the output of the partial remainder register. Reference numeral 27 denotes a quotient register that stores the output of the quotient generation circuit 24, and reference numeral 28 denotes a quotient two's complement adder that performs two's complement of the quotient.

In the above-described conventional divider, the divisor required for scaling and the multiple of the dividend are required to be up to 1/64, but in the present embodiment, it may be up to 1/8.

Next, the operation of this embodiment will be described. The upper 3 bits excluding the divisor MSB are input to the multiplication coefficient generation circuit 1, and the generated coefficients are input to the multiple selection circuits 15 and 17. The divisors and dividends output from the various shifters for generating multiples are input to the multiple selection circuits 15 and 17, and after the necessary multiples are selected by the multiplication coefficient, they are compressed to carry and sum by a carry save adder or the like. Later, it is input to the multiple generation adders 16 and 18. At this time, the required multiple is
1/2, 1/4, 1/8,-1/8, 1/16,
1/64 is not required. Outputs of the multiple generation adders 16 and 18 are input to a divisor register 20 and a partial remainder register 22.

In this embodiment, since the division is repeatedly performed, the input of the partial remainder register becomes the dividend only once and the partial remainder is selected by the selector 21 each time thereafter.

In the quotient generation cycle, the partial remainder register 2
From 2, the partial remainder of the number of bits required for quotient determination is read out, and the upper 5 bits of the two-complement converted partial remainder by the two's complement conversion circuit 23 are generated. In a conventional division circuit, 4
Although there were bits, here 5 bits are generated. For this reason, the range of the uncertainty area on the P-D plot can be narrowed as compared with the conventional example, and the quotient can be selected without fail in the scaling range adopted in the present invention.

The two's complement processing can be realized by, for example, a carry propagation adder. When the number of bits of two's complement is increased, the number of bits to be two's complemented can be increased by a carry selection adder or the like without affecting the delay.

The quotient generation circuit 24 generates two bits of the quotient using the upper four bits of the partial remainder, as in the conventional example. The generated quotient is stored in the quotient register 27. Further, in accordance with the generated quotient, the divisor multiple generation circuits 15 and 17 generate a multiple, and the partial remainder generation redundant binary adder / subtracter 26 generates a partial remainder used in the next cycle. Finally, after the required number of bits are obtained, the quotient two's complement adder 28
Converts the quotient into a normal number, and the division ends.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[0059]

As described above, according to the divider of the present invention, in the scaling, 1/16, 1/64
Determining the quotient by referring to only the upper 4 bits of the two's complement partial remainder, as in the case where the use of a multiple is not required and scaling is performed in the range of 1.75 ≦ divisor <2.00. Thus, there is an effect that the increase in the circuit scale is suppressed and the speed is increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a scaling type divider according to an embodiment of the present invention.

FIG. 2 illustrates a division algorithm to which the present invention is applied.
It is a PD plot.

FIG. 3 is a diagram illustrating an example of a configuration of a scaling type divider according to a conventional method.

FIG. 4 is a PD plot illustrating a division algorithm to which conventional scaling is applied.

FIG. 5 is a PD plot illustrating a conventional division algorithm.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 multiplication coefficient generation circuit 2 divisor 1 / 2-time generation shifter 3 divisor 1 / 4-time generation shifter 4 divisor 1 / 8-time generation shifter 5 divisor-1 / 8-time generation shifter 6 dividend 1 / 2-time generation shifter 7 dividend 1 / 4 times generation shifter 8 dividend 1/8 times generation shifter 9 dividend-1/8 times generation shifter 15 divisor multiple selection circuit 16 divisor multiple generation adder 17 dividend multiple selection circuit 18 dividend multiple generation adder 20 divisor register 21 partial remainder selector Reference Signs List 22 partial remainder register 23 two's complement conversion circuit 24 quotient generation circuit 25 divisor multiple generation circuit 26 partial remainder generation redundant binary addition / subtraction circuit 27 quotient register 28 quotient two's complement adder 101 multiplication coefficient generation circuit 102 divisor 1/2 generation shifter 103 Divisor 1/4 times generation shifter 104 Divisor 1/8 times generation shifter 105 Divisor 1/16 times generation shifter 106 Division Number 1/64 times generation shifter 107 Divided 1/2 times generation shifter 108 Divided 1/4 times generation shifter 109 Divided 1/8 times generation shifter 110 Dividend 1/16 times generation shifter 111 Divided 1/64 times generation shifter 115 Divisor multiple Selection circuit 116 divisor multiple generation adder 117 dividend multiple selection circuit 118 dividend multiple generation adder 120 divisor register 121 partial remainder selector 122 partial remainder register 123 two's complement conversion circuit 124 quotient generation circuit 125 divisor multiple generation circuit 126 partial remainder generation redundancy 2 Addition / subtraction circuit 127 Quotient register 128 Quotient two's complement adder

Claims (4)

[Claims] (1) When k is a positive integer, ＾ {k to 〜}
A divisor and a dividend normalized to (k + 1) (where ＾ indicates a power operation) and a high value that determines a quotient by referring to a bit length determined by a radix of operation and a maximum digit number among all bits of the partial remainder A radix-type division circuit, wherein m is a predetermined positive integer, a multiple generating means for generating a multiple of ± 1/2 ＾ m times the input divisor and dividend, and a predetermined number of divisors according to a range of the divisor. Multiplication coefficient generation means for generating a multiplication coefficient that scales within a range, scaling means for scaling a divisor and a dividend from the multiple generated by the multiple generation means and the multiplication coefficient generated by the multiplication coefficient generation means, Division means for performing division by the divisor generated by the scaling means and the dividend. 2. The division circuit according to claim 1, wherein said multiple generation means includes a half of said divisor and said dividend,
The scaling means generates multiples of 1/4, 1/8 and-1/8 times, and the scaling means converts the divisor to 3/2 x 1/2.
A division circuit for performing scaling in a range of {k or more and less than 7/4 × 1/2} k. 3. The division circuit according to claim 1, wherein said scaling means generates the plurality of multiples generated by said multiple generation means by compressing them into a carry and a sum by a carry save addition means. A division circuit for performing scaling by adding a carry and a sum by a carry propagation unit. 4. The division circuit according to claim 2, wherein the division means refers to the number of upper bits of an arbitrary length of the partial remainder, and generates upper bits of a 5-bit partial remainder that is two's complement, Means for generating a quotient by referring to the upper four bits of the partial remainder.