JP2795253B2 - Divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital divider.

[0002]

2. Description of the Related Art As a conventional divider, an algorithm using a so-called "subtraction shift method" or "subtraction separation method" as a division algorithm has a good balance between hardware amount and performance. Commonly used.

This division algorithm is a method of performing division by determining a quotient, shifting a remainder (partial remainder), and subtracting a multiple of a denominator (divisor) from the remainder, as in the case of performing division by handwriting. . Such division algorithms are described in, for example, publications (“High-speed computer operation”,
Restorative division, non-recoverable division, SRT division (D.Sweeney, JERobertso, 1980, Modern Science, pp. 214-249)
n, a method proposed simultaneously by three researchers of TDTocher), and various division methods such as extended SRT division. Reference ⁽¹⁾ (Transactions of the Institute of Electronics, Information and Communication Engineers, 1984, Vol. J67-D, No. 4, pp. 450-457) describes SRT division with a radix of 2 for operation. Reference ⁽²⁾ (IEEE Transactions on Computers, Vol. C-19, N
o.8, August 1970, pp.720-733), the radix of the operation is 4
The extended SRT division is described.

Japanese Patent Laid-Open Publication No. Hei 3-102519 proposes a structure of a divider that uses SRT division with a radix of 2 and inserts a normalizer before the operation to support fixed-point division. In Japanese Patent Application Laid-Open No. 4-153828,
There has been proposed a division method in which the most significant bit is fixed to a constant value so that the upper bits of the partial remainder do not overflow by using SRT division with the radix of the operation being 2.

In the following, first, a general-purpose division method using the subtraction shift method will be described, and then a conventional example will be described.

First, a general division procedure will be briefly described. The bit length of the operation is n (arbitrary positive integer), the radix of the operation is r, the divisor is D, the dividend is R (0), j is an integer of 0 or more, and the jth partial remainder is R (j), the jth Is the quotient of q (j). Here, the divisor D and the dividend R
(0) is assumed to be normalized.

In the following, as the floating-point normalization format, 1. xxxx shall be used. Even when handling data formats that do not match this format,
By performing an appropriate shift process before and after the operation, the process for this floating-point format can be applied.

Here, the quotient and partial remainder used are represented by a redundant binary expression. That is, in the two's complement representation, where each bit is represented by {0, 1}, {-1, 0,
Allows for three values of 1｝, allowing negative bits.

Under the condition that the input data is normalized as described above, a quotient and a partial remainder can be sequentially obtained by using a recurrence formula expressed by the following formula (1).

R (J + 1) = r × R (j) −q (j + 1) × D (1)

At this time, the quotient q (j + 1) is selected from a set of digits defined by the radix r so as to satisfy the following equation (2).

0 ≦ R (j + 1) <k × D (2)

Here, k is a constant satisfying the following equation (3).

K = m / (r-1) (3)

Here, m is a digit having a maximum absolute value in a digit set in a radix r number system.
In this case, since the minimum value of m is ×× r and the maximum value is r−1, the range of k is as shown in the following equation (4).

1/2 ≦ k <1 (4)

For example, taking a radix-4 number system as an example, a digit set is represented by {-3, -2, -1,0,1,2,3} and {-2, -1,0,1, 2｝
There are two possibilities.

For the former, k = 1, and for the latter, k = ２. The fact that the value of k becomes smaller means that the value range of the partial remainder in the middle of the calculation is narrowed according to the above equation (2). That is, in the latter case, since the triple cannot be selected as a multiple of the divisor, the range of the partial remainder in the middle of the calculation is restricted so that the division can be performed up to twice the divisor.
In the case of a radix-2 number system, the digit set is {-1,0,1}
Only, which corresponds to the case where k = 1.

When the quotient is obtained by the above equation (1), the number of bits of the quotient obtained by one division is log ₂ r. Therefore, by repeating the division n / (log ₂ r) times, the desired bit can be obtained. You can find the quotient of numbers.

Since the finally obtained quotient is in a redundant binary representation, it is necessary to convert this to a two's complement representation according to the following procedure.

First, with reference to the bit string of the quotient in the redundant binary representation, a positive partial quotient having "1" in the bit position of "1" and "0" in the other bit positions; In the quotient of the redundant binary representation, "1" is separated into bit positions of "-1", and the other bit positions are separated into negative partial quotients of "0".

Next, the quotient of the two's complement representation is obtained by subtracting the negative partial quotient from the positive partial quotient using both the two's complement representation. For a method of converting such a redundant binary representation to a two's complement representation, see Reference ⁽³⁾ (1983 IEICE Transactions, Vol. J66).
-D, No.6, pp.683-690) or Reference ⁽⁴⁾ (1984 IEICE Transactions, Vol.J67-D, No.4, pp.450-457). Referenced.

Further, when the final partial remainder becomes a negative value, the quotient is excessively increased by one in the last subtraction, so that one is subtracted from the LSB (least significant bit) of the quotient.

Next, a conventional example of a divider constituted by using the above-described division procedure will be described with reference to the drawings. FIG. 3 is a block diagram showing a configuration of a conventional divider. As a conventional divider, in the following, the radix of the operation is 4, the digital set is {-2, -1,0,1,2}, the divisor and the dividend are n bits long decimal, and the extended SRT division algorithm is used as the operation algorithm. The case of division used will be described. Also, each digit of the redundant binary representation is {-1,0,1} = {(11), (00), (01)}
It is represented by a bit string.

In FIG. 3, 1 is a register for holding a divisor (D) (divisor register), 4 is a register for holding a partial remainder in a redundant binary expression (a partial remainder register), and 16 is a quotient of the redundant binary expression. This is a register (quotient register) to be held. 5 is a circuit for determining a quotient (quotient generation circuit), 10 is a shifter for shifting the partial remainder left by 2 bits, 11, 12,
Reference numeral 14 denotes a multiple generation circuit for generating a -1 multiple, a -2 multiple, and a 2 multiple of the divisor. Reference numeral 21 denotes a divisor multiple selector, which selects any one of the divisor multiples generated by the divisor multiple generators 11, 12, and 14 and '0' according to the result of the quotient generation circuit 5. . Reference numeral 25 denotes a two's complement conversion circuit, which converts a partial remainder upper bit of a bit length necessary for quotient determination into a two's complement number from the partial remainder. Reference numeral 20 denotes a subtractor (partial remainder generation redundant binary subtractor) that performs subtraction of a multiple of the selected divisor from the partial remainder. Reference numeral 24 denotes a selector for selecting any one of an external input (dividend R (0)) and an internally generated partial remainder for the partial remainder. Reference numeral 30 denotes a separator (positive bit / negative bit separator) for separating the quotient held in the redundant binary representation into a positive partial quotient and a negative partial quotient.
Is a two-complement adder (quotient two-complement adder) that obtains a quotient (Q) in two's complement representation by subtracting a negative partial quotient from a positive partial quotient
It is.

Next, the operation of the conventional divider shown in FIG. 3 will be described. Divisor D normalized in the first cycle
And the dividend R (0) are input and stored in the divisor register 1 and the partial remainder register 4, respectively.

The first division is performed in the second cycle. First, the MSB of the divisor stored in the divisor register 1
Upper 4 bits excluding (most significant bit) (M
SB is always known to be 1 and will not be referred to), and the quotient generation circuit 5 generates the first quotient by referring to the 6 bits held in the partial remainder register 4.

Next, based on the generated quotient value, the multiple of the divisor corresponding to the quotient value is selected from the multiples of the divisor previously generated in the divisor multiple generation circuits 11, 12, and 14 by the multiple selector 21. And sends it to the subtractor 20. The quotient is stored in the quotient register 16.

In parallel with the operations of quotient generation, divisor multiple generation, and divisor multiple selection, a two-bit left shift of the partial remainder is performed. As a result of this shift, the least significant two bits that have become empty are filled with a redundant binary number “0”. As a result, the bit length of the partial remainder is extended by 2 bits.

FIG. 4 is a block diagram showing the configuration of the two's complement conversion circuit 25. In FIG. 4, reference numeral 401 denotes a separator (positive / negative bit separator) for separating the input partial remainder of the redundant binary representation into positive and negative bits, and 402 subtracts a negative bit from the separated positive bits. It is a subtractor (6-bit subtractor).

As a result of the subtraction, the input partial remainder is converted into a two's complement number, and the bit length is increased by one bit to a seven-bit length. This is because, in the redundant binary representation, each bit has information corresponding to a sign bit, so that the sign as a whole is not required, whereas when converted to two's complement, such a sign is required. This is because there is no redundancy, and a code bit is separately required.

Finally, the partial remainder generation redundant binary subtractor 20
Is used to calculate the partial remainder used in the next cycle. This partial remainder is selected by the selector 24 and stored in the register 4.

After the third cycle, the same operation as in the second cycle is repeated. 2 quotients per cycle
Since bits can be generated, this operation is repeated for n / 2 cycles to obtain an n-bit quotient.

[0034]

However, in the conventional divider as described above, since the partial remainder is stored in a redundant binary representation, it is necessary to determine a quotient according to the radix of operation and the maximum number of digits. Before the bit length partial remainder is input to the quotient generation circuit, it needs to be converted into a two's complement representation, and there is a problem that the delay of this conversion circuit increases the delay of the divider.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high radix subtraction shift method and a division which uses a redundant binary expression for a partial remainder before determining a quotient. It is an object of the present invention to provide a divider which can reduce the two-complement processing of the partial remainder and increase the speed.

[0036]

To achieve the above object, a divider according to the present invention refers to a bit length defined by a radix of operation and a maximum digit number among all bits of a divisor, a dividend and a partial remainder. A high radix type divider for determining a quotient, wherein a quotient determining means for determining a quotient by referring to higher-order bits expressed by two's complement of a divisor and a partial remainder; Only the bits are held in the two's complement representation, and the other bits are held in the redundant binary representation. The partial remainder holding means, and the partial remainder input from the partial remainder holding means is placed higher by the number of bits determined by the radix of the operation. And a bit length portion corresponding to the number of bits shifted by the shifter in the partial remainder held in redundant binary notation, and held in two's complement notation. And min remainder, a two's complement conversion means for converting to a two's complement representation together, is characterized by comprising a.

Further, in the present invention, the two's complement conversion means may perform a redundant binary conversion on a bit length portion corresponding to the number of bits shifted by the shifter in the partial remainder held in the redundant binary representation. The positive bit which makes the bit of the expression '1' a binary expression '1', the redundant binary expression '0' and '-1' the binary expression '0', and the redundant binary expression ' The bits of -1 are represented by binary representations of '1', and redundant binary representations of '0' and '1'
Positive / negative bit separator that separates a negative bit from the positive bit and outputs a two's complement number, and the two's complement number A second subtractor for subtracting '1' from the upper bits of the partial remainder held in the expression, and an output of the second subtractor if the output of the first subtractor is negative, A selector for selecting an upper bit of a partial remainder held in the two's complement expression when an output of the first subtractor is positive.

[0038]

According to the divider of the present invention, all the partial remainders generated during the operation are not held in the redundant binary representation,
Of the total number of bits of the partial remainder, the partial remainder of the bit length required for quotient determination according to the radix of operation and the maximum number of digits is held as a two's complement representation, and the other partial remainder is represented as a redundant binary representation. Hold.

According to the present invention, at the input stage of the quotient generation circuit, it is not necessary to convert the upper bits necessary for determining the quotient of the partial remainder from the redundant binary representation to the two's complement representation. In the quotient determination, a high-speed operation is realized by omitting the two-complement conversion circuit preceding the quotient generation circuit, which is required in the above-mentioned conventional divider.

[0040]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the first exemplary embodiment of the present invention. In the present embodiment, the radix of the operation is 4, and the digit set is ｛-2, -1,0,1,
2｝, the case where the divisor and the dividend are n-bit decimal numbers and the division is performed using the extended SRT division algorithm as the operation algorithm will be described. Each digit in the redundant binary representation is represented by a bit string of {-1, 0, 1} = {(11), (00), (01)}.

In FIG. 1, 1 is a register for holding a divisor (divisor register), 2 is a register for holding upper bits of a partial remainder required for quotient determination in a two's complement representation (partial higher register), and 3 is a block A register (partial remainder lower register) for holding lower bits other than a partial remainder upper bit held in 2 in a redundant binary expression, and 16 is a register (quotient register) for holding a quotient in a redundant binary expression. . Reference numeral 5 denotes a circuit for determining a quotient (quotient generation circuit), and reference numerals 8 and 9 denote shifters for shifting upper bits / lower bits of the partial remainder by two bits to the left. Reference numerals 11, 12, and 14 denote multiple generation circuits for generating -1 multiples, -2 multiples, and 2 multiples of the divisor, respectively. Further, reference numeral 21 denotes a divisor multiple selector, which selects any one of the divisor multiples generated by the divisor multiple generators 11, 12 and 14 and '0' according to the result of the quotient generation circuit 5. .

In FIG. 1, reference numeral 6 denotes a two's complement conversion circuit for extracting the upper two bits of the partial remainder of the redundant binary representation of the output of the shifter 9,
This is a circuit for converting the two bits into the two's complement number together with the upper bits of the partial remainder of the two's complement expression held in. Numerals 18 and 19 denote subtracters (partial remainder higher generation two's complement subtractor and partial remainder lower generation two's complement subtractor) for respectively performing a subtraction of a multiple of the divisor selected from the partial remainder. The subtractor 18 is a carry propagation subtractor in which the upper bit of the two's complement representation is used as one of the subtraction inputs, while the partial remainder lower generation two's complement subtractor 19 subtracts the lower bits of the redundant binary representation into the subtraction input. One is a redundant binary subtractor.

Further, in FIG. 1, reference numerals 22 and 23 denote selectors for selecting either an external input or an internally generated partial remainder for the partial remainder.
Corresponds to the upper bits of the two's complement representation, and the selector 23 corresponds to the lower bits of the redundant binary representation, respectively. A positive / negative bit separator 30 separates a quotient held in redundant binary representation into a positive partial quotient and a negative partial quotient, and 31 subtracts a negative partial quotient from the positive partial quotient. This is a two's complement adder for finding the quotient of the complement representation.

Next, the operation of the divider of this embodiment will be described.

The divisor D and dividend R (0) normalized in the first cycle are input and stored in the divisor register 1, the partial remainder upper register 2, and the partial remainder lower register 3, respectively.

The first division is performed in the second cycle. First, the upper 4 bits excluding the MSB of the divisor stored in the division register 1 (the MSB is always known to be 1 by normalization, so it is not referred to) and the 7 bits held in the partial remainder upper register 2 Referring to the quotient generation circuit 5, the first quotient is generated.

Next, based on the generated quotient value, the divisor selector 21 selects a divisor multiple corresponding to the quotient value from among divisors previously generated by the divisor multiple generation circuits 11, 12, and 14. And sends it to the subtractors 18 and 19. The quotient is stored in the quotient register 16.

In parallel with the above operations of quotient generation, divisor multiple generation, and divisor multiple selection, a two-bit left shift of the partial remainder is performed. Overflow input occurs due to shifting from the lower bits to the upper bits of the two's complement representation held in the partial remainder upper register 2.

The two bits input to the upper bits are converted into the two's complement representation. At this time, the upper bits may be borrowed. Reduce.

The two's complement conversion circuit 6 converts the lower two bits of the overflow caused by the shift into the two's complement representation, and performs the subtraction by borrowing generated during the conversion.

FIG. 2 is a block diagram showing the configuration of the two's complement conversion circuit 6. In FIG. 2, reference numeral 301 denotes “1” for an overflow bit in a redundant binary expression generated by a shift.
A positive bit string in which bits of the binary representation are '1' and the other bits, that is, '0' and '-1' of the redundant binary representation are '0' of the binary representation, and '-1' Of the binary representation of “1” and the other bits, that is, the redundant binary representation of “0” and “1”, into a negative bit sequence of binary representation of “0” ( A positive / negative bit separator) 302 is a two-bit subtractor that subtracts the negative bit from the separated positive bit and converts it into a two's complement representation. Reference numeral 303 denotes a subtractor (7) for subtracting '1' from the LSB of the partial remainder upper bit in the two's complement representation.
304 is a 7-bit subtractor 303
And a selector for selecting one of the subtraction output of the two bits and the partial upper bits of the two-complement representation by the borrow output of the two-bit subtractor 302.

The operation of the two's complement conversion circuit will be described. The upper two bits of the partial remainder lower bit overflowed by the shift operation are input to the two's complement conversion circuit shown in FIG. 2 and separated into a positive bit and a negative bit by a positive / negative bit separator 301, and subtracted by two bits. The signal is input to the unit 302 and subtraction is performed to convert it to two's complement.

When two bits of the overflow input take a negative value, a borrow occurs and is transmitted to the selector 304. In parallel with these operations, the upper 7 bits of the two's complement representation are 7 bits.
The signal is input to the bit subtractor 303, and '1' is subtracted from the LSB.

The borrow output of the 2-bit subtractor 302 is "1".
In the case of (with borrowing), the output of the 7-bit subtractor 303 is selected as the output of the selector 304. In the case of '0' (without borrowing), the output of the selector 304 is input to the two's complement converter. The upper 7 bits of the represented two's complement representation are selected as they are.

By the above operation, the conversion of the lower bits of the overflow due to the shift to the two's complement representation and the subtraction that occurs during the conversion are executed.

Finally, the partial remainder high-order two's complement subtractor 1
8 and the partial remainder lower generation redundant binary subtractor 19 calculate the partial remainder used in the next cycle. The upper bits of the two-complement representation and the lower bits of the redundant binary representation are selected by selectors 22 and 23, respectively, and are stored in partial remainder upper register 2 and partial remainder lower register 3.

After the third cycle, the same operation as in the upper second cycle is repeated. Since two bits can be generated per cycle, this operation is repeated n / 2 cycles to obtain an n-bit quotient.

In the present embodiment, as compared with the conventional divider shown in FIG. 3, the ordinary number conversion circuit for the upper bits of the partial remainder provided at the previous stage of the quotient generation circuit 5 can be reduced. The operation can be performed at high speed. In addition, when the configuration as in the present embodiment is used, it is necessary to use not a redundant binary subtractor but a subtracter that causes normal carry propagation for the upper bits. The delay is greater than that of a subtractor using a hexadecimal expression.
However, since the bit length is as short as 7 bits and the redundant binary subtraction of the lower bits is performed in parallel, the delay increment is (upper bit subtraction processing time)-(lower bit redundant binary subtraction processing). .

On the other hand, in the case of the above conventional divider,
The two-complement conversion processing of the upper bits is (positive bit / negative bit separation) + (subtraction processing), and the delay is much larger than that of the divider of the present embodiment.

[0060]

As described above, according to the divider of the present invention, while the ordinary subtractor holds all the partial remainders in the redundant binary representation, the bit length required for determining the quotient is determined. Only the upper bits of the partial remainder are stored in two's complement representation.
For this reason, it is possible to omit the two-complement process of the partial remainder before the quotient generation, and to achieve an effect of realizing high speed in each cycle of division.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention, and is a block diagram showing a subtraction shift type subtractor.

FIG. 2 is an ordinary number conversion circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a configuration of a radix-r subtraction shift type divider according to a conventional method.

FIG. 4 is a diagram showing a configuration of a conventional ordinary number conversion circuit.

[Description of Signs] 1 divisor register 2 partial remainder upper register 3 partial remainder lower register 4 partial remainder register 5 quotient generation circuit 6 two's complement conversion circuit 8 2 bit shifter 9 2 bit shifter 10 2 bit shifter 11 divisor -1 multiple generation circuit 12 divisor 14 Doubler generator for divisor 16 Quotient register 18 Partial remainder higher generation two's complement subtractor 19 Partial remainder lower generation redundant binary subtractor 20 Partial remainder generation redundant binary subtractor 21 Divisor multiple selection selector 22 Partial remainder upper selection selector 23 Partial remainder lower selection selector 24 Partial remainder selection selector 25 Two's complement conversion circuit 30 Positive / negative bit separator 31 Quotient two's complement adder 301 Positive / negative bit separator 302 Two-bit subtractor 303 7-bit subtractor 304 Partial remainder higher-order selector 401 Positive / negative bit separator 402 7-bit subtractor

Claims (2)

(57) [Claims] 1. A high radix type divider for determining a quotient by referring to a bit length determined by a radix of operation and a maximum digit number among all bits of a divisor, a dividend, and a partial remainder, wherein the divisor and the partial remainder are divided by two. Quotient determining means for determining the quotient by referring to the higher-order bits represented by the complement, and for the partial remainder, only the bits of the part input to the quotient determining means are held in the two's complement representation, and the other bits are redundant binary. A partial remainder holding means for holding in a binary representation, a shifter for shifting a partial remainder input from the partial remainder holding means upward by a number of bits determined by a radix of an operation, and a partial remainder held in a redundant binary representation A two-complement conversion that converts a bit length portion corresponding to the number of bits shifted by the shifter and a partial remainder held in a two-complement expression into a two-complement expression. Means, and a divider. 2. The two-complement conversion means, for a bit length portion corresponding to the number of bits shifted by the shifter in the partial remainder held in the redundant binary representation, converts the partial remainder to "1" in the redundant binary representation. Is the binary representation of '1' and the redundant binary representations '0' and '-1' are
The positive bit to be 0 and the bit of -1 in the redundant binary representation are set to '1' in the binary representation, and '0' and '1' in the redundant binary representation are set to '0' in the binary representation. A positive / negative bit separator that separates the positive bit from the negative bit, a first subtractor that outputs a two's complement by subtracting the negative bit from the positive bit, and a partial remainder held in the two's complement representation. A second subtractor for subtracting '1' from the upper bit; and if the output of the first subtractor is negative, the output of the second subtractor is selected, and the output of the first subtractor is positive. 2. The divider according to claim 1, further comprising: a selector for selecting an upper bit of a partial remainder held in the two's complement expression.