KR940008610B1 - Method and processor for high-speed convergence factor determination - Google Patents

Abstract

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Description

[Name of invention]

Fast convergence factor determination method and processor

[Brief Description of Drawings]

1 is a block diagram illustrating one embodiment of the present invention.

2 is a block diagram illustrating one embodiment of a newly normalized signature decision to improve convergence factor determination in convergence division.

3 is a block diagram illustrating one embodiment of a newly normalized signature decision to enhance convergence factor determination in a square root determination.

4 is a block diagram of computer hardware implementation of the present invention.

Detailed description of the invention

[Background of invention]

Traditional implementations of moving point convergence call methods and square root arithmetic determinations are difficult due to the lack of computation of effective convergence factors in both operations. Convergence operations use repeated multiplication to achieve some exact result. The possible range of modified input values, X, is known as 0 <X <2. Other limitations of this range advance computational decisions.

In addition, the determination of the convergence factor for convergence appeal generally requires a normalization step, a subtraction operation that requires a propagation-propagation step, and other normalization steps. In addition, the determination of the convergence factor for square root calculation requires coefficient calculation. Therefore, the convergence method and evaluation of the convergence factor for square root determination require more computation cycles than the move-point multiplication calculation. Since the convergence factor occurs continuously in both calculations, the inefficiency of the calculation of the convergence factor directly reduces the efficiency of the calculation in both the convergence sum method and the square root determination operation.

Such a need exists for a more efficient method of determining convergence methods and convergence factors for square root determination for convergent subtraction square root determination to facilitate these two entire processors in a digital platform.

[Summary of invention]

The present invention is directed to a numerical central arithmetic processing unit, such as a digital signal central arithmetic processing unit, by making the convergence factor determination familiar through the combinational logic and taking a limited range for the changed input values for the convergence factor determination and Square root determination enhances the efficiency of convergence factor determination. This approach avoids subtraction and propagation-propagation operation, thereby allowing both convergence operations to be preferentially limited by the multiplier arrival time factor.

Best Mode for Carrying Out the Invention

FIG. 1, generally denoted by number 100, is a flow chart representing one embodiment of the present invention, via advantageous combinational logic, in contrast to various operations, to determine new values for X 116, X '. We use the newly normalized decision of the signature (f ') and obtain the convergence factor used as a mathematical decision, ie convergence call method or square root decision, which is repeated (118, 120) until a solution with a certain accuracy is obtained. do.

In order to initiate convergence division and square root determination using shift-point operation according to one embodiment of the present invention, a numerical central processing unit (e.g., a digital signal central processing unit) may have X equals ± ∞, ± 0. Or use a processing platform to check input X to determine whether it matches a Not-a-Number (NaN) 102. If X matches ± ∞, ± 0, or NaN, the error-checking mechanism determines the convergence factor according to the principle of using a range limit of X to 0.5 <X <B (122, B is represented by multiple values below). Avoid. If X has a value different from ± ∞, ± 0, or NaN, X is changed by multiplication by the appropriate seed value S, where B is assigned 2.0 for the square root decision (103, 104) and 1.5 for the convergent division. A value that S can execute to get X in the range 0.5 ≦ X <B, i.e. S 1 / X. When X is set to X = 2 ^{e *} f, 1 ≦ f <2 (105). The processing platform then checks whether 0.5 ≦ X <1.0. If 0.5 ≦ X <1.0, the platform is set to e = −1 (110). If 0.5 ≦ X <1.0 is not established, 1.0 ≦ X <1.0 is not established, and 1.0 ≦ X <β 108, e is set to 0 (112). If e is set (110, 112), f 'is determined (114; additional details regarding the determination of f' will be provided below). X 'is also determined, where X' = 2 ^{e *} f. The platform uses X 'to calculate the convergence factor such that a mathematical decision such as convergence division or square root decision 118 occurs. The convergence operation is then calculated such that a mathematical decision, such as convergence division or square root determination, is generated and repeated until a solution with a certain accuracy is obtained (120).

In an embodiment where the convergence factor determination is indicated by numeral 200 in FIG. 2 and convergence factor determination after e has been set 110 and 112 for convergence division determination, the processing platform uses the radix bias to enable IEEE 754-1985. The exponent e is biased according to the moving point reference, providing the least significant bit and the biased exponent.

If the least significant bit of the biased exponent is 1 (214), a binary f value of 1. WXYZO is selected (212, 213). If the biased least significant bit is zero, then a value of compliance f of 1.1 VWXY is selected (21, 215). Provides a binary number of 1.0V'W'X'Y 'for f' if the least significant bit is 0, and 1.W'X'Y'Z 'for f' if the least significant bit is 1 (218). The selected value of f is inverted to provide an integer of one. In addition, the least significant bit of the biased exponent e is inverted to form a final biased exponent for f '(210) (208).

In one embodiment of the convergence factor determination for the square root determination, denoted by the number 300 in FIG. 3 and after e is set (112, 114), the processing platform is an IEEE 754-1985 shift using radix bias. -Bias the exponent e according to the decimal point criteria and generate an exponential biased with the least significant bit (306). If the least significant bit of the biased exponent is 1 314 (314), a binary f value of 1.VWXYZ is selected (312, 313). If the least significant bit of the biased exponent is zero (314), a binary f value of 1.11 VXW is selected (312, 315). If the least significant bit is 0, provide a binary number of 1.00V'W'X '; if the least significant bit is 1 (318), provide a binary number of 1.V'W'X'Y'Z'. The selected value of f is reversed (316). In addition, the least significant bit of the biased exponent is inverted to form 315 the final biased exponent for f '(308).

For convergence division and square root determinations, the convergence factor determination will result in the original 1 sb of error. The source of the error 1sb is the use of one complement rather than two complementary operations. While the two complements do not provide the original 1sb of error, the two complements require propagation propagation that hinders convergence factor determination. One complement prevents this propagation and is used primarily because of its speed. The original 1sb of error is negligible in the convergence operation because it is typically performed using extended precision hardware of the calculation and rounded with relatively low precision.

In the case of X = 1, the circle 1sb of the error will result in a particularly small amount than the circle, and thus the index 1b will change.

4 shows the hardware implementation of this command generally indicated by the number 400. A computer program for the implementation of the present invention may be authored in program memory 404, other memory 412, or arithmetic logic unit (ALU) due to the assignment of data storage means and data adjusting means of a numerical central processing unit. Can be realized in hardware. In one embodiment, program control unit 402 uses bus 410 to select a computer program to implement the present invention, and the status register determines whether X = ± ∞, ± 0 or NaN. 408, if X = ± ∞, ± 0, or NaN, the processing platform handles the error-checking mechanism and processing stops. If X is different from ± ∞, ± 0, or NaN, then ALU converts X to an X value such that 0.5 ≦ X <β. The multiplication by 1 / X is a feasible transform and β is chosen to be 1.5 for the convergence division and 2.0 for the square root determination (406).

For convergence division, the ALU's primary selection means selects a -1 value for e with 0.5 ≦ X <1.0, and the ALU's secondary selection means selects a zero value for e with 1.0 ≦ X <1.5 (406). For the square root determination, the ALU's tertiary selection means selects a value of -1 for e with 0.5 ≦ X <1.0, and the ALU's fourth order means selects a zero value for e with 1.0 ≦ X <2.0 (406 ). This index e is biased to the radix bias value according to the IEEE 754-1985 shift-point criteria. The ALU computes the value of f and outputs f as a series of binary bits consisting of the most significant bits and generally described as 1.VWXYZ, where f = X / 2 ^e if 1 ≦ <2 (406). For convergence division and 0.5 ≦ X <1.0, the ALU selects the output of the most significant bit so that the least significant bit of the biased exponent matches zero. For the convergence division and 1.0 ≦ X <1.5, the ALU selects the output of the most significant bit so that the least significant bit 1sb of the biased exponent is equal to one (406).

For the square root determination and 0.5≤X <1.0 so that the least significant bit of the biased exponent is zero, the ALU is followed by two initial bits to the right of the binary decimal point for the new binary bit to the right of the binary point. Select the output of the most significant binary bit of one bit to the left of the bit and the binary point (406). For the square root decision and 1.0≤X <2.0, so that the least significant bit of the biased exponent matches 1, the ALU is left to the beginning of all bits to the right of the binary point and to the left of the binary point for the new binary bit to the right of the binary point. The output of the most significant bit of the bits of 406 is selected (406). The ALU also supplements 406 the least significant bit of the biased exponent to determine the newly biased exponent 406.

For all these decisions, the ALU determines X ', where X' = 2 ^{e *} f '(406). For convergence division, the ALU determines a convergence factor of 2.0-X 'and a convergence factor of 1.5-0.5X' for the square root determination (406). The ALU uses one or more data adjustments and storage devices to compute convergence division operations or square root decisions using the relevant convergence factors until a solution with a certain accuracy is obtained.

Claims (10)

Numerical central processing unit including a processing platform for processing convergence factors using inputs different from ± ∞, ± 0, or not-a-number (NaN) for mathematical decisions, ie convergent division or square root determination As such, the input value is changed to the value X, whereby X is limited to a range having a lower limit that is equal to or greater than 0.5 and an upper limit β determined at least in part by the mathematical decision, which is defined as X = 2 ^{e *} f. A numerical processing unit, comprising: A) first selection means responsive to an input value for selecting an input value different from ± ∞, ± 0 or NaN, B) an input selected by the value X such that 0.5 &lt; Input value converting means responsive to said first selecting means for converting a value, said input value converting means each β value being a constant value related to a mathematical decision, C) said input value for selecting a value for an index e Means of conversion Exponent means responsive to D, and first determining means responsive to said input value converting means and exponent means for determining a value for f, where X = X / 2 ^{e so} that 1 &lt; f &lt; A first determining means, represented as a series of binary bits consisting of the most significant binary bit and the remaining binary bits, E) the most significant binary bit of f, 1, with the remaining binary bits of f located to the right of the binary decimal point, immediately to the left of the binary point. Positioning means responsive to the first determining means for positioning; F) second selecting means responsive to the positioning means and the first determining means for selecting a binary bit to the right of the binary decimal point according to the X value and a mathematical decision. G) complementary means responsive to said second selection means for determining the complement of the binary bit selected to the right of the binary point, H) the highest ratio of f equal to 1 And writing because combining the complement of the selected binary bits, f ', that is, to determine the new values for f combining means responsive to the complementary means, I) X' new value for a, or X X = 2 ^{e *} f Second deciding means responsive to said combining means to determine X ', and J) convergence factor Y such that Y = 2.0-X' for convergence division and Y = 1.5-0.5X 'for square root determination. And a processing platform for holding a third determining means responsive to the second determining means for generating a digital signal. 2. The apparatus of claim 1, wherein said first selection means for determining that an input value is different from ± ∞, ± 0 or NaN comprises a processing platform for performing an error check procedure, the upper limit being used for mathematical determination of convergence division. And β = 1.5 for one, and β = 2.0 for the mathematical determination of the square root. The method of claim 1, wherein the exponent means for selecting a value for the index e is A) in the convergence division decision, converting the input value to select a -1 value of e for the value of X such that 0.5 < = X < 1.0. Primary selection means responsive to the means, B) secondary selection means responsive to said input value converting means for selecting a zero value of e for a value of X such that 1.0? In the square root determination, the cubic selection means responsive to the input value converting means for selecting the value of -1 for the value of X such that 0.5 ≦ X <1.0, and D) so that 1.0 ≦ X <2.0 in the square root determination. Quaternary means responsive to said input value converting means for selecting a zero value of e for an X value, said second selecting means for selecting a right binary bit of a binary decimal point in accordance with an X value and a mathematical decision, AA) 0.5 in the convergence division decision For a range of X such that X <1.0, output for the new binary bit to the right of the binary point followed by the initial second bit and all subsequent bits to the right of the binary point, BB) 1.0 in determining convergence division For the square root determination, CC) output for the new binary bit to the right of the binary point followed by the initial second bit and all the binary bits following 2 to the right of the binary point, for a range of X where ≤X <1.5. For outputting a new binary bit to the right of the binary point, two bits followed by all the initial bits to the right of the binary point, for a range of X such that 0.5 ≦ X <1.0, and DD) For a range of X where 1.0≤X <2.0, a new to the right of the binary point, which is all the initial bits to the right of the binary point. Numerical central processing unit providing output for binary bits. The method of claim 1, wherein at least one of the security means for determining the complement of the selected bit to the right of the binary point comprises inverting all bit values to the right of the binary point, wherein a solution with a certain accuracy is generated. And means for repeating the determination of the convergence factor until it is reached for a mathematical decision, and adjusting one or more data to repeat the determination of the convergence factor until a solution with a certain accuracy is reached for the type of decision that caused it. Further comprising allocating a storage device, wherein the computer program storage medium itself comprises a first selection means, an input value converting means, an exponent means, a first determining means, a positioning means, a first, so that the computer program storage medium can execute processing of the convergence terminal. Fixed hardware embodiment of second selection means, complementary means, combining means, second determining means, and third determining means Includes a computer program storage medium comprising computer program storage medium value central processing unit, which itself also comprises a computer program storage medium comprising a computer program application of the processing made by the unit to handle a convergence factor. A first selecting means, an input value converting means, an exponent means, a first determining means, a positioning means, a second selecting means, a second of the apparatus, for merging the two parts to process the convergence factor. A numerical central computing process comprising a computer program storage medium having a determining means and a combination of at least one part of a fixed headware embodiment of the third determining means with at least one part of a computer program application of processing achieved by the apparatus. Device. Mathematical decision, ie convergent division or square root decision, and an input value X that is different from ± ∞, ± 0 or NaN, limited to any range with a lower limit equal to or greater than 0.5 and an upper limit β determined by said mathematical decision In the method of allocating data storage and data adjustment means of a numerical central processing unit to facilitate and improve moving-point calculations of convergence factors 2.0-X and 1.5-0.5X for 2 ^{e * f} , A) Allocating one or more data input devices for storage, B) allocating one or more data adjustment devices to determine that the input values are not ± ∞, ± 0 or NaN, C) input value X 0.5≤ Allocating one or more data adjustments and storage devices for conversion to X values such that X <β, wherein β is a constant value related to the mathematical decision, D) one or more options for selecting values for dimension e. Allocating other adjustment and storage, E) 1≤f <2 is and that f = X / 2 ^e f is to determine the value for f is represented by the most significant bit and the remaining bits, a binary number consisting of a series of binary bits Allocating one or more data reconciliation and storage devices, f) allocating one or more data reconciliation and storage devices to set the most significant bit of f to 1 with the remaining binary bits of f to the right of the binary decimal point, G ) Allocating one or more data adjustments and storage devices to select a binary bit to the right of the binary decimal point according to the value of X and a mathematical decision; H) one or more data to obtain the complement of the binary bit selected to the right of the binary decimal point. Allocating reconciliation and storage, I) combining the most significant bit 1 of f with the complement of the selected binary bits to The new value, that is, f 'step of assigning one or more data adjustment and storage in order to determine the value, J) the new X, i.e., X' values, X '= 2 ^{e *} f' to define one or more data adjusted to and stored Assigning a device, and K) assigning one or more data adjustments and storage devices to generate a convergence factor Y such that Y = 2.0-X 'for convergence division and Y = 1.5-0.5X' for a square root determination. A method of allocating data storage and data mediation means comprising steps. 7. The method of claim 6, further comprising allocating one or more data adjustments and storage devices to repeat the determination of the convergence factor until a solution with a certain accuracy is reached for a determination of the type that caused the data. Means allocation method. 7. The method of claim 6, further comprising a computer program storage medium comprising a fixed hardware embodiment of the computer program of the present invention such that the computer program storage medium itself can execute the program. 7. A method according to claim 6, comprising a computer program storage medium comprising a computer program application of the method such that the computer program storage medium itself can execute the program. 7. The apparatus according to claim 6, wherein the first selecting means, the input value converting means, the exponential means, the first determining means, the positioning means, the second selecting means, the second determining means of the apparatus for merging two convergence factors to be processed. And a computer program storage medium having a combination of at least one part of the fixed headware embodiment of the third determining means and at least one part of the computer program application of processing achieved by the apparatus. Assignment method.