JPH04505978A - Method and apparatus for fast convergence coefficient determination - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Background of the invention of method and device for fast convergence coefficient determination Traditionally, floating-point convergence division algorithms and square root algorithm tests are performed. The problem is that there is no way to efficiently calculate the convergence coefficient within both algorithms. is hindered by. The convergence algorithm uses iterative multiplication to achieve a given accuracy get the result. It is proven that the possible range of the corrected input value X is 0<X<2. ing. By further limiting such a range, the efficiency of algorithm judgment can be improved. It is possible to aim for

Furthermore, determining the convergence coefficient for convergence division generally requires a normalization step and a carry/transfer step. A subtraction operation that requires a carry-propagation step and another A normalization step is required.

Determining the convergence coefficient of the square root operation requires an additional scale song operation. Therefore , to determine the convergence factor for both convergence division and square root determination, use floating point multiplication requires more computational cycles than The convergence factor is sequential in both operations. occurs, so if the convergence factor operation is inefficient, the convergence division and square root determination This will directly reduce the computational efficiency of both algorithms.

Including the convergence coefficients of convergence division and square root determination, these two processes are all performed digitally. More efficient methods are needed to make the body more efficient.

Summary of the invention The present invention uses combinatorial logic to speed up the determination of convergence coefficients. digital signal processing by assuming a limited range of corrected input values for floating-point convergence division and square root determination in numerical processors such as Improve the efficiency of determining convergence coefficients. This method uses subtraction and carry/propagation operations. Therefore, both convergence algorithm operations are reduced by a multiplier latency factor (mult Mainly limited by iplier latency time factor) be able to.

Brief description of the drawing FIG. 1 is a block diagram illustrating one embodiment of the invention.

Figure 2 shows a new normalization method for improving convergence coefficient judgment in convergence division operations. 2 is a block diagram illustrating one embodiment of determining significant digits; FIG. Ru.

Figure 3 shows a new normalization method for improving convergence coefficient judgment in square root judgment. FIG. 2 is a block diagram illustrating one example of determining an effective figure.

FIG. 4 is a block diagram showing the computer hardware architecture of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1, designated by the reference numeral 100, is a flow diagram illustrating one embodiment of the invention. It is a chart. This example uses fast combinatorial logic rather than multiple operations to Using the determination of normalized significant digits (f’) , find the new value of X, X′ (116), and use convergent division or square root test Determine the convergence coefficient used in a certain calculation decision, and use this to obtain a solution with a given accuracy. (118.120).

Convergent division and squaring using l/1 using floating point arithmetic in accordance with one embodiment of the present invention To start root determination, a numerical processor (e.g., a digital signal processor) is required. A processor) uses a processing platform to check the input X and determine whether X is ±ω, ± Equal to 0 or "Not-a-Number: N a N It is determined whether or not (102). If X equals ±ω, ±O or NaN, error - The checking mechanism is based on the basis that X is restricted to the range 0.5≦X and β and bypassing the convergence coefficient judgment (122) (however, regarding β), details are given below. explain). If X is other than ±ω, ±0 or NaN, 5.1/X is valid for X. value, modified by multiplication by an appropriate seed value S. Corrected, we obtain X in the range of 0°5≦x and β. However, β is 1.5 in the case of convergent division is assigned, and in the case of square root determination, 2.0 is assigned (103, 104 ). Under the condition that 1≦f<2, set X to X=2eXf (105), then, The processing platform checks whether 0.5≦X<1.0 (106) . If O,S≦X<1.0, the platform sets e=-1. 0 ．． If 5≦X<1.0, 1.0≦X becomes β (108), and e is set to O. is set (112), e is set (110, 112), fo is set (11 4) (However, details regarding the determination of fo will be explained below), (116) However, X' = 2"Xf'.The platform is ′ is used to determine the convergence of the called operation test, which is a convergence division or square root test. Calculate the coefficients (118).

Next, the convergence algorithm for the called arithmetic test, which is a convergent division or square root test. The algorithm is calculated and iterated (120) until a solution of a predetermined accuracy is obtained.

The convergence division test shown in FIG. 2 and represented generally by the reference numeral 200 In one example of determining the convergence coefficient for 2), the processing platform uses IEEE 754-19 using odd bias 85 floating point standard, biasing the exponent e so that the least significant bit ( Obtain (206) a biased index with LSB). biased index If the least significant bit is 1 (214), the binary f value of rl, wxyzOJ is selected (212, 213). If the least significant bit of the biased exponent is O, then [ The binary f-value of 1, lvwxyJ is selected (212, 215). binary small The selected f value to the right of the binary decimal point is inverted. (216), if the associated least significant bit is O, then f.

is a binary value r1. Ov’ w’ x’ y’ J, and the related bottom If the digit bit is 1, fo becomes [1, W + x + y)z゛ 1'' (218 ). Furthermore, the least significant bit of the biased index e is inverted (208) and f' becomes the last biased index of (210).

The collection for square root determination shown in FIG. In one embodiment of bundle coefficient determination, after e is set (112, 114), the processing The platform follows the IEEE754-1985 floating point standard using odd bias. Bias the exponent e according to the Obtain (306). (If the least significant bit of the ignored exponent is 1 (314), A binary f value of [1°vwx yzJ is selected (312, 313). by If the least significant bit of the assigned exponent is O (314), rl, 11 vwxj A binary f value is selected (312, 315). Then to the right of the binary decimal point The value of some selected f is inverted (316) and if the associated least significant bit is O , the binary value r1.00v'　w'　x'　J, and the associated least significant bit If the value is 1, it becomes "1.v'w' x' y" zIJ (318). moreover , the least significant bit of the biased index e is inverted (308) and It becomes a bias index (310).

In both convergence division and square root tests, the convergence coefficient test is Please note that it is accompanied by ra.

This one least significant bit error requires the use of one's complement arithmetic instead of two's complement. caused by. Two's complement numbers do not have a one least significant bit error, but two's complement numbers This requires upward propagation, which slows down the convergence coefficient determination speed. The one's complement is this It avoids carry propagation and is preferred because of its speed.

One least significant bit error is negligible in the convergence algorithm. This is extended precision This is because the calculation is performed using hardware and then rounded to a lower precision. be.

For X=1, 1 least significant bit error causes the result to be slightly less than 1, all That is, the value is 1 minus 1 least significant bit, and the lowest bit of the exponent is accordingly The digit bit also changes.

FIG. 4 shows a hardware architecture of the present invention, generally represented by the reference numeral 400. show. The computer program constituting the present invention is stored in a program memory (4 04), can be stored in other memory (412), and some ν) can be stored in the numerical calculation processor. By allocating the data storage means and data processing means of the It can also be implemented by hardware within the (ALU) (406). One example Then, the program control unit (402) uses the bus (41,0) to Select the computer program to run the invention and set the status register to It is determined whether ω, ±0 or N a N (408). X=±ω, ±0 or If it is NaN, the processing platform handles the error checking mechanism to Processing will stop. If X is other than +, ±O, or NaN, the ALU sets X to 0. ．． Convert to a value X such that 5≦X×β. However, multiplication by -1/X is valid. transformation, β is chosen as 1.5 for convergent division and 2 for square root determination. ．． 0 (406).

In the case of convergent division, the primary selection means of the ALU is and the secondary selection means of the ALU selects e when 1.0≦X<1.5. "0" is selected for (406). In the case of square root determination, the ALU's tertiary selection method When 0.5≦X<1.0, negative “1” is selected for e, and the fourth selection of ALU is performed. The selection means selects "0" for e when 1.0≦X<2.0 (406). child The exponent e of is odd biased based on the IEEE754-1985 floating point standard. Therefore, it is biased. ALU is f=X/2e, with the condition that 1≦f<2, Calculate the value of f and set the most significant bit "1" on the left side of the binary point and f as a sequence of binary bits consisting of the remaining binary bits on the right Output. This is generally written here as rl,vwxyzJ. (406).

In the case of convergent division, 0.5≦X<1.0 and the least significant bit of the biased exponent If the bit is equal to '0', the ALU selects the most significant bit '1' to the left of the binary point. ” and the new binary bit to the right of the binary point. Select the output consisting of rlJ on the right followed by the binary bits (40 6). In the case of convergent division, 1.0≦X<1.5 and the maximum of the biased exponent If the lower bit is equal to 1, the ALU selects the most significant bit r to the left of the binary point. lJ and the new binary bit to the right of the binary point. The first second binary bit to the right of the number point and all subsequent binary bits An output consisting of bits and '0' is selected (406).

In the case of square root judgment, 0.5≦X<1.0 and the lowest biased index If the bit is equal to rOJ, the ALU selects the most significant bit to the left of the binary point. 1” and two 1’s as new binary bits to the right of the binary point. and all subsequent bits (406). Square root determination If 1.0≦x2゜O and the least significant bit of the biased exponent is 1. If equal, the ALU selects the most significant bit '1' to the left of the binary point and the binary first the new binary bits to the right of the binary point. Select the output consisting of all bits (406). Then, the ALU performs the above Inverts all bits to the right of the binary decimal point for all arithmetic decisions. Then, f' is output (406). Also, ALU is at the bottom of the biased index. The complement of the digit bit is taken and a new biased exponent is calculated (406).

For all such decisions, the ALU calculates X. However, X’=2″ Xf" (406). In the case of convergent division, the ALU uses the convergence coefficient r2.0-X' In the case of square root determination, ALU uses a convergence coefficient r1.5-0.5X' (406). An ALU utilizes one or more data processing and data storage devices. the convergent division algorithm with the associated convergence factor until a solution of a given accuracy is obtained. Calculation of algorithm or square root determination is performed (406).

abstract Fast processors utilize combinatorial logic and range constraints on modified input values to achieve convergence. Improve efficiency in determining convergence coefficients for division and square root determinations. Input value (101) is modified to a value within a limited range and then split into two parts. (106, 108). Using these two parts, the processing platform Converges by inverting selected binary bits to generate modified coefficients Minimize the time consumption in coefficient determination and use the modified coefficients to To speed up the calculation of bundle coefficients (118°120).

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Claims (10)

[Claims] 1. A numerical processor that: For operation judgments such as convergence division judgment or square root judgment, ±∞, ±0 or numerical value Process the convergence coefficient using input values other than Not-a-Number (NaN) processing platform, where the lower bound is greater than or equal to 0.5 and the upper bound is X is limited to a range in which β is determined at least in part by the extracted arithmetic decision. The input value is modified to the value X so that the platform: A) The first option is to select an input value other than ±∞, ±0 or NaN in response to the input value. means of choice; B) In response to the first selection means, β is a constant value related to the calculation determination. The input value to convert the selected input value to the value X such that 0.5≦X<β. conversion means; C) exponent means for selecting the value of the index e in response to the input value conversion means; D) In response to the input value conversion means and the exponent means, 1≦f<2 and f is the most significant byte. A set of binary bits consisting of a binary bit and the remaining binary bits. E) first determining means for determining the value of f where f=X/2e, as expressed by In response to the 1 determining means, the most significant bit of f, which is ``1'', is placed immediately to the left of the binary point. and the remaining binary of f. Placer that places bits to the right of the binary decimal point Stage; F) In response to the arrangement means and the first determination means, the buffer is determined according to the value of X and the calculation determination. second selection means for selecting the binary bit to the right of the inline decimal point; G) in response to the second selection means, select the selected binary bit to the right of the binary point; H) In response to the complement means, the most significant bit of f is 1'' and the one's complement of the selected binary bit to create the new value of f. I) In response to the combination means, X′=2e×f′ a second determination means for determining a new value of X, X′, so that J) In response to the second determining means, in the case of convergent division, Y = 2.0-X', and the square root In the case of judgment, the third judgment generates the convergence coefficient Y so that Y=1.5-0.5X'. A numerical arithmetic processor characterized in that it is comprised of; 2. The first selection means for determining that the input value is other than ±∞, ±0 or NaN is , a processing platform that performs error checking processing, and has an upper limit of : In the case of convergent division operation judgment, β = 1.5; and in the case of square root operation judgment, β 2. The device according to claim 1, wherein one of: =2.0; 3. The exponent means for selecting the value of the exponent e: A) in response to the input value conversion means, In order to satisfy 0.5≦X<1.0 in calculation judgment, the value of e of the value of 1”; primary selection means for selecting “1”; B) In response to the input value conversion means, in the convergence division judgment, 1.0≦X<1.5. secondary selection means for selecting "0" as the value of e for the value of X; C) In response to the input value conversion means, 0.5≦X<1.0 in square root determination. tertiary selection means for selecting negative "1" as the value of e of the value of X; D) In response to the input value conversion means, 1.0≦X<2.0 in square root determination. Quaternary selection means for selecting "0" as the value of e for the value of X; composed of Select the binary bit to the right of the binary decimal point according to the value of The second selection means for selecting is: AA) 0.5≦X<1.0 in the convergence division judgment. As the output of the new binary bit to the right of the binary point for the range of ``1'' to the right of the binary point and the first second and subsequent all binary bits; BB) In the convergence division judgment, for the range of X where 1.0≦X<1.5, to the right of the binary point as the output of the new binary bit to the right of the null point. the first second and all subsequent binary bits; CC) square root value For the range of X where 0.5≦X<1.0 in the As the output of new binary bits, first the two to the right of the binary point are "1" and all subsequent bits; and DD) 1. in square root determination. For a range of X where 0≦X<2.0, the new binary As the output of the re-bit, all the bits initially to the right of the binary point; 2. The device according to claim 1, wherein the device outputs: 4. the one's complement of the selected binary bits to the right of the binary point the means comprising inverting all bit values to the right of the binary point; Furthermore, the convergence coefficient is have a means of repeating the determination; Additionally, you can allocate one or more data processing and data storage devices to Repeat the determination of the convergence coefficient until a solution with a predetermined accuracy is obtained for the type of determination made. consisting of the steps of; Furthermore, the computer program storage medium itself performs the processing of convergence coefficients. uni, a first selection means, an input value conversion means, an index means, a first determination means, and an arrangement of the device; means, second selection means, complement means, combination means, second judgment means and third judgment means have a computer program storage medium containing a fixed hardware configuration of and further, that the computer program storage medium itself is capable of processing convergence factors; computer program application of the process performed by the device, so as to have a computer program storage medium containing an application; 2. The device according to claim 1, wherein the device is one of: 5. computer program application of the process performed by the device; a first selection means, an input value conversion means, an index means, First determination means, arrangement means, second selection means, complement means, combination means, second determination means and at least a part of the fixed hardware configuration of the third determination means. computer program storage medium, and these two parts cooperate with each other. 2. The device according to claim 1, further comprising a step of processing convergence coefficients using a method of calculating convergence coefficients. 6. β whose lower limit is 0.5 or more and whose upper limit is determined by the operation judgment called ±∞, ±0 so that X is limited to a certain range and X=2e×f. or an arithmetic judgment that is a convergence division or square root judgment for an input value X other than NaN. The effectiveness of floating point arithmetic with convergence factors of 2.0- In order to streamline and improve the data storage means and data of the numerical calculation processor, A method of allocating a processing means: A) allocating one or more data input devices to store input value X ; B) Check one or more data points to determine if the input value is not ±∞, ±0 or NaN. allocating data processing devices; C) β is a constant value related to calculation judgment, and input so that 0.5≦X<β one or more data processing and data storage devices to convert value X to value Assigning stage; D) one or more data processing and data storage devices to select the value of the exponent e. E) f=X/2e, where 1≦f<2 and f is A set of binary bits consisting of the most significant bit and the remaining binary bits One or more data processing and data storage steps are performed to determine the value of f, which is expressed as Assigning devices; F) Set the most significant bit of f to 1 and set the remaining binary bits of f to binary Set up one or more data processing and data storage devices to the right of several points. Assigning stage; G) to the right of the binary decimal point, based on the value of One or more data processing and data storage devices to select binary bits. Stage of allocating chairs; H) One's complement for selected binary bits to the right of the binary decimal point allocating one or more data processing and data storage devices to take ;I) the most significant bit of f that is ``1'' and the 1 complement of the selected binary bit; In order to find the new value f′ of f by combining the numbers, one or more data allocating processing and data storage devices; J) One or more pieces of data to find a new value X' of X where X'=2e×f' allocating processing and data storage devices; and K) In the case of convergent division, Y = 2.0-X', and in the case of square root determination, Y = 1.5-0 ．． 5X', one or more data processing and The stage of scraping the data storage device; A method characterized by comprising: 7. The convergence coefficient is Allocate one or more data processing and data storage devices to iterate the determination. 7. The method of claim 6, further comprising the step of: 8. Just as the computer program storage medium itself can execute the program, a computer comprising a fixed hardware configuration of the computer program of the method; 7. A method according to claim 6, characterized in that it comprises: - a program storage medium. 9. Just as the computer program storage medium itself can execute the program, A computer program containing a computer program application of the method. 7. The method according to claim 6, further comprising a program storage medium. 10. A computer program application for processing performed by the device. a first selection means, an input value conversion means, and an index means of the device; , first determination means, arrangement means, second selection means, complement means, combination means, second determination means and at least a part of a fixed hardware configuration of the third determining means. a computer program storage medium, the two parts cooperating with each other. 7. A method as claimed in claim 6, characterized in that the convergence coefficients are processed as follows.