CA2050353C - Method and processor for high-speed convergence factor determination - Google Patents
Method and processor for high-speed convergence factor determinationInfo
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- CA2050353C CA2050353C CA002050353A CA2050353A CA2050353C CA 2050353 C CA2050353 C CA 2050353C CA 002050353 A CA002050353 A CA 002050353A CA 2050353 A CA2050353 A CA 2050353A CA 2050353 C CA2050353 C CA 2050353C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/535—Dividing only
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/552—Powers or roots, e.g. Pythagorean sums
- G06F7/5525—Roots or inverse roots of single operands
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
- G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
- G06F7/487—Multiplying; Dividing
- G06F7/4873—Dividing
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Abstract
A high-speed processor utilizes combinational logic and range limitation for a modified input value to increase efficiency in convergence factor determination for convergent division and square root computation. An input value (101) is modified to a value in a limited range (104), which is then partitioned into two subdivisions (106, 108). By utilizing these two groupings, the processing platform minimizes time consumption in conversion factor determination by inverting selected binary bits to form a modified factor (114) and utilizes that modified factor to facilitate high-speed convergence factor computation.
Description
wo 91/10188 1;;~ 53 Pcr/usso/07034 METHOD AND PROCESSOR FOR
HIGH-SPEED CONVERGENCE FACTOR
DETERMINATION
Traditional implementations of floating-point convergent division algorithms and square root algorithm determinations are hampered by the lack of efficient computation of l 0 convergence factors within both algorithm~. Convergence algorithms utilize repeated multiplication to achieve results of a predetermined accuracy. A feasible range of a modified input value, X, has been shown to be O ~ X < 2. Further limitation of such a rangc would expedite algorithmic l 5 determinations.
In add tion, determination of a convergence factor for convergent di ision generally requires a normalization step, a subtraction operation requiring a carry-propagate step, and another normalization stcp. Determination of a convergence 0 factor for a square root computation, in addition~ requires a scaling computation. Evaluation of a convergence factor for both thc convergent division and the square root determination thus requires more computation cycles than a f!oating-point multiplication computation. Because the convergence factors 2 5 occur serially in both computations, the inefffciency of the computation of the convergence factors has directly reduced the efficiency of computation within both the convergent division and square root determination algorithms.
The necd exists for a more efficient method of 30 determining convergencc factors for convergent division ~nd for square root determination to facilitate these two over-all processes within a digital platform~
. :
i WO 91tlO188 . PCr/US9~)/07034 ~:~35~7~ ~3 2 ;
Summarv of the In~ention The present invention enhances the efficiency of determining convergence factors for floating-point conver~ent `.
division and square root determination in a numeric processor, such as a digital signal processor, by expediting the convergence factor determinations via combinational logic and by assuming a limited range for a modified input value for a convergence factor determination. This approach avoids a subtraction and carry-propagation operation, thereby allowing both convergent algorithm computations to be limited primarily by a multiplier latency time factor.
~ri~f DescriDtion of the Drawin~s FIG. I is a block diagram depicting one embodiment of the invention.
FIG. 2 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing - convergence factor de~ermination in a convergent division computation .
FIG. 3 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergencc factor determination in a square root determination.
FIG. 4 is block diagram of a computer hardware 2 5 implementation of the invention.
~est Mode For CarrvinQ out the ln~en~ion FIG. 1, gcnerally depicted by the numeral 100, is a flow chart setting forth one embodiment of the present invention 3 0 that utilizes determination of a ncw normalized significand (f) via an expedient combinational logic, as opposed to multiple operations, to determine a new value for X (116), being X', and -~ obtains a conYergence factor utilized in a mathematical ;~ determination, being convcrgent division or square root WO 91/10188 PCl/US90/07034 determination, that is iterated until a solution with a predetermined degree of accuracy is obtained ( I 18, 120).
To commence convergent division and square root S determination utilizing floating-point arithmetic in accordance with one embodiment of the invention, a numeric processor (such as a digital signal processor) utilizes a processing platform to check an input X to determine whether or not X is equal to + ~, + O, or Not-a-Number (NaN) (102). If X is equal to +oo, +0, or NaN, an error-check mechanism bypasses convergence factor determination according to a rationale tha utilizes a range limitation of X to O.S < X < B (122, B being set out more specifically below). If X is other than + oo, +0, or NaN~ X is modified by multiplication by a suitable seed value S, 1 S S - l/X being a workable value, to obtain an X in a range of 0.5 < X < B such that B is assigned 1.5 for convergent division and 2.0 for square root determination (103, 104)~ Set X to X =
2e ~ f, provided that 1 < f < 2 (lOS). The processing platform then checks whether or not 0.5 < X < 1.0 (106). If O.S < X <
1.0, the platform sets e = -1 (110). If it is not true that O.S < X
< 1.0, then 1.0 X < B (108), and e is set to O (112). When e has been set (110, 112), f' is determined (114; additional detail :: ~ ; regarding the determination of f will be provided below), and X' is also~determined (116)~ where X' = 2e~ f l`he platform : 25 utilizcs X' to compute a convergence factor for the :: ~ mathematical detetmination being invoked, being convergent : division: or square root determination (118). Then a convcrgencc algorithm is computed for the mathematical determination being invoked, convergent division or square 3 0 root determinatic . and is itcrated until a solution with a predetcrmined degree of accuracy is obtained ( 120).
` :: In one cmbodiment of a convergence factor ~: determination for a convergent division determination, set forth in FIG. 2 and depicted generally by the numeral '~00, -:, wo gl/10188 ;~ ,3~ Pcr/US90/07034 after e has been set ( 1 10, 1 12), the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating-point standard using an odd bias, yielding a biased exponent with a least significant bit (lsb)(206). If the least signi~lcant bit r 5 of the biased exponent is 1 (214J, a binary f value of l.wxyzO is selected (212, 213). If the least significant bit of the biased exponent is 0, a binary f value of l .1 vwxy is selected (212, 215). The selected value of f to the right of the binary decimal ,~ is inverted (216) to yield a binary number of 1.0v'w'x'y' for f if the related least significant bit is 0 and 1.w'x'y'z'1 for f if the related least significant bit is 1 (218). In addition, the least significant bit of the biased exponent e is inverted (208~ to form a final biased exponent for f (21Q).
In one embodiment of a convergence factor determination for a square root determination, set forth in FIG.
3 and depicted generally by the numeral 300, after e has been set (112, 114), the proccssing platforrn biases the exponent e in accordance with thc IEEE 754-1985 floating-point standard using an odd bias, yielding a biased exponent with a least significant bit (306). If the least significant bit of the biased ~- ~ exponent is 1 (3l4), a binary f value of l.vwxyz is selected `~ (312, 313). If thc least significant bit of the biased exponent is ` ~ 0 (314), a binary f valuc of l.llvwx is selected (312, 3I5).
The selected value of f to thc rigbt of the binary decimal is 2 5 then invertcd (316) to yield a binary number of 1.00v'w'x' if the related Icast signîficant bit is 0 and l.v'w'x'y'z' if the relatcd least significant bît is 1 (318). In addîtion, the least sîgnificant bit of thc bîased exponent e is inverted (308) to form a final biased cxponent for f' (310?.
3 0 It should be noted that, both in convergent divîsion and square root determînation, convergence factor determination wîll incur one lsb of error, The cause of the onc lsb of error is due to the usc of the one's complement rather than the two's complement opcratîon. While the two's complement wîll not ~' WO 91/10188 PCT~/US90/07034 35~
give the one lsb of error, the two's complement requires a carry propagation which slows down the convergencc factor determination. The one's complement avoids this carry ~
propagation and is preferred because of its speed. The one lsb S of error is negligible in convergence algorithms since the computation is typically performed using extended precision hardware and is then rounded to a lower precision.
In the case of X = 1, the onc lsb ot error will cause the result to be slightly less than one, speci~lcally, one lsb less than 10 one, and the exponent lsb changes accordingly.
FIG. 4 depicts a hardware implementation of the present invention, generally depicted by the numeral 400. A computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or 15 may be embodied in hardware in the arithmetic logic unit (ALU) (406) by allocation of data storage means and data manipulation means of a numeric processor. In one embodiment, the program contro I unit (402) utilizes the bus (410) to select a computer program to implement the present 0 invention, and the status register determines whether X = + ~.
+ O, or NaN (408). If X - + ~, :i: 0, or NaN, a processing platform processes an error-check mechanism, and processing - stops. If X is other than ~ 0, or NaN, the ALU converts X
to a value X such that O.S S X < B, where multiplication by 25 -1/X is a workabl`e conversion and ~ is selected as 1.5 for convergent division and as 2.0 for square root determination (406).
Por convergent division a primary selecting means of the ALU selects a valuc of negative one for e where O.S S X c 1.0, 30 and a secondary selecting means of the ALU selects a value of zero for e where 1.0 S X ~ 1.5 (406). For square root determination a tertiary selecting means of the ALU selects a value of ncgative one for e where 0.5 S X < 1.0, and a quaternary means of the ALU selec~s a value of zero for e wo 91/101~8 Pcr/usso/0703 where l.0 S X < 2.0 (406). This exponent e is biascd with an odd bias value according to the IEEE 754-1985 floating-point standard. The ALU computes a value of f, where f = X/2 provided that 1 ~i f < 2, and outputs f as a series of binary bits consisting of a most significant bit, being one, to the left of a point and remaining binary bits to the nght of the binary point.
generally descnbed here as l.vwxyz (406). For convergent division and 0.5 S X ~ l.0 such that the lsb of the biased exponent is equal to zero, the ALU selects an output of a most signi~lcant binary bit of one to the left of the binary point and of one followed by the binary bits to the right of the binary point for the new binary bits to the right of the binary point (406). For convergent division and l.0 < X < l.5 such that the lsb of the biased exponent is equal to l, the ALU selects an l 5 output of a most significant binary bit of one to the left of the binary point and of the initially second and all following binary ~: bits to the right of the binary decimal point together with a zero for thc new binary bits to the right of thc binary point (406).
For squarc root determination and 0.5 c X < l.0 such that the lsb of biased exponent is equal to zero, the ALU selects an output of a most significant binary bit of one to thc left of the binary point and of two ones followed by all bits initially to the right of thc binary decimal for the new binary bits to the '7 S right of thc binary point (406). For square root detcrmination and l.0 S X < 2.0 such that thc lsb of the biased exponent is equal to one, the ALU sclccts an output of a most significant binary bit of onc to thc left of the binary point and of all bits initially to the right of the binary point for thc ncw binary bits 3 0 to the right of thc binary point (406). Thè ALU then inverts all bits to the right of thc binary decimal point for all mathcmatical dcterminations described abo-le, the output being f (406). The ALU also complements the lsb of the biased exponent to dcterminc the new biased exponent (406).
~0 91/10188 PCI/US90/07034 3~J~3 For all such determinations, the ALU determines X', where X' = 2e ~ f (406). For convergent division the ALU
determines a convergence factor of 2.0 - X' and for square~ root determination the ALU deaérmines a convergence factor of 1.5 5 - O.5X' (406~. The ALU utilizes one or more data manipulation and storage devices for computing a convergent division algorithm or a square root determination employing a related convergence factor until a solution with a predetermined degree of accuracy is obtained (406). :~
What is claimed is: ;
HIGH-SPEED CONVERGENCE FACTOR
DETERMINATION
Traditional implementations of floating-point convergent division algorithms and square root algorithm determinations are hampered by the lack of efficient computation of l 0 convergence factors within both algorithm~. Convergence algorithms utilize repeated multiplication to achieve results of a predetermined accuracy. A feasible range of a modified input value, X, has been shown to be O ~ X < 2. Further limitation of such a rangc would expedite algorithmic l 5 determinations.
In add tion, determination of a convergence factor for convergent di ision generally requires a normalization step, a subtraction operation requiring a carry-propagate step, and another normalization stcp. Determination of a convergence 0 factor for a square root computation, in addition~ requires a scaling computation. Evaluation of a convergence factor for both thc convergent division and the square root determination thus requires more computation cycles than a f!oating-point multiplication computation. Because the convergence factors 2 5 occur serially in both computations, the inefffciency of the computation of the convergence factors has directly reduced the efficiency of computation within both the convergent division and square root determination algorithms.
The necd exists for a more efficient method of 30 determining convergencc factors for convergent division ~nd for square root determination to facilitate these two over-all processes within a digital platform~
. :
i WO 91tlO188 . PCr/US9~)/07034 ~:~35~7~ ~3 2 ;
Summarv of the In~ention The present invention enhances the efficiency of determining convergence factors for floating-point conver~ent `.
division and square root determination in a numeric processor, such as a digital signal processor, by expediting the convergence factor determinations via combinational logic and by assuming a limited range for a modified input value for a convergence factor determination. This approach avoids a subtraction and carry-propagation operation, thereby allowing both convergent algorithm computations to be limited primarily by a multiplier latency time factor.
~ri~f DescriDtion of the Drawin~s FIG. I is a block diagram depicting one embodiment of the invention.
FIG. 2 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing - convergence factor de~ermination in a convergent division computation .
FIG. 3 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergencc factor determination in a square root determination.
FIG. 4 is block diagram of a computer hardware 2 5 implementation of the invention.
~est Mode For CarrvinQ out the ln~en~ion FIG. 1, gcnerally depicted by the numeral 100, is a flow chart setting forth one embodiment of the present invention 3 0 that utilizes determination of a ncw normalized significand (f) via an expedient combinational logic, as opposed to multiple operations, to determine a new value for X (116), being X', and -~ obtains a conYergence factor utilized in a mathematical ;~ determination, being convcrgent division or square root WO 91/10188 PCl/US90/07034 determination, that is iterated until a solution with a predetermined degree of accuracy is obtained ( I 18, 120).
To commence convergent division and square root S determination utilizing floating-point arithmetic in accordance with one embodiment of the invention, a numeric processor (such as a digital signal processor) utilizes a processing platform to check an input X to determine whether or not X is equal to + ~, + O, or Not-a-Number (NaN) (102). If X is equal to +oo, +0, or NaN, an error-check mechanism bypasses convergence factor determination according to a rationale tha utilizes a range limitation of X to O.S < X < B (122, B being set out more specifically below). If X is other than + oo, +0, or NaN~ X is modified by multiplication by a suitable seed value S, 1 S S - l/X being a workable value, to obtain an X in a range of 0.5 < X < B such that B is assigned 1.5 for convergent division and 2.0 for square root determination (103, 104)~ Set X to X =
2e ~ f, provided that 1 < f < 2 (lOS). The processing platform then checks whether or not 0.5 < X < 1.0 (106). If O.S < X <
1.0, the platform sets e = -1 (110). If it is not true that O.S < X
< 1.0, then 1.0 X < B (108), and e is set to O (112). When e has been set (110, 112), f' is determined (114; additional detail :: ~ ; regarding the determination of f will be provided below), and X' is also~determined (116)~ where X' = 2e~ f l`he platform : 25 utilizcs X' to compute a convergence factor for the :: ~ mathematical detetmination being invoked, being convergent : division: or square root determination (118). Then a convcrgencc algorithm is computed for the mathematical determination being invoked, convergent division or square 3 0 root determinatic . and is itcrated until a solution with a predetcrmined degree of accuracy is obtained ( 120).
` :: In one cmbodiment of a convergence factor ~: determination for a convergent division determination, set forth in FIG. 2 and depicted generally by the numeral '~00, -:, wo gl/10188 ;~ ,3~ Pcr/US90/07034 after e has been set ( 1 10, 1 12), the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating-point standard using an odd bias, yielding a biased exponent with a least significant bit (lsb)(206). If the least signi~lcant bit r 5 of the biased exponent is 1 (214J, a binary f value of l.wxyzO is selected (212, 213). If the least significant bit of the biased exponent is 0, a binary f value of l .1 vwxy is selected (212, 215). The selected value of f to the right of the binary decimal ,~ is inverted (216) to yield a binary number of 1.0v'w'x'y' for f if the related least significant bit is 0 and 1.w'x'y'z'1 for f if the related least significant bit is 1 (218). In addition, the least significant bit of the biased exponent e is inverted (208~ to form a final biased exponent for f (21Q).
In one embodiment of a convergence factor determination for a square root determination, set forth in FIG.
3 and depicted generally by the numeral 300, after e has been set (112, 114), the proccssing platforrn biases the exponent e in accordance with thc IEEE 754-1985 floating-point standard using an odd bias, yielding a biased exponent with a least significant bit (306). If the least significant bit of the biased ~- ~ exponent is 1 (3l4), a binary f value of l.vwxyz is selected `~ (312, 313). If thc least significant bit of the biased exponent is ` ~ 0 (314), a binary f valuc of l.llvwx is selected (312, 3I5).
The selected value of f to thc rigbt of the binary decimal is 2 5 then invertcd (316) to yield a binary number of 1.00v'w'x' if the related Icast signîficant bit is 0 and l.v'w'x'y'z' if the relatcd least significant bît is 1 (318). In addîtion, the least sîgnificant bit of thc bîased exponent e is inverted (308) to form a final biased cxponent for f' (310?.
3 0 It should be noted that, both in convergent divîsion and square root determînation, convergence factor determination wîll incur one lsb of error, The cause of the onc lsb of error is due to the usc of the one's complement rather than the two's complement opcratîon. While the two's complement wîll not ~' WO 91/10188 PCT~/US90/07034 35~
give the one lsb of error, the two's complement requires a carry propagation which slows down the convergencc factor determination. The one's complement avoids this carry ~
propagation and is preferred because of its speed. The one lsb S of error is negligible in convergence algorithms since the computation is typically performed using extended precision hardware and is then rounded to a lower precision.
In the case of X = 1, the onc lsb ot error will cause the result to be slightly less than one, speci~lcally, one lsb less than 10 one, and the exponent lsb changes accordingly.
FIG. 4 depicts a hardware implementation of the present invention, generally depicted by the numeral 400. A computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or 15 may be embodied in hardware in the arithmetic logic unit (ALU) (406) by allocation of data storage means and data manipulation means of a numeric processor. In one embodiment, the program contro I unit (402) utilizes the bus (410) to select a computer program to implement the present 0 invention, and the status register determines whether X = + ~.
+ O, or NaN (408). If X - + ~, :i: 0, or NaN, a processing platform processes an error-check mechanism, and processing - stops. If X is other than ~ 0, or NaN, the ALU converts X
to a value X such that O.S S X < B, where multiplication by 25 -1/X is a workabl`e conversion and ~ is selected as 1.5 for convergent division and as 2.0 for square root determination (406).
Por convergent division a primary selecting means of the ALU selects a valuc of negative one for e where O.S S X c 1.0, 30 and a secondary selecting means of the ALU selects a value of zero for e where 1.0 S X ~ 1.5 (406). For square root determination a tertiary selecting means of the ALU selects a value of ncgative one for e where 0.5 S X < 1.0, and a quaternary means of the ALU selec~s a value of zero for e wo 91/101~8 Pcr/usso/0703 where l.0 S X < 2.0 (406). This exponent e is biascd with an odd bias value according to the IEEE 754-1985 floating-point standard. The ALU computes a value of f, where f = X/2 provided that 1 ~i f < 2, and outputs f as a series of binary bits consisting of a most significant bit, being one, to the left of a point and remaining binary bits to the nght of the binary point.
generally descnbed here as l.vwxyz (406). For convergent division and 0.5 S X ~ l.0 such that the lsb of the biased exponent is equal to zero, the ALU selects an output of a most signi~lcant binary bit of one to the left of the binary point and of one followed by the binary bits to the right of the binary point for the new binary bits to the right of the binary point (406). For convergent division and l.0 < X < l.5 such that the lsb of the biased exponent is equal to l, the ALU selects an l 5 output of a most significant binary bit of one to the left of the binary point and of the initially second and all following binary ~: bits to the right of the binary decimal point together with a zero for thc new binary bits to the right of thc binary point (406).
For squarc root determination and 0.5 c X < l.0 such that the lsb of biased exponent is equal to zero, the ALU selects an output of a most significant binary bit of one to thc left of the binary point and of two ones followed by all bits initially to the right of thc binary decimal for the new binary bits to the '7 S right of thc binary point (406). For square root detcrmination and l.0 S X < 2.0 such that thc lsb of the biased exponent is equal to one, the ALU sclccts an output of a most significant binary bit of onc to thc left of the binary point and of all bits initially to the right of the binary point for thc ncw binary bits 3 0 to the right of thc binary point (406). Thè ALU then inverts all bits to the right of thc binary decimal point for all mathcmatical dcterminations described abo-le, the output being f (406). The ALU also complements the lsb of the biased exponent to dcterminc the new biased exponent (406).
~0 91/10188 PCI/US90/07034 3~J~3 For all such determinations, the ALU determines X', where X' = 2e ~ f (406). For convergent division the ALU
determines a convergence factor of 2.0 - X' and for square~ root determination the ALU deaérmines a convergence factor of 1.5 5 - O.5X' (406~. The ALU utilizes one or more data manipulation and storage devices for computing a convergent division algorithm or a square root determination employing a related convergence factor until a solution with a predetermined degree of accuracy is obtained (406). :~
What is claimed is: ;
Claims (17)
1. A numeric processor comprising:
a processing platform for processing convergence factors utilizing an input value other than + ?, ? 0, or Not-a-Number (NaN), for a mathematical determination, being convergent division determination or square root determination, wherein the input value is modified to a value X, such that X is limited to a range with a lower limit greater than or equal to 0.5 and an upper limit B determined, at least in part, by the mathematical determination invoked and such that X is defined as X = 2e * f, said platform comprising:
A) first selecting means responsive to the input value for selecting an input value other than ? ?, ? 0, or NaN;
B) input value altering means responsive to the first selecting means for converting a selected input value to a value X such that 0.5 ? X < B, the respective value of B being a constant value related to the mathematical determination;
C) exponent means responsive to the input value altering means for selecting a value for an exponent e;
D) first determining means responsive to the input value altering means and the exponent means for determining a value for f, wherein f = X/2e such that 1? f < 2 and f is represented by a series of binary bits consisting of a most significant binary bit and remaining binary bits;
E) locating means responsive to the first determining means for placing the most significant binary bit of f, being 1, to the immediate left of a binary point with the remaining binary bits of f located to the right of the binary decimal point;
F) second selecting means responsive to the locating means and the first determining means for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination;
G) complementing means responsive to the second selecting means for determining a one's complement of the selected binary bits to the right of the binary point;
H) combining means responsive to the complementing means for combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining f, a new value for f;
I) second determining means responsive to the combining means for determining X', a new value for X, such that X' = 2e * f'; and J) third determining means responsive to the second determining means for generating a convergence factor Y such that Y = 2.0 - X' for convergent division and Y = 1.5 - 0.5X' for square root determination.
a processing platform for processing convergence factors utilizing an input value other than + ?, ? 0, or Not-a-Number (NaN), for a mathematical determination, being convergent division determination or square root determination, wherein the input value is modified to a value X, such that X is limited to a range with a lower limit greater than or equal to 0.5 and an upper limit B determined, at least in part, by the mathematical determination invoked and such that X is defined as X = 2e * f, said platform comprising:
A) first selecting means responsive to the input value for selecting an input value other than ? ?, ? 0, or NaN;
B) input value altering means responsive to the first selecting means for converting a selected input value to a value X such that 0.5 ? X < B, the respective value of B being a constant value related to the mathematical determination;
C) exponent means responsive to the input value altering means for selecting a value for an exponent e;
D) first determining means responsive to the input value altering means and the exponent means for determining a value for f, wherein f = X/2e such that 1? f < 2 and f is represented by a series of binary bits consisting of a most significant binary bit and remaining binary bits;
E) locating means responsive to the first determining means for placing the most significant binary bit of f, being 1, to the immediate left of a binary point with the remaining binary bits of f located to the right of the binary decimal point;
F) second selecting means responsive to the locating means and the first determining means for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination;
G) complementing means responsive to the second selecting means for determining a one's complement of the selected binary bits to the right of the binary point;
H) combining means responsive to the complementing means for combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining f, a new value for f;
I) second determining means responsive to the combining means for determining X', a new value for X, such that X' = 2e * f'; and J) third determining means responsive to the second determining means for generating a convergence factor Y such that Y = 2.0 - X' for convergent division and Y = 1.5 - 0.5X' for square root determination.
2. The apparatus of claim 1, wherein the first selecting means for determining that an input value is other than ? ?, ? 0, or NaN comprises a processing platform for executing an error check process.
3. The apparatus of claim 1, wherein the upper limit .beta. = 1.5 for a mathematical determination of convergent division.
4. The apparatus of claim 1, wherein the upper limit .beta. = 2.0 for a mathematical determination of a square root.
5. The apparatus of claim 1 wherein the exponent means for selecting a value for an exponent e comprises:
A) primary selecting means responsive to the input value altering means for selecting a value of negative 1 for e for values of X such that 0.5 ? X < 1.0 in convergent division determination;
B) secondary selecting means responsive to the input value altering means for selecting a value of zero for e for values of X such that 1.0 ? X < 1.5 in convergent division determination;
C) tertiary selecting means responsive to the input value altering means for selecting a value of negative 1 for e for values of X such that 0.5 < X < 1.0 in square root determination; and D) quaternary means responsive to the input value altering means for selecting a value of zero for e for values of X
such that 1.0 ? X < 2.0 in square root determination.
A) primary selecting means responsive to the input value altering means for selecting a value of negative 1 for e for values of X such that 0.5 ? X < 1.0 in convergent division determination;
B) secondary selecting means responsive to the input value altering means for selecting a value of zero for e for values of X such that 1.0 ? X < 1.5 in convergent division determination;
C) tertiary selecting means responsive to the input value altering means for selecting a value of negative 1 for e for values of X such that 0.5 < X < 1.0 in square root determination; and D) quaternary means responsive to the input value altering means for selecting a value of zero for e for values of X
such that 1.0 ? X < 2.0 in square root determination.
6. The apparatus of claim 1 wherein the second selecting means for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination outputs the following:
A) for a range of X such that 0.5 ? X < 1.0 in a convergent division determination, an output for the new binary bits to the right of the binary point being one followed by the initially second, and all following binary bits to the right of the binary point;
B) for a range of X such that 1.0 ? X < 1.5 in a convergent division determination, an output for the new binary bits to the right of the binary point being the initially second, and all following binary bits to the right of the binary point;
C) for a range of X such that 0.5 ? X < 1.0 in a square root determination, an output for the new binary bits to the right of the binary point being two ones followed by all bits initially to the right of the binary point; and D) for a range of X such that 1.0 ? X < 2.0 in a square root determination, an output for the new binary bits to the right of the binary point being all bits initially to the right of the binary point.
A) for a range of X such that 0.5 ? X < 1.0 in a convergent division determination, an output for the new binary bits to the right of the binary point being one followed by the initially second, and all following binary bits to the right of the binary point;
B) for a range of X such that 1.0 ? X < 1.5 in a convergent division determination, an output for the new binary bits to the right of the binary point being the initially second, and all following binary bits to the right of the binary point;
C) for a range of X such that 0.5 ? X < 1.0 in a square root determination, an output for the new binary bits to the right of the binary point being two ones followed by all bits initially to the right of the binary point; and D) for a range of X such that 1.0 ? X < 2.0 in a square root determination, an output for the new binary bits to the right of the binary point being all bits initially to the right of the binary point.
7. The apparatus of claim 1 wherein the complementing means for determining a one's complement of the selected binary bits to the right of the binary point comprises inverting all bit values to the right of the binary point.
8. The apparatus of claim 1 further including means for iterating a determination of the convergence factor until a solution with a predetermined degree of accuracy is reached for the mathematical determination invoked.
9. The apparatus of claim 1, further including allocating one or more data manipulation and storage devices for iterating the determination of a convergence factor until a solution with a predetermined degree of accuracy is reached for the type of determination invoked.
10. The apparatus of claim 1, further including a computer program storage medium containing a fixed hardware embodiment of the first selecting means, the input value altering means, the exponent means, the first determining means, the locating means, the second selecting means, the complementing means, the combining means, the second determining means, and the third determining means of the apparatus such that the computer program storage medium itself can implement processing of the convergence factors.
11. The apparatus of claim 1, further including a computer program storage medium containing a computer program application of the processing achieved by the apparatus such that the computer program storage medium itself can process the convergence factors.
12. The apparatus of claim 1, further including a computer program storage medium containing a combination of at least a part of a computer program application of the processing achieved by the apparatus together with at least a part of a fixed hardware embodiment of the first selecting means, the input value altering means, the exponent means, the first determining means, the locating means, the second selecting means, the complementing means, the combining means, the second determining means, and the third determining means of the apparatus such that the two parts together coordinate to process the convergence factors.
13. A method for allocating data storage means and data manipulation means of a numeric processor so as to expedite and improve floating point computation of convergence factors 2.0 -X and 1.5 - 0.5X for a mathematical determination, being convergent division or square root determination, for an input value X other than ? ?, ? 0, or NaN wherein X is limited to a certain range with a lower limit greater than or equal to 0.5 and an upper limit B determined by the mathematical determination invoked and such that X = 2e * f, said method comprising the steps of:
A ) allocating one or more data input devices for storing an input value X;
B) allocating one or more data manipulation devices for determining that input value is not ? ?, + 0, or NaN;
C) allocating one or more data manipulation and storage devices for converting an input value X to a value X
such: that 0.5 ? X < .beta., wherein .beta. is a constant value related to the mathematical determination;
D) allocating one or more data manipulation and storage devices for selecting a value for an exponent e;
E) allocating one or more data manipulation and storage devices for determining a value for f wherein f = X/2e such that 1? f < 2 and f is represented by a series of binary bits consisting of a most significant bit and remaining binary bits;
F) allocating one or more data manipulation and storage devices for setting the most significant bit of f to 1 with the remaining binary bits of f to the right of a binary decimal point;
G) allocating one or more data manipulation and storage devices for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination invoked;
H) allocating one or more data manipulation and storage devices for one's complementing the selected binary bits to the right of the binary decimal point;
I ) allocating one or more data manipulation and storage devices for combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining a new value for f, designated f;
J) allocating one or more data manipulation and storage devices for determining a new X, designated X', wherein X' = 2e * f;
and K) allocating one or more data manipulation and storage devices for generating a convergence factor Y such that Y - 2.0 - X' for convergent division and Y = 1.5 - 0.5X' for square root determination.
A ) allocating one or more data input devices for storing an input value X;
B) allocating one or more data manipulation devices for determining that input value is not ? ?, + 0, or NaN;
C) allocating one or more data manipulation and storage devices for converting an input value X to a value X
such: that 0.5 ? X < .beta., wherein .beta. is a constant value related to the mathematical determination;
D) allocating one or more data manipulation and storage devices for selecting a value for an exponent e;
E) allocating one or more data manipulation and storage devices for determining a value for f wherein f = X/2e such that 1? f < 2 and f is represented by a series of binary bits consisting of a most significant bit and remaining binary bits;
F) allocating one or more data manipulation and storage devices for setting the most significant bit of f to 1 with the remaining binary bits of f to the right of a binary decimal point;
G) allocating one or more data manipulation and storage devices for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination invoked;
H) allocating one or more data manipulation and storage devices for one's complementing the selected binary bits to the right of the binary decimal point;
I ) allocating one or more data manipulation and storage devices for combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining a new value for f, designated f;
J) allocating one or more data manipulation and storage devices for determining a new X, designated X', wherein X' = 2e * f;
and K) allocating one or more data manipulation and storage devices for generating a convergence factor Y such that Y - 2.0 - X' for convergent division and Y = 1.5 - 0.5X' for square root determination.
14. The method of claim 13, further including allocating one or more data manipulation and storage devices for iterating the determination of a convergence factor until a solution with a predetermined degree of accuracy is reached for the mathematical determination invoked.
15. The method of claim 13, further including a computer program storage medium containing a fixed hardware embodiment of a computer program of the method such that the computer program storage medium itself can execute the program.
16. The method of claim 13, further including a computer program storage medium containing a computer program application of the method such that the computer program storage medium itself can execute the program.
17. The method of claim 13, further including a computer program storage medium containing a combination of at least a part of a computer program application of the processing achieved by the apparatus together with at least a part of a fixed hardware embodiment of the first selecting means, the input value altering means, the exponent means, the first determining means, the locating means, the second selecting means, the complementing means, the combining means, the second determining means, and the third determining means of the apparatus such that the two parts together coordinate to process the convergence factors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US45891589A | 1989-12-29 | 1989-12-29 | |
| US458,915 | 1989-12-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2050353A1 CA2050353A1 (en) | 1991-06-30 |
| CA2050353C true CA2050353C (en) | 1994-08-30 |
Family
ID=23822608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002050353A Expired - Fee Related CA2050353C (en) | 1989-12-29 | 1990-12-03 | Method and processor for high-speed convergence factor determination |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0461230A4 (en) |
| JP (1) | JPH04505978A (en) |
| KR (1) | KR940008610B1 (en) |
| CA (1) | CA2050353C (en) |
| WO (1) | WO1991010188A1 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4878190A (en) * | 1988-01-29 | 1989-10-31 | Texas Instruments Incorporated | Floating point/integer processor with divide and square root functions |
| US4949296A (en) * | 1988-05-18 | 1990-08-14 | Harris Corporation | Method and apparatus for computing square roots of binary numbers |
| US5157624A (en) * | 1990-12-13 | 1992-10-20 | Micron Technology, Inc. | Machine method to perform newton iterations for reciprocal square roots |
-
1990
- 1990-12-03 CA CA002050353A patent/CA2050353C/en not_active Expired - Fee Related
- 1990-12-03 KR KR1019910701002A patent/KR940008610B1/en not_active IP Right Cessation
- 1990-12-03 JP JP3501946A patent/JPH04505978A/en active Pending
- 1990-12-03 WO PCT/US1990/007034 patent/WO1991010188A1/en not_active Application Discontinuation
- 1990-12-03 EP EP19910901464 patent/EP0461230A4/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0461230A1 (en) | 1991-12-18 |
| KR940008610B1 (en) | 1994-09-24 |
| JPH04505978A (en) | 1992-10-15 |
| EP0461230A4 (en) | 1993-08-18 |
| KR920701901A (en) | 1992-08-12 |
| WO1991010188A1 (en) | 1991-07-11 |
| CA2050353A1 (en) | 1991-06-30 |
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