EP0461230A1 - Method and processor for high-speed convergence factor determination - Google Patents

Method and processor for high-speed convergence factor determination

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Publication number
EP0461230A1
EP0461230A1 EP91901464A EP91901464A EP0461230A1 EP 0461230 A1 EP0461230 A1 EP 0461230A1 EP 91901464 A EP91901464 A EP 91901464A EP 91901464 A EP91901464 A EP 91901464A EP 0461230 A1 EP0461230 A1 EP 0461230A1
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EP
European Patent Office
Prior art keywords
binary
determination
value
selecting
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91901464A
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German (de)
French (fr)
Other versions
EP0461230A4 (en
Inventor
Brett Louis Lindsley
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Motorola Solutions Inc
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Motorola Inc
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Publication date
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Publication of EP0461230A1 publication Critical patent/EP0461230A1/en
Publication of EP0461230A4 publication Critical patent/EP0461230A4/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums
    • G06F7/5525—Roots or inverse roots of single operands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
    • G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G06F7/4873—Dividing

Definitions

  • determination of a convergence factor for convergent division generally requires a normalization step, a subtraction operation requiring a carry-propagate step, and another normalization step.
  • Determination of a convergence factor for a square root computation requires a scaling computation. Evaluation of a convergence factor for both the convergent division and the square root determination thus requires more computation cycles than a floating-point multiplication computation. Because the convergence factors occur serially in both computations, the inefficiency of the computation of the convergence factors has directly reduced the efficiency of computation within both the convergent division and square root determination algorithms. The need exists for a more efficient method of determining convergence factors for convergent division and for square root determination to facilitate these two over-all processes within a digital platform. Summary of the Invention
  • the present invention enhances the efficiency of determining convergence factors for floating-point convergent division and square root determination in a numeric processor, such as a digital signal processor, by expediting the convergence factor determinations via combinational logic and by assuming a limited range for a modified input value for a convergence factor determination.
  • This approach avoids a subtraction and carry-propagation operation, thereby allowing both convergent algorithm computations to be limited primarily by a multiplier latency time factor.
  • FIG. 1 is a block diagram depicting one embodiment of the invention.
  • FIG. 2 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergence factor determination in a convergent division computation.
  • FIG. 3 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergence factor determination in a square root determination.
  • FIG. 4 is block diagram of a computer hardware implementation of the invention.
  • FIG. 1 generally depicted by the numeral 100, is a flow chart setting forth one embodiment of the present invention that utilizes determination of a new normalized significand (f ) via an expedient combinational logic, as opposed to multiple operations, to determine a new value for X (116), being X', and obtains a convergence factor utilized in a mathematical determination, being convergent division or square root determination, that is iterated until a solution with a predetermined degree of accuracy is obtained (118, 120).
  • a numeric processor (such as a digital signal processor) utilizes a processing platform to check an input X to determine whether or not X is equal to ⁇ ⁇ , ⁇ 0, or Not-a-Number (NaN) (102). If X is equal to ⁇ «», ⁇ 0, or NaN, an error-check mechanism bypasses convergence factor determination according to a rationale that utilizes a range limitation of X to 0.5 ⁇ X ⁇ ⁇ (122, ⁇ being set out more specifically below).
  • X is other than ⁇ °°, ⁇ 0, or NaN
  • Set X to X 2 C * f, provided that 1 ⁇ f ⁇ 2 (105).
  • ⁇ X ⁇ 1.0 If it is not true that 0.5 ⁇ X ⁇ 1.0, then 1.0 ⁇ X ⁇ ⁇ (108), and e is set to 0 (112).
  • the platform utilizes X' to compute a convergence factor for the mathematical determination being invoked, being convergent division or square root determination (118). Then a convergence algorithm is computed for the mathematical determination being invoked, convergent division or square root determination, and is iterated until a solution with a predetermined degree of accuracy is obtained (120).
  • the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating ⁇ point standard using an odd bias, yielding a biased exponent with a least significant bit (lsb)(206). If the least significant bit of the biased exponent is 1 (214), a binary f value of l.wxyzO is selected (212, 213). If the least significant bit of the biased exponent is 0, a binary f value of l.lvwxy is selected (212, 215).
  • the selected value of f to the right of the binary decimal is inverted (216) to yield a binary number of l.Ov'w'x'y' for f if the related least significant bit is 0 and l.w'x'y'z'l for f if the related least significant bit is 1 (218).
  • the least significant bit of the biased exponent e is inverted (208) to form a final biased exponent for f (210).
  • the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating-point standard using an odd bias, yielding a biased exponent with a least significant bit (306). If the least significant bit of the biased exponent is 1 (314), a binary f value of l.vwxyz is selected (312 , 313). If the least significant bit of the biased exponent is 0 (314), a binary f value of l.l lvwx is selected (312 , 315).
  • the selected value of f to the right of the binary decimal is then inverted (316) to yield a binary number of l.OOv'w'x' if the related least significant bit is 0 and l .v'w'x'y'z' if the related least significant bit is 1 (318).
  • the least significant bit of the biased exponent e is inverted (308) to form a final biased exponent for f (310). It should be noted that, both in convergent division and square root determination, convergence factor determination will incur one Isb of error. The cause of the one lsb of error is due to the use of the one's complement rather than the two's complement operation.
  • the two's complement While the two's complement will not give the one lsb of error, the two's complement requires a carry propagation which slows down the convergence factor determination.
  • the one's complement avoids this carry propagation and is preferred because of its speed.
  • the one lsb of error is negligible in convergence algorithms since the computation is typically performed using extended precision hardware and is then rounded to a lower precision.
  • FIG. 4 depicts a hardware implementation of the present invention, generally depicted by the numeral 400.
  • a computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or may be embodied in hardware in the arithmetic logic unit
  • ALU (406) by allocation of data storage means and data manipulation means of a numeric processor.
  • a primary selecting means of the ALU selects a value of negative one for e where 0.5 ⁇ X ⁇ 1.0, and a secondary selecting means of the ALU selects a value of zero for e where 1.0 ⁇ X ⁇ 1.5 (406).
  • a tertiary selecting means of the ALU selects a value of negative one for e where 0.5 ⁇ X ⁇ 1.0, and a quaternary means of the ALU selects a value of zero for e where 1.0 ⁇ X ⁇ 2.0 (406).
  • This exponent e is biased with an odd bias value according to the IEEE 754-1985 floating-point standard.
  • f X/2 e provided that 1 ⁇ f ⁇ 2
  • f a series of binary bits consisting of a most significant bit, being one, to the left of a point and remaining binary bits to the right of the binary point, generally described here as l.vwxyz (406).
  • the ALU selects an output of a most significant binary bit of one to the left of the binary point and of one followed by the binary bits to the right of the binary point for the new binary bits to the right of the binary point (406).
  • the ALU selects an output of a most significant binary bit of one to the left of the binary point and of the initially second and all following binary bits to the right of the binary decimal point together with a zero for the new binary bits to the right of the binary point (406).
  • the ALU selects an output of a most significant binary bit of one to the left of the binary point and of two ones followed by all bits initially to the right of the binary decimal for the new binary bits to the right of the binary point (406).
  • the ALU selects an output of a most significant binary bit of one to the left of the binary point and of all bits initially to the right of the binary point for the new binary bits to the right of the binary point (406).
  • the ALU then inverts all bits to the right of the binary decimal point for all mathematical determinations described above, the output being f (406).
  • the ALU determines a convergence factor of 2.0 - X' and for square root determination the ALU determines a convergence factor of 1.5 - 0.5X' (406).
  • the ALU utilizes one or more data manipulation and storage devices for computing a convergent division algorithm or a square root determination employing a related convergence factor until a solution with a predetermined degree of accuracy is obtained (406).

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
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Abstract

Un processeur ultra-rapide utilise une logique combinatoire et une limitation de plage pour une valeur d'entrée modifiée, en vue d'augmenter l'efficacité de la détermination du facteur de convergence pour la division convergente et la calcul de la racine carrée. Une valeur d'entrée (101) est modifiée pour obtenir une certaine valeur dans une plage limitée (104), qui est ensuite divisée en deux subdivisions (106, 108). A l'aide de ces deux groupements, le programme de traitement réduit au minimum le temps nécessaire pour déterminer le facteur de conversion en inversant les bits binaires sélectionnés pour former un facteur modifié (114), et le programme utilise ensuite ce facteur modifié pour faciliter le calcul ultra-rapide du facteur de convergence.An ultra-fast processor uses combinational logic and range limitation for a modified input value, in order to increase the efficiency of determining the convergence factor for convergent division and the calculation of the square root. An input value (101) is changed to obtain a certain value within a limited range (104), which is then divided into two subdivisions (106, 108). Using these two groupings, the processing program minimizes the time required to determine the conversion factor by inverting the selected binary bits to form a modified factor (114), and the program then uses this modified factor to facilitate the ultra-fast calculation of the convergence factor.

Description

METHOD AND PROCESSOR FOR
HIGH-SPEED CONVERGENCE FACTOR
DETERMINATION
Background of the Invention
Traditional implementations of floating-point convergent division algorithms and square root algorithm determinations are hampered by the lack of efficient computation of convergence factors within both algorithms. Convergence algorithms utilize repeated multiplication to achieve results of a predetermined accuracy. A feasible range of a modified input value, X, has been shown to be 0 < X < 2. Further limitation of such a range would expedite algorithmic determinations.
In addition, determination of a convergence factor for convergent division generally requires a normalization step, a subtraction operation requiring a carry-propagate step, and another normalization step. Determination of a convergence factor for a square root computation, in addition, requires a scaling computation. Evaluation of a convergence factor for both the convergent division and the square root determination thus requires more computation cycles than a floating-point multiplication computation. Because the convergence factors occur serially in both computations, the inefficiency of the computation of the convergence factors has directly reduced the efficiency of computation within both the convergent division and square root determination algorithms. The need exists for a more efficient method of determining convergence factors for convergent division and for square root determination to facilitate these two over-all processes within a digital platform. Summary of the Invention
The present invention enhances the efficiency of determining convergence factors for floating-point convergent division and square root determination in a numeric processor, such as a digital signal processor, by expediting the convergence factor determinations via combinational logic and by assuming a limited range for a modified input value for a convergence factor determination. This approach avoids a subtraction and carry-propagation operation, thereby allowing both convergent algorithm computations to be limited primarily by a multiplier latency time factor.
Brief Description of the Drawing-.
FIG. 1 is a block diagram depicting one embodiment of the invention.
FIG. 2 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergence factor determination in a convergent division computation. FIG. 3 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergence factor determination in a square root determination.
FIG. 4 is block diagram of a computer hardware implementation of the invention.
Best Mode For Carrvin? out the Invention
FIG. 1, generally depicted by the numeral 100, is a flow chart setting forth one embodiment of the present invention that utilizes determination of a new normalized significand (f ) via an expedient combinational logic, as opposed to multiple operations, to determine a new value for X (116), being X', and obtains a convergence factor utilized in a mathematical determination, being convergent division or square root determination, that is iterated until a solution with a predetermined degree of accuracy is obtained (118, 120).
To commence convergent division and square root determination utilizing floating-point arithmetic in accordance with one embodiment of the invention, a numeric processor (such as a digital signal processor) utilizes a processing platform to check an input X to determine whether or not X is equal to ± ∞, ± 0, or Not-a-Number (NaN) (102). If X is equal to ±«», ±0, or NaN, an error-check mechanism bypasses convergence factor determination according to a rationale that utilizes a range limitation of X to 0.5 < X < β (122, β being set out more specifically below). If X is other than ± °°, ±0, or NaN, X is modified by multiplication by a suitable seed value S, S = 1/X being a workable value, to obtain an X in a range of 0.5 < X < β such that β is assigned 1.5 for convergent division and 2.0 for square root determination (103, 104). Set X to X = 2C * f, provided that 1 < f < 2 (105). The processing platform then checks whether or not 0.5 ≤ X < 1.0 (106). If 0.5 < X < 1.0, the platform sets e = -1 (110). If it is not true that 0.5 < X < 1.0, then 1.0 < X < β (108), and e is set to 0 (112). When e has been set (110, 112), f is determined (114; additional detail regarding the determination of f will be provided below), and X' is also determined (116), where X' = 2C * f. The platform utilizes X' to compute a convergence factor for the mathematical determination being invoked, being convergent division or square root determination (118). Then a convergence algorithm is computed for the mathematical determination being invoked, convergent division or square root determination, and is iterated until a solution with a predetermined degree of accuracy is obtained (120).
In one embodiment of a convergence factor determination for a convergent division determination, set forth in FIG. 2 and depicted generally by the numeral 200, after e has been set (110, 112), the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating¬ point standard using an odd bias, yielding a biased exponent with a least significant bit (lsb)(206). If the least significant bit of the biased exponent is 1 (214), a binary f value of l.wxyzO is selected (212, 213). If the least significant bit of the biased exponent is 0, a binary f value of l.lvwxy is selected (212, 215). The selected value of f to the right of the binary decimal is inverted (216) to yield a binary number of l.Ov'w'x'y' for f if the related least significant bit is 0 and l.w'x'y'z'l for f if the related least significant bit is 1 (218). In addition, the least significant bit of the biased exponent e is inverted (208) to form a final biased exponent for f (210).
In one embodiment of a convergence factor determination for a square root determination, set forth in FIG.
3 and depicted generally by the numeral 300, after e has been set (112, 114), the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating-point standard using an odd bias, yielding a biased exponent with a least significant bit (306). If the least significant bit of the biased exponent is 1 (314), a binary f value of l.vwxyz is selected (312 , 313). If the least significant bit of the biased exponent is 0 (314), a binary f value of l.l lvwx is selected (312 , 315). The selected value of f to the right of the binary decimal is then inverted (316) to yield a binary number of l.OOv'w'x' if the related least significant bit is 0 and l .v'w'x'y'z' if the related least significant bit is 1 (318). In addition, the least significant bit of the biased exponent e is inverted (308) to form a final biased exponent for f (310). It should be noted that, both in convergent division and square root determination, convergence factor determination will incur one Isb of error. The cause of the one lsb of error is due to the use of the one's complement rather than the two's complement operation. While the two's complement will not give the one lsb of error, the two's complement requires a carry propagation which slows down the convergence factor determination. The one's complement avoids this carry propagation and is preferred because of its speed. The one lsb of error is negligible in convergence algorithms since the computation is typically performed using extended precision hardware and is then rounded to a lower precision.
In the case of X = 1, the one lsb of error will cause the result to be slightly less than one, specifically, one lsb less than one, and the exponent lsb changes accordingly.
FIG. 4 depicts a hardware implementation of the present invention, generally depicted by the numeral 400. A computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or may be embodied in hardware in the arithmetic logic unit
(ALU) (406) by allocation of data storage means and data manipulation means of a numeric processor. In one embodiment, the program control unit (402) utilizes the bus (410) to select a computer program to implement the present invention, and the status register determines whether X = ± °°,
± 0, or NaN (408). If X = ± ∞, ± 0, or NaN, a processing platform processes an error-check mechanism, and processing stops. If X is other than ± ∞, ± 0, or NaN, the ALU converts X to a value X such that 0.5 < X < β, where multiplication by =*1/X is a workable conversion and β is selected as 1.5 for convergent division and as 2.0 for square root determination (406).
For convergent division a primary selecting means of the ALU selects a value of negative one for e where 0.5 < X < 1.0, and a secondary selecting means of the ALU selects a value of zero for e where 1.0 ≤ X < 1.5 (406). For square root determination a tertiary selecting means of the ALU selects a value of negative one for e where 0.5 < X < 1.0, and a quaternary means of the ALU selects a value of zero for e where 1.0 < X < 2.0 (406). This exponent e is biased with an odd bias value according to the IEEE 754-1985 floating-point standard. The ALU computes a value of f, where f = X/2e provided that 1 < f < 2, and outputs f as a series of binary bits consisting of a most significant bit, being one, to the left of a point and remaining binary bits to the right of the binary point, generally described here as l.vwxyz (406). For convergent division and 0.5 < X < 1.0 such that the lsb of the biased exponent is equal to zero, the ALU selects an output of a most significant binary bit of one to the left of the binary point and of one followed by the binary bits to the right of the binary point for the new binary bits to the right of the binary point (406). For convergent division and 1.0 ≤ X < 1.5 such that the lsb of the biased exponent is equal to 1, the ALU selects an output of a most significant binary bit of one to the left of the binary point and of the initially second and all following binary bits to the right of the binary decimal point together with a zero for the new binary bits to the right of the binary point (406). For square root determination and 0.5 < X < 1.0 such that the lsb of biased exponent is equal to zero, the ALU selects an output of a most significant binary bit of one to the left of the binary point and of two ones followed by all bits initially to the right of the binary decimal for the new binary bits to the right of the binary point (406). For square root determination and 1.0 < X < 2.0 such that the lsb of the biased exponent is equal to one, the ALU selects an output of a most significant binary bit of one to the left of the binary point and of all bits initially to the right of the binary point for the new binary bits to the right of the binary point (406). The ALU then inverts all bits to the right of the binary decimal point for all mathematical determinations described above, the output being f (406). The ALU also complements the lsb of the biased exponent to determine the new biased exponent (406). For all such determinations, the ALU determines X', where X' = 2C * f (406). For convergent division the ALU determines a convergence factor of 2.0 - X' and for square root determination the ALU determines a convergence factor of 1.5 - 0.5X' (406). The ALU utilizes one or more data manipulation and storage devices for computing a convergent division algorithm or a square root determination employing a related convergence factor until a solution with a predetermined degree of accuracy is obtained (406). What is claimed is:

Claims

Claims
1. A numeric processor comprising: a processing platform for processing convergence factors utilizing an input value other than ± <», ± 0, or Not-a-Number (NaN), for a mathematical determination, being convergent division determination or square root determination, wherein the input value is modified to a value X, such that X is limited to a range with a lower limit greater than or equal to 0.5 and an upper limit β determined, at least in part, by the mathematical determination invoked and such that X is defined as X = 2e * f, said platform comprising:
A) first selecting means responsive to the input value for selecting an input value other than ± °°, ± 0, or NaN;
B) input value altering means responsive to the first selecting means for converting a selected input value to a value
X such that 0.5 < X < β, the respective value of β being a constant value related to the mathematical determination; O exponent means responsive to the input value altering means for selecting a value for an exponent e; D) first determining means responsive to the input value altering means and the exponent means for determining a value for f, wherein f = X/2e such that 1< f < 2 and f is represented by a series of binary bits consisting of a most significant binary bit and remaining binary bits; E) locating means responsive to the first determining means for placing the most significant binary bit of f, being 1, to the immediate left of a binary point with the remaining binary bits of f located to the right of the binary decimal point; F) second selecting means responsive to the locating means and the first determining means for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination; G) complementing means responsive to the second selecting means for determining a one's complement of the selected binary bits to the right of the binary point;
H) combining means responsive to the complementing means for combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining f , a new value for f;
I) second determining means responsive to the combining means for determining X', a new value for X, such that X* = 2β * f ; and
J) third determining means responsive to the second determining means for generating a convergence factor Y such that Y = 2.0 - X' for convergent division and Y = 1.5 - 0.5X* for square root determination.
2. The apparatus of claim 1, wherein the first selecting means for determining that an input value is other than ± «*>, ± 0, or NaN comprises a processing platform for executing an error check process.
3. The apparatus of claim 1, wherein the upper limit β = 1.5 for a mathematical determination of convergent division.
4. The apparatus of claim 1, wherein the upper limit β = 2.0 for a mathematical determination of a square root.
5. The apparatus of claim 1 wherein the exponent means for selecting a value for an exponent e comprises:
A) primary selecting means responsive to the input value altering means for selecting a value of negative 1 for e for values of X such that 0.5 < X < 1.0 in convergent division determination; B) secondary selecting means responsive to the input value altering means for selecting a value of zero for e for values of X such that 1.0 < X < 1.5 in convergent division determination;
Q tertiary selecting means responsive to the input value altering means for selecting a value of negative 1 for e for values of X such that 0.5 < X < 1.0 in square root determination; and
D) quaternary means responsive to the input value altering means for selecting a value of zero for e for values of X such that 1.0 ≤ X < 2.0 in square root determination.
6. The apparatus of claim 1 wherein the second selecting means for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination outputs the following: A) for a range of X such that 0.5 < X < 1.0 in a convergent division determination, an output for the new binary bits to the right of the binary point being one followed by the initially second, and all following binary bits to the right of the binary point; B) for a range of X such that 1.0 < X < 1.5 in a convergent division determination, an output for the new binary bits to the right of the binary point being the initially second, and all following binary bits to the right of the binary point;
Q for a range of X such that 0.5 < X < 1.0 in a square root determination, an output for the new binary bits to the right of the binary point being two ones followed by all bits initially to the right of the binary point; and D) for a range of X such that 1.0 < X < 2.0 in a square root determination, an output for the new binary bits to the right of the binary point being all bits initially to the right of the binary point.
7. The apparatus of claim 1 wherein the complementing means for determining a one's complement of the selected binary bits to the right of the binary point comprises inverting all bit values to the right of the binary point.
8. The apparatus of claim 1 further including means for iterating a determination of the convergence factor until a solution with a predetermined degree of accuracy is reached for the mathematical determination invoked.
9. The apparatus of claim 1, further including allocating one or more data manipulation and storage devices for iterating the determination of a convergence factor until a solution with a predetermined degree of accuracy is reached for the type of determination invoked.
10. The apparatus of claim 1, further including a computer program storage medium containing a fixed hardware embodiment of the first selecting means, the input value altering means, the exponent means, the first determining means, the locating means, the second selecting means, the complementing means, the combining means, the second determining means, and the third determining means of the apparatus such that the computer program storage medium itself can implement processing of the convergence factors.
1 1. The apparatus of claim 1 , further including a computer program storage medium containing a computer program application of the processing achieved by the apparatus such that the computer program storage medium itself can process the convergence factors.
12. The apparatus of claim 1, further including a computer program storage medium containing a combination of at least a part of a computer program application of the processing achieved by the apparatus together with at least a part of a fixed hardware embodiment of the first selecting means, the input value altering means, the exponent means, the first determining means, the locating means, the second selecting means, the complementing means, the combining means, the second determining means, and the third determining means of the apparatus such that the two parts together coordinate to process the convergence factors.
13. A method for allocating data storage means and data manipulation means of a numeric processor so as to expedite and improve floating point computation of convergence factors 2.0 -X and 1.5 - 0.5X for a mathematical determination, being convergent division or square root determination, for an input value X other than ± , ± 0, or NaN wherein X is limited to a certain range with a lower limit greater than or equal to 0.5 and an upper limit β determined by the mathematical determination invoked and such that X = 2e * f, said method comprising the steps of:
A) allocating one or more data input devices for storing an input value X;
B) allocating one or more data man! ilation devices for determining that input value is not ± ∞, ± 0, or NaN; Q allocating one or more data manipulation and storage devices for converting an input value X to a value X such that
0.5 < X < β, wherein β is a constant value related to the mathematical determination; D) allocating one or more data manipulation and storage devices for selecting a value for an exponent e;
E) allocating one or more data manipulation and storage devices for determining a value for f wherein f = X/2e such that 1< f < 2 and f is represented by a series of binary bits consisting of a most significant bit and remaining binary bits;
F) allocating one or more data manipulation and storage devices for setting the most significant bit of f to 1 with the remaining binary bits of f to the right of a binary decimal point;
G) allocating one or more data manipulation and storage devices for selecting binary bits to the right of the binary decimal point in accordance with the value of X and the mathematical determination invoked; H) allocating one or more data manipulation and storage devices for one's complementing the selected binary bits to the right of the binary decimal point;
I) allocating one or more data manipulation and storage devices for combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining a new value for f, designated f ;
J) allocating one or more data manipulation and storage devices for determining a new X, designated X', wherein X' = 2e * f ; and
K) allocating one or more data manipulation and storage devices for generating a convergence factor Y such that Y = 2.0 - X' for convergent division and Y = 1.5 - 0.5X' for square root determination.
14. The method of claim 13, further including allocating one or more data manipulation and storage devices for iterating the determination of a convergence factor until a solution with a predetermined degree of accuracy is reached for the mathematical determination invoked.
15. The method of claim 13, further including a computer program storage medium containing a fixed hardware embodiment of a computer program of the method such that the computer program storage medium itself can execute the program.
16. The method of claim 13, further including a computer program storage medium containing a computer program application of the method such that the computer program storage medium itself can execute the program.
17. The method of claim 13, further including a computer program storage medium containing a combination of at least a part of a computer program application of the processing achieved by the apparatus together with at least a part of a fixed hardware embodiment of the first selecting means, the input value altering means, the exponent means, the first determining means, the locating means, the second selecting means, the complementing means, the combining means, the second determining means, and the third determining means of the apparatus such that the two parts together coordinate to process the convergence factors.
EP19910901464 1989-12-29 1990-12-03 Method and processor for high-speed convergence factor determination Withdrawn EP0461230A4 (en)

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Citations (1)

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US5157624A (en) * 1990-12-13 1992-10-20 Micron Technology, Inc. Machine method to perform newton iterations for reciprocal square roots

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US4878190A (en) * 1988-01-29 1989-10-31 Texas Instruments Incorporated Floating point/integer processor with divide and square root functions
US4949296A (en) * 1988-05-18 1990-08-14 Harris Corporation Method and apparatus for computing square roots of binary numbers

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US5157624A (en) * 1990-12-13 1992-10-20 Micron Technology, Inc. Machine method to perform newton iterations for reciprocal square roots

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PROCEEDINGS OF THE 9TH SYMPOSIUM ON COMPUTER ARITHMETIC, 6-8 SEPT. 1989, SANTA MONICA, CA, USA. 1989, IEEE, WASHINGTON D.C., USA pages 60 - 67 D. FOWLER ET AL. 'An Accurate, High Speed Implementation of Division by Reciprocal Approximation' *
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WEITEK APPLICATION NOTE 'WTL 1032/1033 Floating Point Division/Square Root/ IEEE Arithmetic' 1983 , WEITEK CORPORATION , SANTA CLARA, CA, USA *

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KR940008610B1 (en) 1994-09-24
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KR920701901A (en) 1992-08-12
WO1991010188A1 (en) 1991-07-11
CA2050353A1 (en) 1991-06-30

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