JPH0225924A - Floating point arithmetic processor - Google Patents

Abstract

PURPOSE:To increase arithmetic processing speed for extraction of the square root by supplying the output of a bit inverting circuit to a rounding circuit via a multiplexer only in a partial arithmetic process for extraction of the square root and performing a right shift by one bit after addition of 1 to the minimum digit. CONSTITUTION:A multiplexer 8 supplies the output of a bit inverting circuit 7 to a rounding circuit 6 only in a partial arithmetic process for extraction of the square root. The output of the circuit 7 receives 1 at its minimum digit and is shifted to the right by one bit in the circuit 6. Otherwise the output of a right shift circuit 5 is supplied directly to the circuit 6 via the multiplexer 8. Thus it is possible to perform the binary calculation of 1/2*(3-AXi) where 0<AXi<=1 is satisfied in a single step via an arithmetic processor capable of the multiplication of floating points just with addition of the circuit 7 and the multiplexer 8. Then the repetitive calculation is carried out at high speed for the extraction of the square root.

Description

[Detailed Description of the Invention] [Summary] Regarding a floating-point arithmetic processing device, particularly an arithmetic circuit that performs square root calculation, it is possible to speed up the repetitive calculation of square root calculation by simple circuit improvement, thereby realizing high-speed square root calculation processing. Using an integer multiplier, right shift circuit, and rounding circuit,
A floating point arithmetic processing device capable of obtaining a multiplied value of the mantissa parts of two binary numbers to be multiplied, wherein a bit inversion circuit and a multiplexer are provided between the right shift circuit and the rounding circuit, and a bit inversion circuit and a multiplexer are provided between the right shift circuit and the rounding circuit, Only during operation, the output of the bit inverting circuit is supplied to the rounding circuit via the multiplexer, "1" is added to the minimum digit, and the output is shifted to the right by 1 bit, and at times other than the above operations, the output of the bit inverting circuit is supplied to the rounding circuit via the multiplexer. The output of the rounding circuit is configured to be supplied to the rounding circuit via the multiplexer.

[Industrial Application Field] The present invention relates to a floating-point arithmetic processing device, and more particularly to an arithmetic circuit that performs square rooting of numerical values in floating-point notation. Floating-point arithmetic has a wider dynamic range and higher accuracy than integer (fixed-point) arithmetic, so there is a recent trend toward a system that satisfies various advanced arithmetic requirements. Among these, high-speed processing related to square root is becoming important.

[Conventional technology]

In general, as a square root method, a method using a convergence method (for example, the Newton-Labrun method) is known, and is not limited to floating point. To find the square root of the number B, first 1/
, /' Find T, multiply it by B, and find 1. When calculating 1/, /'T by convergence calculation using the Newton-Raphson method, the number of iterations required for convergence decreases as the initial value of the reciprocal is closer to the true value.

Many floating-point arithmetic processors currently released use the Newton-Labrun method to perform square root calculation. In the Newton-Raphson method, if the initial value of the reciprocal is given within a certain precision, the convergence value can be obtained by performing convergence calculations about 3 to 4 times. Therefore, square root processing using the Newton-Raphson method can be processed at high speed.

We will explain the square root using the Newton-Labrun method. To perform square root, first find the inverse function. for example,
C-77 can be expressed in the form of a reciprocal number: c = B (1/, /'T). Using the Newton-Raphson method to find the iterative expression of the inverse function, the following formula%Formula%Formula% Here, when i = 0, Xo is the approximation of the reciprocal of the first f, and X is the first approximation. It is. The symbol * is the symbol for multiplication. The operation ends when the initial value X0 satisfies the condition of inequality O used as a pointer to R
OM outputs the contents of the address indicated by the value of B as an initial value.

The number of output bits is usually approximately the same as the number of input bits. Generally, in the case of floating-point square root, the reciprocals of the exponent and mantissa parts are obtained from separate lookup tables.

FIG. 4 shows a conventional floating point arithmetic processing device (multiplier). The floating point numbers input from two inputs (input 1 and input 2) are (-1)s'''2 Ex-bias (1
, F a ) and (-1> “2 E to b!” (1,
F b ). This floating point multiplier handles only normalized numbers.

The respective mantissa parts (1, F a ) and (1, F b )
is (1, Fa) by an integer (fixed point) multiplier
x(1,Fb) is executed. This result is l,xxx
x..., or lx, xxxx.... l,
In the case of x x xX..., it has already been normalized. l
In the case of x, xxxx, etc., normalization processing is required.

That is, the right shift circuit 5 executes a 1-bit right shift. At this time, it is necessary to add +l to the exponent part.

Next, rounding is performed to match the normalized numbers to the output data format. Rounding circuit 12 in rounding circuit 6
, truncates the digits below the LSB (least digit) in the output data format, and converts rLJ to the LSB according to the rounding mode.
Decide whether to add And “1” in LSB
The operation of adding is performed by an incrementer 11. At this time, if all the data is rlJ, an overflow will occur. In this case, the right shift circuit 13
The final output is a normalized number.

The calculation of the exponent part will be explained. The calculation of the exponent part is performed on the left side of the vertical chain line in the figure. 1st stage adder 2
1, Ea+Eb is executed, and the second stage adder 22 adds -bias to the result. Therefore, the calculation of Ea +Eb-bias is performed by these two adders. The third-stage integrator 23 performs +1 addition when it is necessary to correct overflow by normalization processing. Further, in the fourth stage integrator 24, +1 addition is performed in advance for overflow correction by rounding processing, and one of them is selected by the multiplexer (MIIX) 25 in accordance with the overflow signal V. Calculation of sign is 3a and sb
It is performed by exclusive OR of .

In a conventional floating-point multiplier as shown in Figure 4, 2
-BX, cannot be calculated, and in order to calculate 2-BX, when using a conventional floating point multiplier, an additional adder is required.

[Problem to be solved by the invention]

As mentioned above, Xi, l = 1/2*Xi (3-BX, the iterative calculation of ) Multiplication: Xi * (3-(A*Xi)) Multiplication: 1
/2*(xi*(3-(A*X,))) five arithmetic operations are required, and the overall processing time is long, making it difficult to meet demands for speeding up.

An object of the present invention is to improve the above-mentioned iterative calculations by simple improvements in a floating-point arithmetic processing device, and to realize speeding up of square root arithmetic processing.

[Means to solve the problem]

In the present invention, as illustrated in FIG. 1, the mantissa parts of two binary numbers to be multiplied are multiplied by an integer (fixed point) multiplier 20, and the multiplied value is set to correspond to the value of the most significant bit. The signal is then supplied to a rounding circuit 6 via a right shift circuit 5 which shifts the number to the right by 1 bit, and is then supplied to a floating point arithmetic processing device which obtains the mantissa part of the binary number multiplied by the output of the rounding circuit 6, and is further supplied with a bit inverting circuit 7. and a multiplexer 8.

The bit inversion circuit 7 and the multiplexer 8 are provided between the right shift circuit 5 and the rounding circuit 6, and the bit inversion circuit 7 sets a binary number "lO" in the digits above the decimal point, and sets the binary number "lO" in the digits below the decimal point. Invert. The multiplexer 8 supplies the output of the bit inversion circuit 7 to the rounding circuit 6 only during a part of the square root operation. Then, the bit inversion circuit 7
In the rounding circuit, "1" is added to the minimum digit of the output, and the output is shifted to the right by one bit. At times other than the above operations, the output of the right shift circuit 5 is directly supplied to the rounding circuit 6 via the multiplexer 8.

In another embodiment of the present invention, as illustrated using FIGS. 1 and 2, the mantissa parts of two binary numbers to be multiplied are multiplied by an integer (fixed point) multiplier 20, and the multiplication A floating point number that is supplied to a rounding circuit 36 through a right shift circuit 5 that shifts the value by one bit to the right in accordance with the value of the most significant bit, and obtains the mantissa part of the binary number multiplied by the output of the rounding circuit 36. The arithmetic processing device is further provided with a bit inversion circuit 37 and a multiplexer 8. The bit inversion circuit 37
and the multiplexer 8 are connected to the right shift circuit 5 and the rounding circuit 3.
The bit inversion circuit 37 inverts the input numerical value. The multiplexer 8 supplies the output of the bit inversion circuit 37 to the rounding circuit 36 only during a part of the square root operation. Then, "1" is added to the minimum digit of the output of the bit inverting circuit 37 in the rounding circuit, and
It is shifted to the right by 1 bit and "1" is set in the most significant digit.

At times other than the above operations, the output of the right shift circuit 5 is directly supplied to the rounding circuit 36 via the multiplexer 8.

[For production]

By using the above-mentioned device, in an arithmetic processing unit that performs floating-point multiplication, by simply adding a bit inversion circuit 7 or 37 and a multiplexer 8, 1/2 * (iAX,)
(However, 0<AXi≦1) can be executed in one step using an arithmetic processing unit capable of floating-point multiplication, and the iterative calculation required for square root calculation can be speeded up.

〔Example〕

Prior to describing embodiments, the present invention will first be described in detail.

The calculation of the mantissa part of the square root of a normalized number (1≦B<2) using the floating point data format of the IEEE standard will be described. If C is the square root value, then C-5-B(1/
,/”T).

1, the approximate value X 1 + 1 of #H is Xi, +=1/
It can be expressed as 2*Xi (3-BXi”).However,
O<Xo<f7th block, B>0゜Here, the initial value
If we set the range of 0 < Xo≦fT7N, then Q<
AXo ≦1 (However, A=BXO) Therefore, 2≦(3
AXo ) < 3 Therefore, 1≦1/2* (3-AXO)<3/2,
1/2* (3-AXi) is also a normalized number. Therefore,
Generally, 1/2*(3-AX,) is a normalized number. Next, consider the calculation of 1/2k (3-AX,). 0<AX
, ≦1, so let AX be the bit inversion below the decimal point of AX, then (3-AX,)d = (10,AX, +L
It can be converted to SB (1))b.

Here, LSB (1): means adding 1 to the LSB (least digit), ()d: decimal, ()b: binary.

Further obtained (10. AXi +LSB (
1))b.

By shifting one bit to the right, 1/2*(3-AXi
), where we can perform the calculation of (0<AXi≦1). In the above manner, the above-mentioned five-time iterative calculation is simplified as follows.

Multiplication: B*XH1 Calculation according to the invention with this as =A: 1/2'l' (3-A*X,)
Multiplication: X□ * (1/2* (3-A*X,)) In this way, it can be performed with only three arithmetic operations.

A circuit diagram of a floating point arithmetic processing device as an embodiment of the present invention is shown in FIG. This device is divided into left and right parts by the dashed line in the center of FIG. (Incrementer) 23
and 24, and a multi-buxa 25. This exponent calculation part is the same as that of the conventional arithmetic processing device, so a description thereof will be omitted. Further, the sign determination circuit is also the same as that of the conventional type.

The mantissa calculation circuit is shown on the right side of the center dashed line in FIG. The mantissa parts of the two inputs to be multiplied (input 1 and input 2) are output by the integer (fixed point) multiplier as data as shown by the dashed block. The most significant digit V is supplied to the integrator 23 in the exponent part calculation and causes the right shift circuit 5 to shift by 1 bit. Adder 4
The output of is supplied to the right shift circuit 5. Right shift circuit 5
The output of is supplied to a bit inversion circuit 7 and a multiplexer 8, which are newly provided according to the present invention.

Regarding the input data, the bit inversion circuit 7 inverts the bits in the lower digits from the decimal point, and converts the upper bits into "10".
The data ``rlO,xxx...'' is output.

The calculation of 1/2*(3-A*X,) will be explained below. , the output AX from the adder 4 is 0<AX,≦1, so the overflow bit V is 0. The data after passing through the right shift circuit 5 is 1.0000. ,,O or Q
,xxxx,,,. These are converted to 1.0000 by the bit inversion circuit 7, , 10.1111. ,．． 0°xxx becomes 10,xxxx, . Here, X is the inverted value of X. The multiplexer 8 selects the output from the bit inversion circuit 7 according to the control signal (square root) given at the time of some operations in the square root operation, that is, the operation of 1/21 (3-A*X,), and outputs the square root signal. When there is no output from the right shift circuit 5, the output from the right shift circuit 5 is supplied to an incrementer 11 which is one element of the rounding circuit 6. When the square root control signal is given, the integrator 11 further adds "
1" is added. The output of the integrator 11 is passed through another right shift circuit 13 to output a mantissa output. The rounding circuit 6 includes an integrator 111, a right shift circuit 13, and a round circuit 12, and in the rounding mode, the multiplexer 8
The receiver supplies the output to the integrator 11, and rounds the calculated output.

When the most significant digit (■) in the integrator 11 is "11", a signal is sent to the exponent multiplexer 25, the output from the integrator 23 is selected, and the right shift circuit 13 performs a 1-bit right shift. During square root control, the overflow bit (i.e. 2'
Since the digit) is "1", it is shifted to the right by 1 bit.

Therefore, up to the output of the integrator 11 mentioned above, the calculation of 3-A*X is performed, which is multiplied by 1/2 by the right shift circuit 13, and finally the calculation of 1/2 * (3-A X i ) is performed. This is done in one step (here 0<AXi≦1).

A modification of the above embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 shows a partial circuit diagram of a modified example. That is, a circuit diagram of the right shift circuit 5 and subsequent parts in the mantissa calculation circuit is shown. The other circuits are similar to the circuit shown in FIG.

In this circuit, a bit inversion circuit 37 is used in place of the bit inversion circuit 7. In the bit inversion circuit 7, the bits in the lower digits from the decimal point are inverted and the upper bits are set to "10", but the bit inversion circuit 37 does not set the upper bits to "IO". Further, in place of the right shift circuit 13, a right shift circuit 33 is used in the modified example.

Details of the right shift circuit 33 are shown in FIG. In this circuit, if the control signal S is "1", the left input of each multiplexer 41 is selected, and if rOJ, the right input is selected. When the control signal S is “1”, the most significant digit (MSB
) is set to "1". The control signal S is 1/2* (3-A*X,) [where O<
AX, ≦1] is controlled so that rlJ is satisfied. The operation of the control signal S and the right shift circuit 33 makes it possible to omit the setting of "10" in the bit inversion circuit 7.

〔Effect of the invention〕

According to the present invention, by simply adding a circuit to a floating-point arithmetic processing device, it is possible to speed up the iterative calculations required for square root calculation, thereby realizing speeding up of square root calculation processing.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a floating point arithmetic processing device as an embodiment of the present invention, Fig. 2 is a partial circuit diagram showing a modification of the embodiment of Fig. 1, and Fig. 3 is a circuit diagram of a rounding circuit of Fig. 2. FIG. 4 is a circuit diagram showing a right shift circuit, and FIG. 4 is a circuit diagram of a conventional floating point arithmetic processing device. In the figure, 5... right shift circuit, 7... bit inversion circuit, 11... integrator, 13... right shift circuit, 21, 22... adder, 23, 24... integration 33... right shift circuit, 37... bit inversion circuit. ...Rounding circuit, ...Multiplexer, 2...Round circuit, 0...Integer multiplier, 25...Multiplexer, 36...Rounding circuit, 41...Multiplexer,

Claims (1)

[Claims] The mantissa parts of two binary numbers to be multiplied are multiplied by an integer multiplier (20) which is a fixed-point multiplier, and the multiplied value is divided into one bit corresponding to the value of the most significant bit. A floating point arithmetic processing device that supplies a rounding circuit (6) via a right shift circuit (5) for right shifting, and obtains the mantissa part of a binary number multiplied by the output of the rounding circuit (6), Between the right shift circuit (5) and the rounding circuit (6), a bit inverting circuit (7) and a multiplexer (8) set a binary number "10" in the digits above the decimal point and invert the digits below the decimal point. is established, and only during some calculations in square root calculation,
The output of the bit inversion circuit (7) is connected to the multiplexer (8).
) is supplied to the rounding circuit (6), and the minimum digit is "1".
'' is added and shifted to the right by 1 bit, and at times other than the above operations, the output of the right shift circuit (5) is supplied to the rounding circuit (6) via the multiplexer (8). Decimal point arithmetic processing unit. 2. A right shift circuit that multiplies the mantissa parts of two binary numbers to be multiplied by an integer multiplier (20) that is a fixed-point multiplier, and shifts the multiplied value to the right by 1 bit corresponding to the value of the most significant bit. (5), the floating point arithmetic processing device supplies the rounding circuit (36) and obtains the mantissa part of the binary number multiplied by the output of the rounding circuit (36), the floating point arithmetic processing device comprising the right shift circuit (5). ) and the rounding circuit (36), a bit inverting circuit (37) and a multiplexer (8) are provided to invert the applied numerical value, and the bit inverting circuit (37) is used only during part of the square root operation. The output is supplied to the rounding circuit (36) via the multiplexer (8), "1" is added to the least significant digit, shifted one bit to the right, and "1" is set to the most significant digit. is a floating point arithmetic processing device in which the output of the right shift circuit (5) is supplied to the rounding circuit (36) via the multiplexer (8).