JPS58137045A - Parallel multiplier - Google Patents

Abstract

PURPOSE:To reduce the scale of a circuit remarkably without delaying the operating time, by splitting a multiplier into N, multiplying each section of the split multiplier to a multiplicand sequentially, summing each obtained product and obtaining the product between the multiplier and multiplicand. CONSTITUTION:A multiplier 5 multiplies a multiplicand X, e.g., 12-bit, outputted from a multiplicand register 2 with a system clock (a), with a multiplier lower- order Yl and a multiplier upper-order YU, each 8-bit, alternatey outputted from a multiplier lower/upper order switching circuit 4. An output (h) of the multiplier 5 is shifted for bits. Through the keperation like this, an upper partial product X.Yl and a lower partial product X.Yu are outputted from a circuit 6 as a 25- bit length. In the two clocks of the clock (a), the upper partial product X.Yu is inputted to an input terminal A of an adder 9 and a lower partial product X.Yl is inputted to an input terminal B, the product between the multiplicand X and the multilier Y is outputted and picked up from an accumulator output circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel multiplier that can reduce the circuit scale.

Conventionally, digital multipliers have been broadly classified into the following three types.

(b) A method in which the multiplicand X is added the same number of times as the multiplier Y.

(b) A method in which the partial products of the multiplicand X and each digit of the multiplier Y are sequentially shifted and added using a register (hereinafter referred to as the sequential circuit method).

(c) A method that realizes multiplication using only combinational circuits (hereinafter referred to as combinational circuit method).

Among these methods, method (a) has a simple logic, but has the drawback of requiring a very long calculation time.

Further, since the sequential circuit method (b) also requires a shift operation, it has the disadvantage that the calculation time is longer than the combinational circuit method (c).

Further, FIG. 1 shows a multiplication algorithm in a combinational circuit system when unsigned data is targeted. In this case, the partial product z of the multiplicand X and each digit of the multiplier Y
i is determined by an array of AND gates, and these partial products zi are added by a parallel adder. Therefore, 1
Since each stage requires M AND gates of N stages and parallel adders of (N-1) stages, there is a drawback that the circuit scale becomes large.

Further, FIG. 2 shows a multiplication algorithm in a combinational circuit system using a two's complement format in a signed case. In the figure, is and ys represent sign bits, and "Δ" represents a logical sum.

As is clear from the figure, in this case, a correction circuit is further required for the sign, which has the disadvantage of further increasing the circuit scale.

Additionally, Booth's algorithm is a method for simplifying signed multiplication. This algorithm simplifies the generation of partial products and allows two's complement multiplication to be performed without correction. FIG. 3 shows the second-order Booth algorithm, in which 8 represents a sign bit.

However, even in combinational circuit type multipliers using Booth's algorithm, as the number of digits in multiplication increases, the number of stages of partial products increases, resulting in an increase in circuit scale.

The present invention has been made in order to eliminate the drawbacks of the conventional art, and it is an object of the present invention to provide a parallel multiplier that can reduce the circuit scale without slowing down the calculation speed.

The parallel multiplier according to the present invention divides the multiplier into N (where N is a natural number of 2 or more), and sequentially multiplies the multiplicand by each divided part of the N-divided multiplier, and adds the resulting products. , which calculates the product of the multiplicand and the multiplier.

The present invention will be described in detail below based on embodiments shown in the drawings.

FIG. 4 shows a multiplication algorithm in one embodiment of the invention. In this figure, X is the multiplicand (12 bits of 2
Y indicates the bit array of the multiplier (16-bit binary number), with the upper digits on the left and the lower digits on the right. Further, 1 indicates the position of the decimal point.

In this embodiment, the multiplier Y is divided into two into an upper Yu and a lower Yl, and the multiplicand X is multiplied by each in a different clock cycle. Here, the lower multiplier Yl is y6 to yOQ of the multiplier Y,
, , consists of 8 bits of 7 bits and the most significant O, while the upper multiplier Yu consists of 8 bits of the multiplier Y from ``14'' to y7.

X, Y7 is the product of the multiplicand X and the lower multiplier Yl (hereinafter,
z18 corresponds to the sign bit, and z25 to z19 are filled with the same data as z18.

X a Yu is the product of the multiplicand X and the upper multiplier Yu (hereinafter,
z24 and 225 are sign bits. Further, Zs to z0 are filled with 0.

Then, the lower partial products X, Yl and the upper partial product X−Yu
By adding, the multiplicand and the entire multiplier Y,
Get the product 2.

FIG. 6 is a circuit diagram of the parallel multiplier according to the embodiment, and FIG. 6 is a signal waveform diagram in the multiplier.

In FIG. 6, 2 is a multiplicand register that holds the multiplicand X, 3 is a multiplier register that holds the multiplier Y, and 4 is a multiplier upper/lower switching circuit that selects the upper and lower parts of the multiplier register 3. Reference numeral 6 denotes a parallel multiplier that multiplies the output I of the multiplicand register 2 by the output q of the multiplier upper switching circuit 4. This multiplier 6 is constructed by the conventional Booth algorithm or the like. 26 is a multiplier output switching circuit for bit-shifting the output of the multiplier 6, 7 is an accumulator, and 8 is a circuit for inputting the output m of the accumulator 7 and an arbitrary number K, and selecting one of these two inputs. This is an accumulator input control circuit that outputs.

9 is an adder that adds the output j of the multiplier output switching circuit 6 and the output of the accumulator input control circuit 8, and outputs it to the accumulator 7; 10, from the output m of the accumulator 7, adds the multiplicand X and the multiplier Y; This is an accumulator output circuit that selects and stores the product of .

Next, the operation of this multiplier will be explained with reference to the signal waveform diagram in FIG.

The multiplicand X is held in the multiplicand register 2 at the rising edge of the multiplicand latch clock C, which has a period twice that of the system clock a. Also, the multiplier Y is held in the multiplier register 3 at the rising edge of the multiplier latch clock d, which has a cycle and period twice that of the system clock a.
Note that Xl, X2. X3. Yl, Y2. Y3
(indicates different multiplicands and multipliers that are successively multiplied).

When the upper/lower switching signal e is at a low level (hereinafter abbreviated as L''), the multiplier upper/lower switching circuit 4 switches the lower Yl of the multiplier Y output from the multiplier register 3 to the upper/lower switching signal. When e is at a high level (hereinafter abbreviated as "H"), the higher order Yu of the multipliers Y output from the multiplier register 3 is selected and output to the multiplier 6.

h indicates the output of this upper/lower switching circuit 4.

The multiplier 6 receives the 12-bit multiplicand x output from the multiplicand register 2 and the lower multiplier Yl alternately output from the multiplier upper/lower switching circuit 4 in response to the system clock a.
, the upper multiplier Yu, each of which is multiplied by 8 bits.

Then, the lower partial products obtained from this are X, YlO
In the first cycle of system clock a, multiplier 6
The upper partial product X-Yu appears at the output of the multiplier 6 in the second cycle of the system clock a.

Here, since the multiplier 5 itself cannot distinguish between the multiplication of the multiplicand X and the lower multiplier Yl, or the multiplication of the multiplicand X and the upper multiplier Yu, the multiplier output switching circuit 6 uses the upper and lower switching signal e to Let's perform a bit shift on the output of the multiplier 6. That is, the output of the multiplier 5 is obtained with a length of 19 pits, but in the case of the lower partial product X·'Yl, the sign bit is extended upward by 7 bits as shown in FIG. Also,
In the case of the upper partial product X-Yu, the output of multiplier 6 is 19
Align the bits to the left.

Through the above operations, the lower partial products X, Yl and the upper partial products XeYu are outputted from the multiplier output switching circuit 6 as each having a length of 26 bits. j indicates the output of this multiplier output switching circuit 6.

On the other hand, the output of the accumulator input control circuit 8 is set to "0" by the accumulator input clear signal r in the first cycle of the system clock a. Therefore, in the first cycle of the system clock a, the adder 9 outputs the lower partial product -X
7 Yl! is output as is (t is the adder 9
). And these lower partial products X, Yt are
At the rising edge of the second cycle of system clock a,
It is stored in the accumulator 7.

Next, in the second cycle of the system clock a, the lower partial product X·Yt is input from the accumulator 7 to the B input terminal of the adder 9 through the accumulator input control circuit 8. At this time, the input terminal of the adder 9 receives the upper partial product X-Yu from the multiplier output switching circuit 6.
is input.

As a result, in the second cycle of system clock a,
The adder 9 outputs the product of the multiplicand X and the entire multiplier Y. This product is then stored in the accumulator 7 at the rising edge of the next cycle of the system clock a.

Therefore, from the accumulator 7, the lower partial products X, Y
t and the product of the multiplicand X and the entire multiplier Y are output alternately every clock of the system clock a. By storing the output m of F, only the multiplicand X, the entire multiplier Y, and the 9 products are stored. Therefore, in this multiplier, the system
Accumulator output circuit 1 with two clocks of clock a
From the output q of 0, we can obtain the product of the multiplicand X and the entire multiplier Y.

In addition, in this embodiment, not only simple multiplication but also the calculation of (multiplicand x x multiplier Y 10 arbitrary number K) can be performed.

That is, when the accumulator input control signal t is "H", the accumulator input control circuit 8 does not select the output of the accumulator 7, but selects an arbitrary number of inputs. In this way, if an arbitrary number K is input from the accumulator input control circuit 8 to the B input terminal of the adder 7 instead of 0 in the first cycle of the system clock a, (multiplicand x x multiplier Y An arbitrary number K) of operations can be performed.

Further, the output of the multiplier output switching circuit 6 is cleared by turning on the multiplier output clear signal U. Then, when the multiplier output clear signal U is turned on, the contents of the achievable data are saved.

When a conventional multiplier using the Booth algorithm shown in FIG. 3 multiplies a 12-bit multiplicand and a 16-bit multiplier, the number of stages of the partial product generating circuit is seven, but in this embodiment, , the multiplier Y is divided into two into 7 bits and 8 bits, so the circuit for generating partial products only needs to have four stages.

Furthermore, since the adder 9 for adding the upper partial product and the lower partial product can be used as the adder provided in the accumulator 7, the additional circuits compared to the conventional ones are the multiplier upper/lower switching circuit 4, the multiplier output With only the switching circuit 6, accumulator input control circuit 8, etc., the scale is almost negligible.

Therefore, the overall circuit size can be about half that of a conventional multiplier.

Further, the signal propagation delay time is also reduced in proportion to the number of circuits, and can be reduced to approximately half of the conventional one.

In this embodiment, twice as many clock cycles as in the conventional method are required to perform one multiplication, but as mentioned above, the signal propagation delay time is approximately half that of the conventional method.
Since it is possible to increase the clock frequency to twice that of the conventional method, the actual calculation time can be kept the same as that of the conventional method.

In the above embodiment, the multiplier is divided into two and each multiplicand is sequentially multiplied, but in general, the multiplier is divided into N,
Multiply each multiplicand in turn and obtain 6
It goes without saying that a configuration in which products are cumulatively added may also be used.

As described above, according to the present invention, the circuit scale can be significantly reduced compared to conventional multipliers without slowing down the calculation time, and the excellent effect of being suitable for LSI implementation can be obtained.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the algorithm of a conventional combinational circuit type multiplier without a code, Figure 2 is a diagram showing the algorithm of a combinational circuit type multiplier with a conventional code, and Figure 3 is a diagram showing the algorithm of a combinational circuit type multiplier in the case of a conventional unsigned case. FIG. 4 is a diagram showing a multiplication algorithm in a parallel multiplier according to an embodiment of the present invention; FIG. 6 is a block diagram showing a parallel multiplier according to the embodiment; FIG. 6 is a signal waveform diagram in the parallel multiplier according to the embodiment. 4... Multiplier upper/lower switching circuit, 6...
Multiplier, 6... Multiplier output switching circuit, 7...
1...Accumulator, 9...Adder. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
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Claims (1)

[Claims] means for dividing a multiplication into N (N is a natural number of 2 or more); a parallel multiplier for sequentially multiplying a multiplicand by each divided part of the N-divided multiplier; and the multiplicand and the multiplier sequentially output from the multiplier. A parallel multiplier comprising a shift means for shifting the product with each divided portion by a number of bits corresponding to the digit position of each divided portion, and an accumulator for cumulatively adding the products shifted by the shifting means. vessel.