JPH01163827A - Adder-subtracter - Google Patents

Abstract

PURPOSE:To make a circuit scale smaller by making an adder part into a half adder, and making the input/output of the half adder obtain both positive and negative logics. CONSTITUTION:An adder-subtracter consists of half adders 2. A constant K is directly inserted to one input of the half adders 2, and a number X to be operated is inserted to the other input so as to obtain the both positive and negative logics, and the output of the half adders 2 is made to obtain the both positive and negative logics. Consequently, by only a constant addition by means of the adder circuit 2 of the conventional half adder, a subtraction can be also carried out. Thus, the circuit scale can be made smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an adder/subtractor 1, such as a logic LSI such as a microcomputer, and particularly to a logic circuit configuration suitable for addition/subtraction of constants.

[Conventional technology]

The conventional adder/subtractor has a configuration in which one of the inputs of the full adder 3 can have both positive and negative logic, as shown in FIG.

In Figure 2, addition to the variable
3=O is added to obtain the output y.

On the other hand, in subtraction, the constant is input with negative logic and the variable X is input with positive logic into the full adder 3, and carry C0103=1 is added thereto to output y.

For example, 5 in decimal representation (hereinafter written as 5 (10,))
, X, which is 00000101 (hereinafter referred to as 00000101 (2)) in 8-bit signed binary representation, and 3
(10)=00000011 (2) Consider the calculation of K. The operation on x+ is 5 (10) + 3 (10
) = 8, which also applies to binary operations as 00
000101(2) +00000011(2) =0
0001000(2)=8(10), and FIG. 3 shows an example of the configuration of a 6-full adder adder circuit in which addition of binary numbers can be simply performed using a full adder adder circuit.

The 1-bit m-order operation is composed of a full adder circuit 100 and a carry circuit 106. The adder circuit shown in Fig. 3 is a 2-bit adder circuit, and input X (lower bit xo: 10
1. Upper bit xz: 108) and K (lower bit Ko:
102. Add 109) to the upper bits and output y(
The lower bit yo: 107° and the upper bit yx: 111) are output.

In the full adder circuit, first, the two inputs x are added, and the addition results 113, 114 and carry 103,
110 and outputs the output y. A carry circuit 106 outputs a carry to the upper bit. Carry output to the upper bit is carried out from the input of the bit position to perform the operation, for example, when ao: 101 and bo2 102 are both 1, and when the addition result of ao and bo is 1 and the carry is from the lower bit. This is performed when human power co:103 is 1. The former is carried (CarryGe)
nerate), and carry propagation (CarryP
ropagate). The carry generation result 104 and the carry propagation result 105 are logically summed and outputted to the upper bit as a carry signal cl:110.

The operation on x- is K, which is the inversion of 0.1 of each bit of K.
x + K + 1 can be calculated using .

For example, x = 5 (to) =00000101(2
), K = 3 (10) =00000011(
Consider case 2). Since K=11111100 (2), x + K = 00000001 (2)
and adding 1 to the result gives 00000010(2
) = 2 (10).

The operation of +1 is performed using the adder circuit shown in Fig. 3.
If it 1 u is input to 03, +1 can be calculated for x+ at the same time.

Regarding the configuration of the addition circuit, for example, see the electronic science series "Easy Electronic Calculation" published by Jurishu Publishing Co., Ltd., and about the method of subtraction using an addition circuit, for example, in R published by CQ Publishing.
16-bit Microcomputer and Programming Fundamentals," etc.

Carry signal generation logic 10 in the adder circuit shown in FIG.
6 is a ripple carry type circuit which takes carry logic for each bit and propagates it to the upper bits. Therefore, when the operation bit length becomes longer, the delay time becomes longer due to the serial structure of the carry logic.
There is a Look Ahead knee 9-LA) technique. This is done by using the carry generation result 104 for each bit and the carry propagation condition 113 (the result of two-person addition that does not include a carry signal) to calculate the carry human force signal C for each bit.
x (110), C2 (112), etc. are directly generated. The result 104 of carry generation of the least significant bit is Go, and the corresponding signals on the upper bit side are hereinafter referred to as Gt+GZv G3, respectively. on the other hand.

The value of the carry propagation condition 113 is also Po
, PI, P21 pH. The carry signal of each bit is Go (103) as shown in FIG.

Let Cs (110), Cz (112), and Ca. At this time, the generation logic of the 01 to C8 signals is as shown in the following equation.

C1=Go+co-P.

C1=Go+co・Pt=Gl+Go-Pl+co-Po-PICa=G
z + Cx・P2 =02 ten 01・Pz ten Go-Pl・Pl+co-Po-
Pl-P2 As is clear from the above equation, the carry human input signal is determined only by the carry generation result, carry propagation conditions, and Go, and therefore is not configured in series on a bit-by-bit basis. Therefore, carry logic is accelerated regardless of the operation bit length. An embodiment is shown in FIG. 4, and this configuration is discussed in detail in ``High-speed Computing Methods for Computers'' published by Kindai Kagakusha.

In order to perform general addition/subtraction operations, an adder circuit with the full adder configuration described above is required, but addition of a certain number and a constant whose effective bit length is much shorter than that number can be achieved with a half adder adder circuit. .

For example, a counter adds a certain number to a constant 1, and this configuration is shown in FIG. Since all the upper bits of the constant 1 except the least significant bit are 0, it is only necessary to add a certain input number and carry at these bit positions. A configuration in which only two numbers (full adder adds three numbers) in this way is called a half adder configuration. Although this configuration has a smaller circuit scale than the full adder configuration, the only operation it can handle is addition.

The operation in 1-bit units is composed of a half adder circuit 120 and a carry circuit 121. Input X (lower bit x
o:122. The upper bit x s : 123) is added to the constant, and the output y (lower bit y.

:124. Upper bit yz:125) is output.

Since the upper bit of the constant is 0, there is no need to input it when adding, so the lowest bit K.

:126 only is input corresponding to the carry manpower 103 in FIG. Since the upper bit of K is 0, the carry circuit 121 does not require a carry generation logic, and sends only the carry propagation result 127 to the upper bit as a carry signal.

When performing addition/subtraction operations with a much shorter effective bit length, no consideration has been given to using a half-adder adder circuit. becomes complicated5
There was a problem that the circuit scale became large.

An object of the present invention is to provide a method that allows addition and subtraction of constants to be implemented using a small-scale half-adder adding circuit.

[Means for solving problems]

The above object is achieved by making the adder a half adder and making it possible for the input and output of this half adder to have both positive and negative rings.

[Effect]

23f! ! When each bit of a value X expressed as a number is inverted, the value becomes -x -1.When calculating ax K, first invert the bits of the value of X.

-x-1. Add K to this value. If the value of is about 2 bits, this adder can be constructed with a half adder. The result after addition is -x -10. If we invert the bits of this result, we get (-x-1+K) -1=
x-, and it is possible to perform calculations on a constant number of variables.

For X+, if K is added to X as it is without bit inversion, and the output is output without bit inversion, it is possible to perform an operation on a variable x ten constants. In this way, it becomes possible to perform subtraction using only constant addition using the conventional half adder adding circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The signal inversion circuit 1 is a selection circuit that inverts the bits of input data or outputs inverted data.

The half adder 2 is an adder for a constant of several bits and a variable X or a bit-inverted variable X. The bit width of the constant is a full adder, and the upper bit positions are a half adder. When subtracting a constant K from a variable X, the bits of the variable
)do. To add the variable X and a constant, it is sufficient to add the variable X to the constant without inverting the bits, and output the addition result as is (y).

Figure 6 shows the 8-bit variable x (LSB=xO2MSB:X
7) and the constants 0 (KO=O, 1=O), 1 (KO=4., 1=O), and 2 (KO=O, 1=1). The signal inversion circuit 1 shown in FIG. 1 is realized by a selection circuit 4 controlled by a control signal 8 as shown in FIG. When performing subtraction with a constant, control signal 8 is set to L.
level, and selects and outputs the variable x (xo''x7) and the bit-inverted data of the output 150 of the half adder 2.

In the case of addition, control signal 8 is set to H level, and bit normal rotation data is selected and output. In FIG. 6, the half adder 2 shown in FIG. 1 is a 2-bit half adder 5,
It consists of 6 and one-digit advance look (CL A) 7. The lower 2-bit half adder 5 is a 2-bit constant K.
O, Kl and 2-bit LSB side data (variable X or bit-inverted variable x/xo, xl or xo, x
Add i). Addition of the least significant bit is performed as an addition of XO or π and KO. 1 than the least significant bit
Addition of the upper bits is performed by adding the carry generated in the addition of the least significant bit, the OR signal 151 of 1 to a constant, and xl or xl. Constant KO=1=1.
In other words, since the constant 3 operation is not supported, both the carry and the constant 1 will not become 1.

A carry 152 generated by the addition of the lower two bits is input to a carry look ahead (CLA) 7 and a half adder 6 which performs bit addition of two and three upper bits from the least significant bit. Half adder 6 inputs 2-bit data x
1, x, +1, and carry addition result 153 is output, and at the same time, when data Xi and X j+1 are both 1, that is, a carry propagation condition signal 154 is output. The carry 152 generated by the addition of the lower two bits and this carry propagation signal 154 are carried forward (CI, A) 7,
By using carry lookahead logic, 2 on the upper bit side
Pill-'It's half adder 6 carry man power 15
Decide on 5,156. Since the upper 6 bits of the constant are O, it is only necessary to consider carry propagation to the upper bit side of the carry generated by addition of the lower 2 bits.

The adder/subtractor with a constant of 0.1.2 according to the present invention is used as an arithmetic unit for address calculation in a microprocessor or the like. When stacking data on a microprocessor with a 16-bit data bus, set the stack address to +1 when writing.
(byte data) or +2 (word data), the stack address calculation at the time of reading is a subtraction of -1°-2. Regarding the relationship between addition and subtraction in address calculation, the reverse case can also be considered.For a 6-instruction fetch address, an addition operation of +1 (byte fetch) or +2 (word fetch) is performed.

In this way, many of the processor's address operations are constant addition and subtraction operations.

〔Effect of the invention〕

According to the present invention, a high-speed constant adder/subtractor can be realized using a half adder and a carry lookahead circuit using only the P signal, so that the circuit scale can be reduced. Constant addition and subtraction can be widely used for processor address calculations.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the present invention, Fig. 2 is a block diagram of a conventional adder/subtractor, and Fig. 3 is a logic diagram of an adder using a full adder circuit.
FIG. 4 shows a carry lookahead circuit, FIG. 5 shows a logic diagram of an adder (counter) using a half adder circuit, and FIG. 6 shows an adder/subtractor of an A-fadder circuit according to the present invention. 1...Signal inversion circuit, 2...Half adder, 4...
・Signal inversion circuit, 5...2-bit half adder, 6.
...2-bit half adder, 7...Carry lookahead agent Patent attorney Katsuo Ogawa 4゛Atsushi 1 Figure NV1 1 I↓1t non-krag 2 Half 2- 3 Fluor 7-y3 Mouth C4C3Cz C+ ■ 5 Figure 121 Yase 9-times stomach trouble

Claims (1)

[Claims] 1. A constant adder/subtractor that adds or subtracts a number with a shorter bit length than the operand to and from the operand, the adder/subtractor being configured with a half adder, and a constant directly input to one input of the half adder. The adder/subtractor is characterized in that an operand is input to the other input so that it can have both positive and negative logic, and the output of the half adder can also take both positive and negative logic. 2. The adder/subtractor according to item 1, wherein the adder/subtractor is used for fetching instructions of a processor or calculating addresses of continuously transferred data.