JP2685466B2 - Address calculator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder / subtractor, for example, a logic LSI such as a microcomputer, and more particularly to a logic circuit configuration suitable for addition and subtraction of constants. [Prior Art] A conventional adder / subtractor has a full adder 3 as shown in FIG.
One of the inputs was configured to be able to take both positive and negative logic. In FIG. 2, the variable x and the constant K are added to the full adder 3 in positive logic, and the carrier C ₀ 103
= 0 is added to obtain the output y. On the other hand, in the subtraction, the constant K has a negative logic and the variable x has a positive logic and is input to the full adder 3, and the carrier C ₀ 103 = 1 is added thereto to obtain an output y. For example, 5 in decimal notation (hereinafter referred to as 5 (10)), 8
Bit-signed binary representation 00000101 (hereinafter 00000101 (2)
And the calculation of K such that 3 (10) = 00000011 (2). The calculation of x + K is 5 (10) +3
(10) = 8, which is 0000 even in binary operation
0101 (2) +00000011 (2) = 00001000 (2) = 8 (1
0), and the addition of binary numbers may be simply performed using a full adder addition circuit. FIG. 3 shows a configuration example of a full adder adder circuit. The operation of one bit unit is the full adder circuit 100 and the carrier circuit 106.
It is composed of The adder circuit shown in FIG. 3 is a 2-bit adder circuit, and the input x (lower bit x ₀ : 101, upper bit x ₁ :
108) and K (lower bit K ₀ : 102, upper bit K ₁ : 109) and output y (lower bit y ₀ : 107, upper bit y ₁ : 111)
Is output. The full adder circuit first adds two inputs x and K, adds the addition results 113 and 114 and the carriers 103 and 110, and outputs the output y. The carrier circuit 106 outputs the carrier to the upper bits. The carrier output to the upper bit is the input of the bit position where the calculation is performed, for example,
When both a ₀ : 101 and b ₀ : 102 are 1 and when the addition result of a ₀ and b ₀ is 1 and the carrier input from the lower bit is c ₀ : 103
Is 1 and. The former is Carry Generate and the latter is Carry Generate.
opagate). The result 104 of carrier generation and the result 105 of carrier propagation are ORed and output as a carrier signal c ₁ : 110 to the upper bits. To calculate x-K, x ++ 1 may be calculated by inverting 0 and 1 of each bit of K. For example, x = 5
(10) = 00000101 (2), K = 3 (10) = 00000011 (2)
Consider the case = 11111100 (2), so x +
K = 00000001 (2), and if you add 1 to the result, 00
000010 (2) = 2 (10). The operation of +1 is x ++ if "1" is input to c ₀ : 103 of the adder circuit shown in FIG.
1 can be calculated at the same time. For the configuration of the adder circuit, refer to, for example, "Easy Electronic Calculations" in the electronic science series published by Kobo Co., Ltd. Basics "and so on. Carrier signal generation logic 10 in the adder circuit shown in FIG.
Reference numeral 6 is a ripple carry circuit that takes carrier logic for each 1-bit unit and propagates it to the higher-order bits. Therefore, when the operation bit length becomes long, the delay time becomes long because the carrier logic is configured in series. Carry foresight (Carry L)
ook Ahead (CLA) technology. This is performed by using the carrier generation result 104 for each bit and the carrier propagation condition 113 (the addition result of two inputs not including the carrier signal), and the carrier input signals C ₁ (110) and C ₂ (for each bit). 112) etc. are directly generated. The result 104 of the carrier occurrence of the lowest bit is G ₀ , and the corresponding signals on the higher bit side are G ₁ , G ₂ , and G ₃ , respectively. On the other hand, carrier propagation conditions
The value of 113 is also P ₀ , P ₁ , P ₂ , P ₃ from the lowest bit.
The carrier input signal of each bit is C ₀ as shown in FIG.
Let (103), C ₁ (110), C ₂ (112), and C ₃ . At this time, C
₁ -C ₃ signal generation logic is as following equation. C ₁ = G ₀ + C ₀ · P ₀ C ₂ = G ₁ + C ₁ · P ₁ = G ₁ + G ₀ · P ₁ + C ₀ · P ₀ · P ₁ C ₃ = G ₂ + C ₂ · P ₂ = G ₂ + G ₁ · P ₂ + G ₀ · P ₂ · P ₁ + C ₀ · P ₀ · P ₁ · P ₂ As is clear from the above equation, the carrier input signal is determined by the carrier propagation condition and C ₀ only as a result of carrier generation. Therefore, it is not connected in series for each bit unit. Therefore, the carrier logic is accelerated regardless of the operation bit length. An embodiment is shown in FIG. 4, and this configuration is discussed in detail in "High-speed computer computing system" published by Modern Science Co., Ltd. In order to perform general addition / subtraction operation, the adder circuit of the above-mentioned full adder is necessary, but addition of a certain number and a constant whose effective bit length is much shorter than that number can be realized by a half adder adder circuit. . For example, the counter is an addition of a certain number and a constant 1. This configuration is shown in FIG. All upper bits except the lowest bit of constant 1 are 0
Therefore, at these bit positions, it is only necessary to add a certain number of inputs and the carrier. In this way, a configuration in which only two numbers are added (addition of three numbers in a full adder) is called a half adder configuration. Although this configuration has a smaller circuit scale than the configuration of the full adder, it can handle only addition. A one-bit operation is composed of a half adder circuit 120 and a carry circuit 121. Input x (lower bits x _0: 12
2, upper bit x ₁ : 123) and constant K are added, and output y
(Lower bit y ₀ : 124, Higher bit y ₁ : 125) is output.
Since the upper bit of the constant K is 0, there is no need to input it when adding. Therefore, only the lowest bit K ₀ : 126 is input in correspondence with the carrier input 103 in FIG. Since the upper bit of K is 0, the carrier circuit 121 does not need the carrier generation logic and sends only the carrier propagation result 127 to the upper bit as a carrier signal. [Problems to be Solved by the Invention] The above-mentioned prior art considers a method of performing an addition / subtraction operation in which the effective bit length of one of the two input signals is much shorter, by a half adder adder circuit. However, if this is performed by a full adder adder circuit, the carrier logic for speeding up becomes complicated and the circuit scale becomes large. An object of the present invention is to provide a method in which constant addition / subtraction can be realized by a half-adder addition circuit having a small circuit scale. [Means for Solving the Problems] The above-mentioned object is achieved by making the adder a half adder so that the input and output of this half adder can take both positive and negative logic. [Operation] When each bit of a certain value x expressed in binary number is inverted, the value becomes -x-1. When x-K is calculated, the value of x is first bit-inverted to obtain -x-1. Add K to this value. If the value of K is about 2 bits, this adder can be constructed by a half adder. The result after addition is -x-1 + K. Bit-reversing this result gives-(-x-1 + K) -1 = x-K,
Variable x-constant K can be calculated. x + K is K as it is, without bit inversion.
And output without bit inversion, the variable x + constant K can be calculated. By doing so, it is possible to execute subtraction only by constant addition by the conventional adder of the half adder. Embodiment An embodiment of the present invention will be described below with reference to FIG. The signal inversion circuit 1 is a selection circuit for outputting bit forward rotation or inversion data of input data. Half adder 2
In the adder of the constant K of several bits and the variable x or the bit x which is bit-inverted, the bit width of the constant K is formed by a full adder, and the bit positions on the upper side are formed by a half adder. When the constant K is subtracted from the variable x, the variable x is bit-inverted by the inverter INV1, added with the constant K by the half adder 2, and the result is bit-inverted by the inverter INV2 and output (y). To add the variable x and the constant K, the variable x may be added as it is to the constant K without bit-inversion, and the addition result may be output as it is (y). Fig. 6 shows 8-bit variable x (LSB = x0, MSB = x7) and constants 0 (K0 = K1 = 0), 1 (K0 = 1, K1 = 0), 2 (K0 = 0, K1).
= 1). The signal inversion circuit 1 shown in FIG. 1 is realized by the selection circuit 4 controlled by the control signal 8 as shown in FIG. When the subtraction with the constant is performed, the control signal 8 is set to the L level, and the variable x (x0 to x7) and the bit inversion data of the output 150 of the half adder 2 are selected and output. In the case of addition, the control signal 8 is set to H level to select and output bit normal data. The half adder 2 shown in FIG. 1 is composed of half bit adders 5 and 6 of 2 bit unit and carry look ahead (CLA) 7 in FIG.
The 2-bit unit half adder 5 on the lower-order side is a 2-bit constant K0, K1 and 2-bit LSB side data (variable x or bit-inverted variable x / x0, x1 or ▲ ▼, ▲
▼) is added. Addition of the lowest bit is x0 or ▲
Calculated as the addition of ▼ and K0. To add a bit one bit higher than the lowest bit, the OR generated by the lowest bit addition and the OR signal 151 of constant K1, x1 or ▲
Calculated as addition of ▼. Constant K0 = K1 = 1, that is, the operation of constant 3 is not supported, so carry and constant
K1 and 1 cannot be 1 together. The carrier 152 generated by the addition of the lower 2 bits is input to the carry look-ahead (CLA) 7 and the half adder 6 which adds the upper 2 and 3 bits from the lowest bit. The half adder 6 outputs the input 2-bit data x _i and x _{i + 1} and the carrier addition result 153, and at the same time, when the data x _i and x _{i + 1} are both 1, that is, the carrier propagation condition signal 154. Output. The carrier input 155,156 of the 2-bit unit half adder 6 on the upper bit side is obtained by carrying the carrier lookahead logic (CLA) 7 for the carrier 152 generated by the addition of the lower 2 bits and the carry propagation signal 154. Decide Since the upper 6 bits of the constant K are 0, the carrier propagation need only consider the propagation of the carrier to the upper bit side, which is generated by the addition of the lower 2 bits. The constant 0, 1, 2 adder / subtractor according to the present invention is used as an address calculator for a microprocessor or the like. If the data bus is a 16-bit microprocessor or the like, and the data is to be stacked, the stack address is calculated at the time of writing by adding +1 (byte data) or +2 (word data), and at the time of reading the stack address is calculated. Is-
Subtraction of 1, -2. The relationship between addition and subtraction in the address calculation can be considered in the opposite case. The instruction fetch address is added by +1 (byte fetch) or +2 (word fetch). As described above, most of the address operations of the processor are constant addition / subtraction operations. [Advantages of the Invention] According to the present invention, a high-speed constant adder / subtractor can be realized by a half adder and a carrier lock head circuit for only P signals, so that the circuit scale can be reduced.
The constant addition / subtraction can be widely used as the address calculation of the processor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the present invention, FIG. 2 is a block diagram of a conventional adder / subtractor, and FIG. 3 is a logic diagram of an adder using a full adder circuit.
FIG. 4 is a carrier-scheduled head circuit, FIG. 5 is a logic diagram of an adder (counter) using a half adder circuit, and FIG. 1 ... Signal inversion circuit, 2 ... Half adder, 4 ... Signal inversion circuit, 5 ... 2 bit half adder, 6 ... 2 bit half adder, 7 ... Carrier task head circuit.

Continuation of front page    (72) Inventor Hideo Nakamura               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshimune Hagiwara               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd.                (56) References JP-A-59-66790 (JP, A)                 JP-A-60-156139 (JP, A)                 JP 62-25325 (JP, A)                 JP-A-62-111362 (JP, A)                 JP 62-118436 (JP, A)                 JP 63-49835 (JP, A)

Claims (1)

(57) [Claims] 1. An address calculator for adding / subtracting a binary-valued constant having a bit length shorter than the operand to / from the operand to be represented by the address operation. A full adder to which the operand and the constant are input, and a half adder to which the operand is input and the constant is not input, and the full adder is at least the least significant of the addresses. The half adder is arranged on the higher bit side than the full adder on the lower bit side including the bit, and the full adder and the half adder are provided by rotating and inverting the bits of the operand. The address arithmetic unit is configured to be capable of being input to, and to be output by inverting and inverting the bits of the outputs of the full adder and the half adder. 2. When the operand is added to the constant, the normal data of the bit of the operand is input and the normal data of the output bit is output, and the constant is subtracted from the operand. When performing the above, the reverse data of bits of the operand is input and the reverse data of bits of the output is output.
The address calculator described in the item.