JP2907276B2 - Arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit for performing a two's complement operation.

[0002]

2. Description of the Related Art A conventional example of this type of arithmetic processing device is shown in FIG.
This will be described with reference to FIG. In FIG. 5, the arithmetic processing unit is divided into four groups of arithmetic units 34, 35, 36, and 37 that operate in parallel with four consecutive bits as one group for 16-bit input data A0 to A15. ing. Each operation unit group includes four input selection circuits 31 and four half adders 33. Further, the computing unit groups 34, 35 and 36 have four output selection circuits 38 in addition to the above configuration, and the computing unit groups 35 and 36 further have a selection circuit 39. The operation unit group 37 includes a carry selection circuit 32 in addition to the above configuration.

[0003] The input selection circuit 31 converts the logical inversion of each bit of the input data or each bit of the input data into the MSB (Most Significant Bit) of the input data.
Select and output. The carry selection circuit 32 of the operation unit group 37 selects and outputs the logical value “1” or the logical value “0” according to the MSB of the input data. The half adder 33 of the operation unit group 37 receives the output of the input selection circuit 31 and the output of the carry selection circuit 32 as inputs, and outputs the result of addition for each bit and the carry signal of the upper bit to the half adder 33.

The selection circuit 39 in the operation unit groups 35 and 36
Selects the carry signal of the half-adder 33 of the most significant bit in each operation unit group and outputs it as a control signal to the upper operation unit group.

[0005] In order to perform the operation at high speed, the operation units operate in parallel, and the output selection circuits 38 of the operation units 34, 35 and 36 are controlled by the control signals of the lower operation units as described above.

Conventionally, when calculating the absolute value of a two's complement number in this arithmetic processing device, when the input data is a negative number, the input selection circuit 31 selects the logical inversion of each bit of the input data, and the carry selection circuit 32 The logical value "1" is selected, and the two inputs are added in the half adder 33.
When the input data is a positive number, each bit of the input data is selected by the input selection circuit 31 and the carry selection circuit 32
, The logical value “0” is selected, and the two inputs are added in the half adder 33.

[0007]

As described above, in the prior art, the arithmetic unit is divided into a plurality of continuous bits in order to perform the arithmetic operation at high speed, and even if the arithmetic unit is operated in parallel, the arithmetic unit is determined by the value of the MSB of the input data. Since the input is determined, the calculation time depends on the MSB of the input data, and the high-speed operation has not been sufficiently achieved.

SUMMARY OF THE INVENTION It is an object of the present invention to speed up the operation by enabling the operation to be started before the value of the most significant bit is determined.

[0009]

According to the present invention, two or more arithmetic units which operate in parallel as a group of a plurality of continuous bits for N (N is a positive integer) input data are divided into two units. in the arithmetic processing unit for performing a complement operation, the arithmetic and logic unit group, said logic inverted data and the lower logical inversion data of the input data for each bit and inverting means Ru determined <br/> Me, for each bit
An operation is performed using a plurality of carry signals from the group of position arithmetic units as inputs, and the operation result and the carry signal resulting from the operation are calculated as described above.
One of the arithmetic means you output to each carry signal from position calculation unit group, a plurality of carry signals from the computing means
A carry output of the arithmetic means of the most significant bit of the plurality of contiguous bits most significant bits and the data of the input data
Selection means for <br/> force out by selecting the arithmetic unit group of the upper by at least one Chi, the most significant bit of the input data In the lowest group, with the remaining groups of the input data A plurality of output selecting means for selecting an operation result for each bit based on the most significant bit and a carry signal from a lower-order arithmetic unit group are provided.

The arithmetic means receives two carry signals as inputs, receives a first half adder which receives the logically inverted data and one of the carry signals, and a first half adder which receives the logically inverted data and the other carry signal. And a second half adder having the input as an input.

According to the present invention, N (N is a positive integer)
It is divided into a plurality of operation units that operate in parallel with a plurality of consecutive bits as one group with respect to the input data of bits, and
In the arithmetic processing unit that performs complementary operation of the arithmetic unit group includes an input selecting means for outputting a logic inverted data of the input data based on the ABS signal indicating "1" for each bit as the selected data, each bit Computing means for computing the selected data and a plurality of carry signals from the lower-order computing unit group as inputs, and outputting a computation result and a carry signal resulting from the computation for each carry signal from the lower-order computing unit group; and One of the plurality of carry signals from the arithmetic means is defined as the logical product of the logically inverted data of the most significant bit of the input data and the ABS signal indicating "1" and the most significant bit of the continuous plurality of bits. Selecting means for selecting and outputting to a higher-order arithmetic unit group by at least one of the carry outputs of the bit arithmetic means; Said a sense inverted data "1"
The logical product of the indicated ABS signal and the remaining group, the logically inverted data of the most significant bit of the input data and the "1"
And a plurality of output selecting means for selecting an operation result for each bit by a logical product of an ABS signal indicating the above and a carry signal from a lower-order operation unit group.

The arithmetic means receives two carry signals as inputs, and a first half adder which receives the selected data and one of the carry signals as inputs, and outputs the selected data and the other carry signal. And a second half adder as an input.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of the present invention. In this case, the arithmetic processing device is divided into four groups of arithmetic units 15, 16, 17, and 18 which operate in parallel with 16 bits of input data A0 to A15 as a group of continuous 4 bits. Each computing unit group has four inverting circuits 1
One and four operation units 12 are included, and operation unit groups 15 to 17 further have four output selection circuits 14, and operation unit group 18 has four output selection circuits 13, respectively. In addition, arithmetic unit group 1
6 and 17 have a selection circuit 1A in addition to the above configuration, and the operation unit group 18 has a selection circuit 19.

The inverting circuit 11 includes an inverter gate 11, as shown in FIG. The arithmetic unit 12 includes two half adders 121 and 122 as shown in FIG.
Consists of The half adder 121 includes an AND gate 1211 and an EX-OR (exclusive OR) circuit 1212,
The half adder 122 includes an AND gate 1221 and an EX-OR.
And a circuit 1222. The half adders 121 and 122 are
An operation is performed using a 1-bit logical inversion signal of input data and a separate carry signal as inputs, and the operation result is output. In each operation unit group, the operation unit 12 of the first bit inputs the power supply potential and the ground potential as carry signals and generates two carry outputs. The arithmetic unit 12 for the second and subsequent bits receives two carry outputs from the arithmetic unit 12 for the leading bit, and provides two carry outputs to the arithmetic unit 12 for the next bit.

As shown in FIG. 2 (c), the output selection circuit 13 includes an inverter gate 131 and a circuit for performing selection based on the value of the MSB of the input data. One of the two inputs is selected and output according to the value of the MSB of the data. The selection circuit 19
As shown in FIG. 2E, the two carry signals from the arithmetic unit 12 of the most significant bit of the arithmetic unit group 18 and the MSB of the input data are input, and the output is selected by the MSB of the input data. Output to the instrument group.

As shown in FIG. 2D, the output selection circuit 14 includes an inverter gate 141 and a carry signal of a lower-order operation unit group (for example, in the case of the output selection circuit 14 of the operation unit group 17, the output of the selection circuit 19 ) And a circuit for selecting based on the value of the MSB of the input data. The operation result from the operation unit 12 is input, and the two operation results and a logically inverted signal obtained by inverting one of them are input. Select any one and output. The selection circuit 1A is configured as shown in FIG.
As shown in (f), a circuit that receives two carry signals from the arithmetic unit 12 of the most significant bit and performs selection based on the carry signal of the group of lower arithmetic units, and a circuit that performs selection based on the MSB value of input data And the output is selected by the carry signal of the lower-order operation unit group and the MSB of the input data.
Output as a control signal to the higher-order computing unit group.

In FIG. 1, for convenience, for example, the output selection circuit 13 of the operation unit group 18 is shown such that the MSB of the input data is given only to the circuit of the least significant bit. It is needless to say that is given to all four output selection circuits 13 of the operation unit group 18. This is the same for the output selection circuits 14 of the operation unit groups 15, 16, and 17.

When calculating the absolute value of a two's complement number in this arithmetic processing unit, when the input data is negative, "1" can be added to the logical inversion of the input data to obtain the absolute value. In step 12, the result obtained by adding "1" to the logical inversion of the input data obtained by the inverting circuit 11 is selected by the MSB of the input data in the output selecting circuit 13, and in the output selecting circuit 14, the carry output of the lower-order operation unit group is output. By selecting the operation result, the absolute value of the input data can be obtained. When the input data is positive, the arithmetic unit 12 inverts the logic of the input data to “0”.
Are added to the output selection circuits 13 and 14
By selecting in, the absolute value of the operation input data can be obtained.

Therefore, the operation is executed irrespective of the value of the MSB of the input data, and the operation result is selected using the MSB of the input data.
It can be executed without depending on.

FIG. 3 is a view showing a second embodiment of the present invention. The arithmetic processing unit also has four arithmetic unit groups 25, 26, 27 and 2 that operate in parallel with 16-bit input data A0 to A15 as a group of continuous 4 bits.
8, and is divided. Each computing unit group includes four input selection circuits 21 and four computing units 22, and the computing unit group 2
5 and 28 further connect the four output selection circuits 23 to the computing unit group 2
6 and 27 each have four output selection circuits 24.
The operation unit groups 26 and 27 have a selection circuit 2D in addition to the above configuration, and the operation unit group 28 has a selection circuit 2C.

The input selection circuit 21, as shown in FIG. 4 (a), consists of a inverter gate 211 and the selection circuit,
Select one bit or logical inversion signal thereof in the input data by A BS signal output. The arithmetic unit 22 is configured as shown in FIG.
As shown in (b), it is composed of two half adders 221 and 222. The half adder 221 includes an AND gate 2211 and E
An X-OR circuit 2212, and the half adder 222
It comprises an AND gate 2221 and an EX-OR circuit 2222. The half adders 221 and 222 perform an operation with the carry signal different from the output of the input selection circuit 21 as an input, and output the operation result. In each of the arithmetic unit groups, the arithmetic unit 22 of the first bit inputs the power supply potential and the ground potential as carry signals and generates two carry outputs. The arithmetic unit 22 for the second and subsequent bits receives two carry outputs from the arithmetic unit 22 for the leading bit, and provides two carry outputs to the arithmetic unit 22 for the next bit.

The output selection circuit 23 receives the output of the arithmetic unit 22 as an input and, as shown in FIG.
31 and a circuit for selecting an output by an output (hereinafter, referred to as a control signal) of an AND gate 29 (FIG. 3) for performing a logical AND between the logical inversion of the MSB of the input data and the ABS signal . The control signal from the AND gate 29 is applied to all output selection circuits 23 in the arithmetic unit group 28.
The selection circuit 2C, as shown in FIG.
8 two carry signal from the arithmetic unit 22 of the most significant bit of an input, logic inversion and A BS of MSB of the input data
An output is selected by a control signal of an AND gate 29 (FIG. 3) which takes a logical product with a signal, and is output to a higher-order arithmetic unit group.

As shown in FIG. 4D, the output selection circuit 24 is provided with an inverter gate 241 and a carry signal of a group of lower-order operation units (for example, in the case of the output selection circuit 24 of the operation unit group 27, the output of the selection circuit 2C). ) by and a circuit for selecting the output by a control signal from the aND gate for taking a logical product of the logic inversion and the a BS signal MSB of the circuit and the input data to be selected (not shown), from the operator 22 The operation result is input, and one of the two operation results and a logically inverted signal obtained by inverting one of them is selected and output. As shown in FIG. 4 (f), the selection circuit 2D receives two carry signals from the arithmetic unit 22 of the most significant bit, performs selection by the carry signal of the lower arithmetic unit group, and the MSB of the input data. And a circuit for selecting an output by a control signal from an AND gate 29 (FIG. 3) for performing a logical product of the logical inversion and the ABS signal, and provides a carry output to a group of higher-order arithmetic units.

As with the output selection circuits 13 and 14 in FIG.
In the arithmetic unit groups 25, 26, 27, the outputs of the preceding selection circuits 2D, 2C are given to all the output selection circuits 23, 24.

With this arithmetic processing unit, it is possible to perform an absolute value operation and an increment operation of two's complement. When performing the absolute value operation, the input selection circuit 21 selects the logical inversion of the input data regardless of whether the input is positive or negative. Next, when the input data is negative, the logic of the input data is inverted.
Since the absolute value can be obtained by adding “1”, the result obtained by adding “1” to the logical inversion of the input data obtained by the input selection circuit 21 in the arithmetic unit 22 is output to the output selection circuit 2.
3 (in this case, the ABS is "1" and the logical inversion of the input data MBS is "0"). In the output selection circuit 24, the operation result is similarly determined by the value of the carry output of the lower operation unit group. By selecting, the absolute value of the input data can be obtained. When the input data is positive, the arithmetic unit 22 inverts the logic of the input data to “0”.
Are added to the output selection circuits 23 and 24.
, The absolute value of the input data can be obtained by selecting with the control signal.

When performing the increment operation, the input selection circuit 21 selects the value of the input data regardless of whether the input data is positive or negative. Since the arithmetic unit 22 is a half adder, a value obtained by adding “1” to the input data is output to the output selection circuits 23 and 2.
If the selection is made in step 4, the result of the increment operation can be obtained. Therefore, as in the first embodiment, the operation is executed regardless of the value of the MSB of the input data, and the operation result is selected using the MSB of the input data. Therefore, the operation start time depends on the MSB of the input data. It can be performed without doing.

The same operation can be performed even when the absolute value operation and the increment operation are combined.

[0028]

As described above, according to the present invention, the operation is performed using the logical inversion of the input data, and the operation result is selected based on the value of the most significant bit after the execution of the operation, so that the value of the most significant bit is determined. The operation can be executed even if the operation is not performed, and the operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of each unit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a specific configuration of each unit shown in FIG. 3;

FIG. 5 shows a circuit diagram of a conventional example.

FIG. 6 is a diagram showing a specific configuration of a main part shown in FIG. 5;

[Explanation of symbols]

 11 Inverting circuit 21, 31 Input selecting circuit 32 Carry selecting circuit 12, 22 Operation unit 33, 121, 122, 221, 222 Half adder 13, 14, 23, 24, 38 Output selecting circuit 1A, 19, 2C, 2D, 39 selection circuits 15-18, 25-28, 34-37

Claims (4)

(57) [Claims] 1. An arithmetic processing device for performing a two's complement operation by dividing a plurality of N-bit (N is a positive integer) input data into a plurality of operation units that operate in parallel with a plurality of consecutive bits as one group in each arithmetic unit group includes a reversal unit that obtains a logical inversion data of the input data for each bit, and <br/> plurality of carry signal from the logic inversion data and lower group of computing units for each bit Is calculated as an input, and the calculation result and
And a carry signal obtained by the operation from the lower-order operation unit group.
And arithmetic means you output to each carry signal, one of a plurality of carry signals from the computing means,
The least significant bit of the most significant bit of the input data and the carry output of the arithmetic means of the most significant bit of the plurality of consecutive bits
At least one means for selecting and outputting to the higher-order arithmetic unit group, and the most significant bit of the input data in the least significant group, and the most significant bit of the input data in the remaining group. And a plurality of output selecting means for selecting an operation result for each bit according to a carry signal from a group of the operation units. 2. The arithmetic processing device according to claim 1, wherein
The arithmetic means receives two carry signals as inputs, receives a first half adder that receives the logically inverted data and one of the carry signals as inputs, and receives the logically inverted data and the other carry signal as inputs. And a second half adder. 3. An arithmetic processing unit for performing a two's complement operation by dividing a plurality of operation units operating in parallel as a group of a plurality of continuous bits for N (N is a positive integer) input data In the above, each of the arithmetic unit groups includes : an input selection unit that outputs logically inverted data of input data as selection data based on an ABS signal indicating “1” for each bit; Computing means for computing the selected data and a plurality of carry signals from the lower-order operation unit group as inputs, and outputting an operation result and a carry signal resulting from the operation for each carry signal from the lower-order operation unit group; Calculating one of the plurality of carry signals from the logical unit of the logically inverted data of the most significant bit of the input data and the ABS signal indicating "1" and calculating the most significant bit of the continuous plurality of bits; hand Selecting means for selecting and outputting to the higher-order arithmetic unit group by at least one of the carry outputs of the stages; and in the lowest-order group, the logically inverted data of the most significant bit of the input data and the ABS indicating "1" In the remaining group, the logical product of the logically inverted data of the most significant bit of the input data and the ABS signal indicating "1" and the carry signal from the lower-order arithmetic unit group, respectively. An arithmetic processing device comprising: a plurality of output selecting means for selecting an operation result for each bit. 4. The arithmetic processing device according to claim 3, wherein
The arithmetic means receives two carry signals as inputs, a first half adder receiving the select data and one carry signal as inputs, and a second half adder receiving the select data and the other carry signal as inputs. And a half-adder.