JP2705162B2 - Arithmetic processing unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device having a plurality of arithmetic elements.

2. Description of the Related Art FIG. 3 shows a configuration of a conventional arithmetic processing device having a plurality of arithmetic elements. FIG. 3 shows, for example, a data path section of a floating-point arithmetic processor, wherein 1 is a multiport data memory, 2 is an adder / subtractor, 3 is a multiplier, and 4 is a divisor when performing division or square root using a multiplier. ROM that outputs the reciprocal of the reciprocal of the square root of the number to be square rooted, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14, and 15 are registers for holding binary data, respectively, and 16 is a data input / output unit between the data memory and the outside. All of these arithmetic units are usually constituted by an ordinary binary system.

The data flow in the conventional arithmetic processing device configured as described above will be described in detail.

First, when performing addition / subtraction, data is fetched from the data memory 1 into the registers 5 and 6 and
And the two data from the register 6 are in the binary system,
Is input to Here, after a normal binary arithmetic processing is performed, the result is written in a register 10 in a binary system and sent to the data memory 1.

Next, when performing multiplication, data is taken into the register 7 and the register 8 from the data memory 1, and two data from the register 7 and the register 8 are input to the multiplier 3 in a binary system. Here, after the normal binary system arithmetic processing is performed, the result is written to the register 11 in the binary system and sent to the data memory 1.

When performing further division, in the first division step, two data are output from the data memory 1, the dividend is taken into the register 13 and the divisor is taken into the register 9 and the register 14, and the data is read from the register 9 into the ROM 4 in a binary system. Is entered. Here division from the reciprocal R ₀ of the divisor read from ROM4 using multiplier 3 by the use of Newton Raphson method _{R i = R i-1 *} (2-R i-1 * Y) [Y: Divisor that By performing the operation several times, the precision of the reciprocal of the divisor read from the ROM 4 is increased, and finally, a result is obtained by the following operation: Z = R _i * X [X: dividend]. Here, the reciprocal of the data in the register 9 is read from the ROM 4 and written into the register 12. In the second division step, the data of the register 12 and the data of the register 14 are taken into the registers 7 and 8 and input to the multiplier 3 in a binary system, and the arithmetic processing in the normal binary system is performed. Is taken into the register 11. In the third step of division, only the data of the register 11 is taken into the register 6 and input to the adder / subtractor 2 in a binary system to perform subtraction from 2, and the result is stored in the register 10
Is written to. In the fourth division step, the data of the register 10 and the data of the register 12 are
Is input to the multiplier 3 in a binary system, the arithmetic processing is performed in a normal binary system, and the result is written in the register 11. In the fifth step of division, register
The data of 11 is fetched into the registers 7 and 15 and the data of the register 14 is fetched into the register 8 and input to the multiplier 3 in a binary system. Is written to. In the sixth division step, only the data in the register 11 is fetched into the register 6 and input to the adder / subtractor 2 in a binary system to perform subtraction from 2, and the result is written into the register 10. In the seventh step of the division, the data of the register 10 and the register 15
Is taken into the registers 7 and 8, input to the multiplier 3 in a binary system, the arithmetic processing in the normal binary system is performed, and the result is written in the register 11. In the eighth step of the division, the data of the register 11 is taken into the registers 7 and 15 and the data of the register 14 is taken into the register 8 and inputted to the multiplier 3 in a binary system. And the result is written to the register 11. In this way, the repetition of the fifth step to the seventh step is repeated several times to increase the precision of the reciprocal of the divisor read from the ROM 4. In the final step, the data of the register 11 and the dividend data of the register 13 are stored in the registers 7 and 8 After being input to the multiplier 3 in a binary system and subjected to arithmetic processing in a normal binary system, the result of the division is written in a register 11 in a binary system and sent to the data memory 1.

When square rooting is performed, in the square rooting first step, data is output from the data memory 1, the data is fetched into the register 9 and the register 14, and the data is input from the register 9 to the ROM 4 in a binary system. Here, the square root is the reciprocal of the square root of the square root number to be squared read from the ROM 4 using the multiplier 3 by using the Newton-Raphson method, from R ₀ to _Ri = R _i-1 * (3-R _i-1 ² * Y). The operation of / 2 is performed several times to increase the precision of the reciprocal of the square root of the number of square roots to be extracted from ROM4, and finally, the result is obtained by the operation of Z = R _i * Y. Here, the reciprocal of the data in the register 9 is read from the ROM 4 and written into the register 12.

In the square root second step, the data of the register 12 and the data of the register 14 are taken into the registers 7 and 8,
The data is input to the multiplier 3 in a binary system, the arithmetic processing is performed in a normal binary system, and the result is taken into the register 11.

In the third step of the square root, the data of the register 11 and the data of the register 12 are taken into the registers 7 and 8,
The data is input to the multiplier 3 in a binary system, the arithmetic processing is performed in a normal binary system, and the result is taken into the register 11.

In the fourth step of the square root, only the data of the register 11 is taken into the register 6, input to the adder / subtractor 2 in a binary system, subtracted from 3, shifted right by one bit, and the result is written into the register 10.

In the fifth square root step, the data of the register 10 and the data of the register 12 are fetched into the registers 7 and 8,
The data is input to the multiplier 3 in the binary system, the arithmetic processing is performed in the normal binary system, and the result is written in the register 11.

In the sixth square root step, the data of the register 11 is stored in the registers 7 and 15 and the data of the register 14 is stored in the register 8.
Is input to the multiplier 3 in a binary system, the arithmetic processing is performed in a normal binary system, and the result is written in the register 11.

In the square rooting seventh step, the data of the register 11 and the data of the register 15 are taken into the registers 7 and 8,
The data is input to the multiplier 3 in a binary system, the arithmetic processing is performed in a normal binary system, and the result is taken into the register 11.

In the eighth step of the square root, only the data in the register 11 is taken into the register 6, input to the adder / subtractor 2 in a binary system, subtracted from 3, shifted right by 1 bit, and the result is written into the register 10.

In the ninth square root step, the data of the register 10 and the data of the register 15 are taken into the registers 7 and 8,
The data is input to the multiplier 3 in a binary system, the arithmetic processing is performed in a normal binary system, and the result is taken into the register 11.

In the tenth square root step, the data of the register 11 is stored in the registers 7 and 15 and the data of the register 14 is stored in the register 8.
Is input to the multiplier 3 in a binary system, the arithmetic processing is performed in a normal binary system, and the result is written in the register 11.

In this manner, the accuracy of the reciprocal of the square root of the number of square roots read out from the ROM 4 is increased by performing the repetitive multiplications from the sixth step to the ninth step several times, and the data in the register 11 and the data in the register 14 7 and are taken into the register 8 and input to the multiplier 3 in the binary system. After the arithmetic processing in the ordinary binary system is performed, the result of the square root is written in the register 11 in the binary system and is stored in the data memory 1. Sent.

Here, assuming that addition and subtraction and multiplication are each one machine cycle, in consideration of division, if repetition of multiplication is performed three times in order to increase the accuracy of the ROM, depending on the accuracy of the ROM, 1 Y − _{-> R 0 2 R 0 *} Y 3 R 0 * Y 4 R 0 * (2-R 0 * Y) = R 1 5 R 1 * Y 6 2-R 1 * Y 7 R 1 * (2-R 1 _{* Y) = R 2 8 R} 2 * Y 9 2-R 2 * Y 10 R 2 * (2-R 2 * Y) = R 3 11 R 3 * calculation that the result of performing, such as X, the 11 cycles Calculation time is required.

Also when considering No. and depending on the accuracy of the ROM and performs iterative multiplication of 3 times to increase the accuracy of the ROM, in each _{cycle, 1 Y -> R 0 2} R 0 * Y 3 2- ^{_{R 0 2 * Y 4 (3}} -R 0 2 * Y) / 2 5 R 0 * (3-R 0 * Y) / 2 = R 1 6 R 1 * Y 7 R 1 2 * Y 8 (3-R ^{_{1 2 * Y) / 2 9}} R 1 * (3-R 1 2 * Y) / 2 = R 2 10 R 2 * Y 11 R 2 2 * Y 12 (3-R 2 2 * Y) / 2 13 R ^{_{2 * (3-R 2 2}} * Y) / 2 = R 3 14 R 3 * calculation that the result of performing, such as Y, is required calculation time of 14 cycles.

References: (S. Kuninobu et al .: Eye, Lee, Lee,
B Proceeding The 8th Computer Arithmetic Symposium (IEEE Proc. 8th Sympo.on Computer Arithmet
ic) According to PP.80-86, 1987), in the multiplier, the input / output is a normal binary system, and the SD display with redundancy is used as internal logic to reduce the number of gate stages and reduce the number of transistors. , And the speed can be increased with a simpler wiring.

Problems to be Solved by the Invention When considering an operation using repetitive multiplication such as division or square root equalization using a multiplier using an SD number system as the internal logic described above, the multiplication result of this multiplier is an SD number system. Because
This SD system must be converted into a binary system and then input to the multiplier, which hinders high-speed arithmetic processing.

In addition, in an algorithm of division or square root equalization using iterative multiplication, a process of subtracting a constant from input data is performed using an adder / subtractor, which hinders high-speed processing such as a subtraction process.

The present invention has been made in view of the above circumstances, and has as its object to provide a high-speed arithmetic processing device that reduces the arithmetic time.

Means for Solving the Problems A first arithmetic processing device according to the present invention includes first input data,
Multiplication means for inputting two input data in which one of the second input data is data using a signed digit system, and outputting a multiplication result expressed in the number system; Operating means for operating a multiplication result expressed in a system and third input data, and outputting an operation result expressed in the number system, wherein the operation result expressed in the number system remains unchanged in the number system It is configured to input as input data of the multiplying means.

Further, the second arithmetic processing device of the present invention comprises: a first arithmetic means for outputting data expressed in a numerical system by a signed digit in which each digit is composed of 2 bits; Data to be output is input, and the upper digit portion performs logical inversion of only one of the two bits, and the lower digit portion performs logical inversion of only the other bit, and outputs data expressed in the numerical system. This is a configuration including a second arithmetic unit.

Effect The first arithmetic processing device of the present invention, when performing an arithmetic operation using repetitive multiplication using a multiplication unit using a number system with a signed digit according to the configuration described above, performs multiplication on the multiplication result of the multiplication unit. After performing a predetermined operation, the data is data using a numerical system using signed digits, but this data can be directly input to the multiplication means without being converted into binary.

In addition, the second arithmetic processing device of the present invention employs an adder / subtractor because the above-described configuration performs a process of subtracting a constant from input data by a bit operation taking advantage of a characteristic of a number system using signed digits. There is no need.

Embodiment FIG. 1 shows an embodiment of the present invention. 1 is a multiport data memory, 2 is an adder / subtracter, 3 is a multiplier, 4 is an arithmetic circuit used when performing division or square root using a multiplier,
5 is an RO that outputs the reciprocal of the divisor or the square root of the number to be squared when performing division or square root using a multiplier.
M, 6, 7, 9, 10, 11, 13, 14, 15 are registers for holding binary data, 8, 12 are registers for holding SD display data with redundancy, and 16 is data memory. And an external input / output unit.

This is different from the configuration shown in FIG. 3 which shows the conventional example, in which the multiplier 3 and the arithmetic circuit 4 use the SD display with redundancy in the internal logic, and the arithmetic result using the multiplier 3 and the arithmetic circuit 4 is used. Is sent to the adder / subtractor 2 as positive / negative two data to perform subtraction, and the
And then send it to the data memory. In addition, in the division or square root using the multiplier 3, in order to make use of the feature of SD display having redundancy in the repetitive multiplication, that is, the multiplication result is not converted to binary data and can be used as it is for the next multiplication. By adapting the internal recoding unit to the SD display with redundancy and by adapting the registers 8 and 12 to the SD display with redundancy, a data path configuration (one SD display data having redundancy uses two data paths.)

 Hereinafter, the data flow will be described in detail.

First, when performing addition / subtraction, data is fetched from the data memory 1 into the registers 6 and 7 and
And two data from the register 7 in a binary system with an adder / subtracter 2
Is input to Here, after the arithmetic processing in the ordinary binary system is performed, the result is written in the register 11 in the binary system and sent to the data memory 1.

Next, when performing multiplication, data is taken into the register 8 and the register 9 from the data memory 1, and two data from the register 8 and the register 9 are input to the multiplier 3 in a binary system. Here, since the register 8 is a register adapted to the SD display having redundancy, when binary data comes from the data memory 1 or the ROM 5, the bit representing the negative value of the data input to the multiplier 3 is 0. become. The two input data are subjected to arithmetic processing by the SD display with redundancy inside the multiplier 3 and the result is passed through the arithmetic circuit 4 (multiplication mode) to the register 12 where the SD display with redundancy is displayed. It is kept as it is. Then, as two positive and negative data, 2
The data is taken into the register 6 and the register 7 in a hexadecimal system and input to the adder / subtractor 2. After performing the subtraction process (converting from SD display with redundancy to binary display data) using the ordinary binary system, the result of the multiplication is registered in the binary system.
11 is sent to the data memory 1. Here, assuming that the operation time required for the adder / subtracter and the multiplier is one machine cycle, two cycles of operation time are required for multiplication.

When performing further division, in the first step of division, two data are output from the data memory 1, the dividend is stored in the register 14, the divisor is captured in the register 10 and the register 15, and the data is stored in the ROM 5 in a binary system from the register 10. Is entered. Here, the reciprocal of the data in the register 10 is read from the ROM 5 and written into the register 13. Divided by the second step, the data of the data and the register 15 of the register 13 is inputted to the multiplier 3 in binary systems incorporated in the register 8 and the register 9, the SD display operation that R ₀ * Y is presence of redundancy And the result is calculated by the arithmetic circuit 4 as 2-R ₀ * Y [ Indicates that the result is an SD display with redundancy. ] (Divide mode) and register
The SD display with redundancy in 12 is kept as it is. In the third step of the division, the data of the register 12 and the data of the register 13 are taken into the registers 8 and 9, the SD display with redundancy is provided from the register 8, and the data is inputted to the multiplier 3 from the register 9 in a binary system. , R ₀ * ( 2−R ₀ * Y ) = R ₁ is performed by the SD display with redundancy, and is passed through the arithmetic circuit 4 (multiplication mode) to the register 12 while the SD display with redundancy remains as it is. Will be retained. In the fourth step of division, the data of the register 12 and the data of the register 15 are fetched into the registers 8 and 9, and the SD display with redundancy exists from the register 8, and the data is input to the multiplier 3 from the register 9 in a binary system. , R _i * Y are performed by the SD display with redundancy, and the result is processed in the arithmetic circuit 4 as 2- R _i * Y (divide mode), and the SD display with redundancy in the register 12 is performed. It is kept as it is. In parallel with this operation, the data from the register 12 is taken into the register 6 and the register 7 in a binary system as two data of positive and negative, and is inputted to the adder / subtractor 2. Here, after a subtraction process (conversion from SD display with redundancy) to binary display data is performed in a normal binary system, the result is written into the register 11 in a binary system. In the fifth step of division, register
The data of the register 12 and the data of the register 11 are taken into the register 8 and the register 9, and the SD from which the redundancy exists
The display and the register 9 are input to the multiplier 3 in a binary system, and the operation of R ₁ * ( 2-R ₁ * Y ) = R ₂ is performed by the SD display with redundancy, and the operation circuit 4 (multiplication mode ) Is stored in the register 12 as the SD display with redundancy. In the sixth division step, the data in the register 12 and the data in the register 15 are fetched into the registers 8 and 9, and the SD display with redundancy is input from the register 8, and the data is input to the multiplier 3 from the register 9 in a binary system. , R ₂ * Y are performed by the SD display with redundancy, and the result is processed in the arithmetic circuit 4 as in 2- R ₂ * Y (division mode), and the SD display with redundancy is displayed in the register 12. It is kept as it is. In parallel with this operation, the data from the register 12 is taken into the register 6 and the register 7 in a binary system as two data of positive and negative, and is inputted to the adder / subtractor 2. Here, after a subtraction process (conversion from SD display with redundancy) to binary display data is performed in a normal binary system, the result is written into the register 11 in a binary system. Thus, from the fourth step to the fifth
The repetition of the divisor read from the ROM 5 is repeated several times to increase the precision of the reciprocal of the divisor. In the last previous step, the data of the register 12 and the dividend data of the register 14 are taken into the registers 8 and 9, and
From the register, an SD display with redundancy is input. The register 9 is input to the multiplier 3 in a binary system, and an operation of R _i * X is performed by the SD display with redundancy, and passes through the arithmetic circuit 4 (multiplication mode). Therefore, the SD display with redundancy is held in the register 12 as it is. In the final step,
The data from the register 12 is 2 as positive and negative data.
The data is taken into the register 6 and the register 7 in a hexadecimal system and input to the adder / subtractor 2. Here, after a subtraction process (conversion from SD display with redundancy) to binary display data is performed in a normal binary system, the result is stored in a register 11 in a binary system.
And sent to the data memory 1.

When square rooting is performed, in the square rooting first step, data is output from the data memory 1, the data is fetched into the registers 10 and 15, and the data is input from the register 10 to the ROM 5 in a binary system. Here, the reciprocal of the square root of the data in register 10 is read from ROM 5 and
Is written to. In the second square root step, the data in the register 13 and the data in the register 15 are
Is input to the multiplier 3 in a binary system, an operation of R ₀ * Y is performed by the SD display with redundancy, and the SD with redundancy is stored in the register 12 through the arithmetic circuit 4 (multiplication mode). It is kept as displayed. In the third step of the square root, the data of the register 12 and the data of the register 13 are fetched into the registers 8 and 9, the SD display with redundancy is input from the register 8, and the data is input to the multiplier 3 from the register 9 in a binary system. The operation R ₀ * R ₀ * Y is performed by the SD display with redundancy, and the result is processed by the arithmetic circuit 4 as (3- R ₀ ² * Y ) / 2 (open square mode), The SD display with redundancy is kept in the register 12 as it is. In the fourth step of the square root, the data of the register 12 and the data of the register 13 are taken into the registers 8 and 9, the SD display with redundancy is provided from the register 8, and the data is inputted to the multiplier 3 from the register 9 in a binary system. The operation of R ₀ * (3-R ₀ ² * Y) / 2 = R ₁ is performed by the SD display with redundancy, and the SD display with redundancy in the register 12 through the arithmetic circuit 4 (multiplication mode). It is kept as it is. In the fifth step of the square root, the data of the register 12 and the data of the register 15 are fetched into the registers 8 and 9, the SD display with redundancy is input from the register 8, and the data is input to the multiplier 3 from the register 9 in a binary system. The operation of R ₁ * Y is performed by the SD display with the redundancy, and is passed through the arithmetic circuit 4 (multiplication mode) and held in the register 12 as the SD display with the redundancy. In parallel with this operation, the data from the register 12 is taken into the register 6 and the register 7 in a binary system as two data of positive and negative, and is inputted to the adder / subtractor 2. Here, after a subtraction process (conversion from SD display with redundancy) to binary display data is performed in a normal binary system, the result is written into the register 11 in a binary system. In the sixth step of Kaiping, register
The data of the register 12 and the data of the register 11 are taken into the register 8 and the register 9, and the SD from which the redundancy exists
The register 9 is input from the register 9 to the multiplier 3 in a binary system, and the operation of R ₁ * R ₁ * Y is performed by SD display with redundancy, and the result is calculated by the arithmetic circuit 4 as (3- R ₁ ² * Y) / 2 (square root mode), and the SD display with redundancy is kept in the register 12 as it is. In the seventh square root step, the data of the register 12 and the data of the register 11 are fetched into the registers 8 and 9, the SD display with redundancy is input from the register 8, and the data is input to the multiplier 3 from the register 9 in a binary system. Te done by _{R 1 * (3-R 1} 2 * Y) / 2 = SD display operation that R ₂ is presence of redundancy, the ALU 4 (multiply mode) the through with SD display that exist redundancy in the register 12 It is kept as it is. In the eighth square root step, the data of the register 12 and the data of the register 15 are fetched into the registers 8 and 9, the SD display with redundancy is input from the register 8, and the data is input to the multiplier 3 from the register 9 in a binary system. The operation of R ₂ * Y is performed by the SD display with redundancy, and is passed through the arithmetic circuit 4 (multiplication mode) and is retained in the register 12 as the SD display with redundancy. In parallel with this operation, the data from the register 12 is taken into the register 6 and the register 7 in a binary system as two data of positive and negative, and is inputted to the adder / subtractor 2. Here, after performing the subtraction processing (converting from SD display with redundancy to binary display data) using the normal binary system, the result is stored in the binary system.
Written to 11. In this way, the repetition of the fifth step to the seventh step is repeated several times to increase the accuracy of the reciprocal of the square root of the square root of the square root to be read out from the ROM 5, and the data of the register 12 and the register 15
Is input to the registers 8 and 9, the SD display with redundancy exists from the register 8, and the data is input to the multiplier 3 in a binary system from the register 9 and processed as R _i * Y. The data is passed through the arithmetic circuit 4 (multiplication mode) and stored in the register 12 in the SD display with redundancy. In the final step, the data from the register 12 is taken into the register 6 and the register 7 in a binary system as two data of positive and negative, and is inputted to the adder / subtractor 2. Here, after a subtraction process (conversion from SD display with redundancy) to binary display data is performed in a normal binary system, the result is written in a register 11 in a binary system and the data is stored in the data memory 1.
Sent to

The data input / output unit 16 inputs and outputs data between the data memory 1 and the outside.

Here, a description will be given of an arithmetic circuit used when performing division or square root using SD display having redundancy as internal logic. The division uses the reciprocal R ₀ of the divisor Y read from the ROM as described above, and repeats the operation of R _i = R _i-1 * (2-R _i-1 * Y) to increase the precision of the reciprocal of the divisor. However, Y is assumed to be a normalized value, and the value read from the ROM is considered as R ₀ = 1 / Y ± a (where 1 ≦ Y <2, a ≦ 2- ⁿ ). And the data input to the arithmetic circuit 4 are: Which are values close to 1 (in this case, the error is
2 ^-n or less). There are many Expressing a value close to 1, which is input to the arithmetic circuit 4 in SD display that exist redundancy but, paying attention to two ^ones place following 000.11111 000.00000 010. 01.00000 10. 1.00000 (where -1 ) Is limited to six. In the case of an SD display having redundancy in which one bit is represented by a sign bit and an absolute value bit, a subtraction value can be represented very easily by considering subtraction from 2 for the above value. That is, inverting the absolute value of the bit logic on 2 ¹ digit of bits (0 -> 1 or 1 ->
0), the position following bits of 2 ⁰ inverts the logic of the sign bit (0 - obtained from subtraction value by> 0) -> 1 or 1. For example, the subtraction value of the above six values from 2 is: 1. 0.111111 01. 0.111111 01. The bits of each digit are represented as follows.

(The initials are I for input and O for output, S for sign bit, A
Is an absolute value bit, and a subscript represents each digit. ) However, the significant bits than 2 ^1, the data input to the arithmetic circuit 4 has a value close to 1 as described above, so that it may be ignored only in this case. In order to increase the accuracy of the value output from the ROM 5 at the time of division in this way, it is very easy to perform the subtraction while the SD display having redundancy exists.

And using the reciprocal R ₀ of the square root of the number Y of No. read from the ROM as described above in the case of No., the arithmetic that _{R i = R i-1 *} (3-R i-1 2 * Y) / 2 Is repeated to increase the accuracy of the reciprocal of the square root of the square root of the square root, but Y is a normalized value and ROM
The value read from (However, it is assumed that 1 ≦ Y <2, a ≦ 2 ⁻² ). Considering the processing as follows, the data input to the arithmetic circuit 4 is Which are values close to 1 (in this case, the error is
2 ^-2n or less). For No. also present numerous Expressed in SD display that exist redundancy a value close to 1, which is input to the subtraction circuit 4, but the same as for the division to focus on 2 ¹ place below. When positively fix the bits for 2 ⁰ of positions over the six values would 00.11111 01.00000 10. 01.00000 10. Three values except 01.00000 becomes the same value. Considering the subtraction from 3 for these values, the subtraction value can be represented very simply as in the case of division.

That is, 2 ¹ position and inverting the absolute value of the bit logic on position following bits of 2 ⁰ (0 -> 1 or 1 -> 0),
For the 2 ⁻¹ bit, a subtraction value can be obtained by inverting the logic of the sign bit (0-> 1 or 1-> 0). For example, the subtraction value of 3 from the above three values is 11. 10. 01.11111. Considering six values near 1 which are input to the arithmetic circuit 4 and represented by the SD notation with redundancy, each bit is expressed as follows.

As with the division, for the upper bits than 2 ^1, the data inputted to the ALU 4 may be ignored because assumes a value close to 1 as described above. Furthermore, the result is 2
The operation of dividing by 1 only needs to be shifted to the right by one bit, so the operation of subtracting the data input to the arithmetic circuit 4 from 3 and further dividing the result by 2 is It is represented as

As described above, the arithmetic circuit which performs the processing of subtracting the data input at the time of division from 2 and the processing of subtracting the data input at the time of square root from 3 and further dividing the result by 2 is shown in FIG. The processing of this circuit can be performed in the same cycle as the multiplier 3.

Here, assuming that the operation time required for the adder / subtracter and the multiplier is one machine cycle, when considering division, ROM
If Depending on the accuracy and repeating the multiplication 3 times to increase the accuracy of the ROM, in each _{cycle, 1 Y -> R 0 2} 2-R 0 * Y 3 R 0 * (2-R 0 _{* Y) = R 1 4 2-} R 1 * Y 5 R 1 * (2-R 1 * Y) = R 2 6 2- R 2 * Y 7 R 2 * (2-R 2 * Y) = R 3 _{8 R 3 * X = Z 9} Z -> will be performed operations such as Z, is required calculation time of 9 cycles.

Also, considering square root, if it is attempted to repeat the multiplication three times in order to increase the accuracy of the ROM, depending on the accuracy of the ROM, then in each cycle, 1 Y-> R ₀ 2 R ₀ * Y 3 ( _{3-R 0 * R 0 *} Y) / 2 4 R 0 * (3-R 0 * R 0 * Y) / 2 = R 1 5 R 1 * Y 6 (3-R 1 * R 1 * Y) / _{2 7 R 1 * (3-} R 1 * R 1 * Y) / 2 = R 2 8 R 2 * Y 9 (3-R 2 * R 2 * Y) / 2 10 R 2 * (3-R 2 * _{R 2 * Y) / 2 =} R 3 11 R 3 * Y = Z 12 Z -> will be performed operations such as Z, are required 12 cycles of calculation time.

As described above, according to the present embodiment, the multiplier and the multiplication unit having the SD display with redundancy as internal logic capable of high-speed processing can reduce the operation time of the multiplication or division and the repetitive multiplication in the square root. And the machine cycle can be reduced. By making the arithmetic circuit used for division and square root as described above, the subtraction process can be performed simultaneously with the multiplication in the previous cycle, and one cycle is performed each time the multiplication is repeatedly performed. Because the calculation time of
The calculation time of division and square root becomes extremely short.

From this, in addition to being able to perform a variety of operations with a small amount of hardware, the operation time for each operation is reduced, and the operation time ratio of division for addition, subtraction, multiplication and square root is reduced. High performance.

In the present embodiment, the SD display with redundancy is used as the internal logic of the multiplier. However, the SD display with redundancy can be used as the internal logic for the adder / subtractor. The configuration is not limited to this embodiment.

Effect of the Invention As described above, the first arithmetic processing device according to the present invention includes:
When performing an operation using repeated multiplication using a multiplying means using a signed digit number system, after performing a predetermined operation on the multiplication result of the multiplying means, a signed digit number system was used. Data.
Since the data is directly input to the multiplication means without being converted into a hexadecimal value, the arithmetic processing can be shortened accordingly.

Further, the second arithmetic processing device of the present invention performs a process such as subtracting a constant from input data by bit operation by utilizing the features of the numerical system using signed digits.
High-speed subtraction processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of an arithmetic processing unit according to the present invention, FIG. 2 is a circuit diagram of an arithmetic circuit capable of performing multiplication and subtraction in the same cycle during division and square root, and FIG. Is a block diagram of a conventional arithmetic processing device. 1 data memory, 2 adder / subtractor, 3 multiplier
4 arithmetic circuit, 5 ROM, 6 to 15 registers, 16
... Data input / output unit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shigeo Kuninobu 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (56) References JP-A-1-266628 (JP, A) Interface, 11 [ 3] (Showa 60.3), CQ Publishing, p. 245

Claims (6)

(57) [Claims] 1. A method according to claim 1, wherein one of the first input data and the second input data receives two input data as data using a number system with a signed digit, and is represented by the number system. A multiplication unit that outputs a multiplication result; and a calculation unit that calculates the multiplication result expressed in the number system and third input data, and outputs an operation result expressed in the number system. An arithmetic processing apparatus characterized in that the expressed arithmetic result is input as input data of the multiplying means as it is in the numerical system. 2. The method according to claim 1, wherein said calculating means is subtracting means, and said third means is a subtracting means.
2. The arithmetic processing device according to claim 1, wherein the input data is a constant. 3. The data expressed by the number system is 2 in each digit.
3. The arithmetic processing device according to claim 1, wherein the data is data expressed in a redundant binary number system composed of bits. 4. The arithmetic means inputs a multiplication result and divides the multiplication result into an upper digit portion and a lower digit portion, wherein the upper digit portion is one of the two bits and the lower digit portion. 4. The arithmetic processing device according to claim 3, wherein the portion is configured by an arithmetic circuit that performs a bit operation on each of the other bits. 5. A first arithmetic means for outputting data expressed in a numerical system by a signed digit in which each digit is composed of 2 bits, and inputting data output from said first arithmetic means, A second arithmetic unit for performing a logical inversion on only one of the two bits in the upper digit portion and a logical inversion on the other bit only in the lower digit portion, and outputting data expressed in the numerical system; An arithmetic processing device, characterized in that: 6. The arithmetic processing device according to claim 5, wherein said first arithmetic means is a multiplication means.