JP3315042B2 - Multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a booth method (Boo
th's method), and more specifically, in the case of a singular calculation that is a combination of a multiplier and a multiplicand that cannot obtain a correct multiplication result by a normal process of the multiplication device, It relates to means for correcting.

[0002]

2. Description of the Related Art To execute multiplications faster, LS
Methods for realizing multiplication by hardware such as I (large-scale integrated circuit) have been studied. In this case, how small the circuit, that is, how small the area on the semiconductor substrate,
It is important how fast the multiplication can be performed.

In realizing such multiplication by hardware, Booth's method (Booth's method) is used as a multiplication method.
d) is often used. On the premise of the Booth method, a proposal for realizing a high-speed and low-cost multiplier (Japanese Patent Publication No. 57-28129) and a proposal for reducing the power consumption of the multiplier have been made (Japanese Patent Application No. 1993-287, pp. 157-287). Flat 7
-259826).

In general, in order to obtain the product of the multiplicand X and the multiplier Y, first, as shown in FIG.
, A partial product with the multiplicand X is calculated, and then the respective partial products are added (cumulative addition). In the process of such multiplication, much time is required for adding partial products. Therefore, if the number of terms of the partial product can be reduced, the speed of the multiplication can be increased. Therefore, in the secondary booth method, FIG.
By reducing the number of partial products to about half as shown by 0, multiplication is speeded up. In the secondary booth method, multiplication by two's complement notation, that is, multiplication in which positive and negative numbers are mixed, can be executed without correction. Hereinafter, the method of the secondary booth will be specifically described.

[0005] Assuming that the multiplier Y is represented by two's complement, the multiplier Y can be expressed as follows. Y = −y _n · 2 ⁿ + Σ (i = 0, n−1) y _i · 2 ⁱ = −y _n · 2 ⁿ + y _n−1 · 2 ⁿ⁻¹ + y _n−2 · 2 ⁿ⁻² + · ·· + y ₀ · 2 ⁰ (1) Here, y _n is a sign bit, and y _{n-1 to} y ₀ are numerical values. In the above, “Σ” is a symbol of the sum, and “Σ (i = n1, n2)” is i = n1 to i for the next term.
= N2 (the same applies hereinafter). From the above equation (1), the multiplicand X and the multiplier Y
Can be expressed as follows. P = X · Y = −y _n · 2 ⁿ · X + y _n−1 · 2 ⁿ⁻¹ · X + y _n−2 · 2 ⁿ⁻² · X +... + Y ₀ · 2 ⁰ · X = (y ₋₁ + y ^{_{0 -2y 1) 2 0 · X}} + (y 1 + y 2 -2y 3) 2 2 · X + ··· + (y n-2 + y n-1 -2y n) 2 n-1 · X = Σ (j = 0, (n-1) / 2) (y 2j-1 + y 2j -2y 2j + 1) 2 2j · X ... (2) where a y _-1 = 0, n is an odd number.

In the above equation (2), (y _2j-1 + y _2j -2y _{2j + 1} ) 2 ^2j · X (3) is a partial product in the secondary booth method, and the number of partial products is (n + 1) ) / 2. Therefore, compared to the general method of finding the partial product with the multiplicand for each bit of the multiplier,
The number of terms has been reduced by half.

The coefficients (y _2j-1 + y _2j -2y _{2j + 1} ) (4) in the partial product represented by the above equation (3) are three consecutive bits y _2j-1 , y _2j , y in the multiplier Y.
_It is determined by the value of _{2j + 1 and} is _one of 0, ± 1, ± 2. Therefore, the partial product in the secondary booth method is any of 0, ± X · 2 ^2j , ± 2X · 2 ^2j . Accordingly, by preparing a circuit for performing each operation of setting the multiplicand X to 0, leaving it as it is, doubling it, and finding a two's complement (inverting the sign) as a partial product generation circuit, Partial products can be obtained. At this time, an operation signal indicating which of these operations is performed on the multiplicand X is required.
Signals CX and C2 defined by the truth table shown in FIG. 11 using the values of three consecutive bits _y2j-1 , _y2j , and _{y2j + 1} .
What is necessary is just to prepare a circuit (called a “booth decoder”) that creates X and Ccomp as operation signals. Here, the operation signal CX indicates whether to keep the multiplicand X as it is, the operation signal C2X indicates whether to double the multiplicand X, and the operation signal Ccomp indicates whether to obtain the two's complement of the multiplicand X. Indicates The "state" in this truth table indicates the content of the partial product, and specifically, the portion of (y _2j-1 + y _2j -2y _{2j + 1} ) X in equation (3) of the partial product (The same applies to other truth tables described later). From this truth table, the operation signals CX, C2X, Ccomp can be expressed by the following logical expressions. CX = _yi-1 (+) _yi (5) C2X =! ｛(Y _i-1 (+) y _i ) +! (Y _i (+) y _{i + 1} )｝ (6) Ccomp = y _{i + 1} (7) where i = 0, 2, 4,..., Where “(+)” is exclusive logic The sum operator, "!"
Is a logical negation operator, and "! A" indicates an inverted value of a (the same applies hereinafter).

Since the partial product corresponding to j = 0 is (y _-1 + y ₀ -2y ₁ ) 2 ^2j · X = (y ₀ -2y ₁ ) 2 ^2j · X, the operation signals CX, C2X, The truth table defining Ccomp is as shown in FIG. 12, and these operation signals can be represented by the following logical expressions. _{CX = y 0 ... (8)} C2X =! (Y ₀ +! Y ₁ ) (9) Ccomp = y ₁ (10) where i = 0, 2, 4,...

Each partial product (j = j) shown in the above equation (3) obtained using the above-described Booth decoder and partial product generation circuit
, (N-1) / 2), the product P of the multiplicand X and the multiplier Y can be obtained. By the way, 2's complement 2
Each partial product obtained by the Booth's method in the base multiplication is represented in two's complement. Therefore, the above product P
In the calculation of, as shown in FIG. 13, a correct product P cannot be obtained without sign extension and addition of the lower partial product (in FIG. 13, “△” indicates that the sign bits of the partial product are aligned). Are shown as sign extension bits).
However, when such a sign extension is performed, the number of bits of the partial product increases, and the amount of hardware for adding the partial product increases. Then, in order to avoid this situation, addition of partial products is performed as follows.

[0010] Now, representing the partial product PP bit length m with ^{_{PP = -a m 2 m + a}} m-1 2 m-1 + a m-2 2 m-2 + ··· + a 0 2 0 ... (11) Let us consider the extension of the sign bit. Here, when the sign bit a _m extended r ^{_{bits, PP = -a m 2 m +}} r + a m 2 m + r-1 + ··· + a m 2 m + 1 + a m 2 m + a m-1 _{^{2 m-1 + a m-}} 2 2 m-2 + ··· + a 0 2 0 ... is (12). Furthermore, a _m = 1-! a _m ... and put a (13), PP = (1- a m!) (- 2 m + r +2 m + r-1 + ··· +2 m + 1 +2 m) + a m-1 2 m-1 ^{_{+ a m-2 2 m-}} 2 + ··· + a 0 2 0 = -2 m + r +2 m + r-1 + ··· +2 m + 1 + (! a m +1) 2 m + a m-1 2 _{^{m-1 + a m-2}} 2 m-2 + ··· + a 0 2 0 ... is (14). From the above equation (14), the addition of the partial products shown in FIG. 13 is equivalent to the addition of the partial products shown in FIG. When the addition shown in FIG. 14 is arranged, the result finally becomes as shown in FIG. 15 (“１５” in FIGS. 14 and 15).
An inverted bit of the sign bit a _m! denote the a _m). In this manner, as shown in FIG. 15, by inverting the most significant bit (sign bit) of the partial product and adding “1” to a predetermined bit position, the addition of the partial product can be performed without sign extension. To get the correct product P.

Now, consider a multiplier that inputs two 16-bit numbers in two's complement notation and calculates their product by the Booth method. Possible values are 2 ¹⁶ combinations of multiplicand X of the multiplier, a value less 2 ¹⁶ combinations can take the multiplier Y, therefore, the combination of inputs to the multiplier is present are two ^32. That is, there are 2 ³² types of multiplications performed by this multiplier. However, for the multiplication of “8000h × 8000h”, a correct product cannot be obtained by the above-mentioned booth method. That is, according to the Booth method described above, the multiplication of the 16-bit number (two's complement notation) is performed by adding partial products as shown in FIG.
A 31-bit multiplication result (product) P30 to P0 is obtained,
As for the multiplication “8000h × 8000h”, as shown in FIG. 17, the operation result is “40000000h”. Now, Figure 1
Assuming that the position of the decimal point is on the right of the sign bit as shown in FIG. 8, “8000h” indicates “−1” and “40000000”
0h ”also indicates“ −1 ”. As a result, FIG. 17 shows“ (−1) ”.
× (-1) = (-1) ", which means that an incorrect multiplication result was obtained. Thus, "8000h x 8000
The incorrect result for the multiplication "h" is obtained even if the decimal point is chosen elsewhere. Below,
Such multiplication for which a correct multiplication result cannot be obtained is referred to as “singular calculation”.

Conventionally, there has been a multiplication apparatus having means for correcting the multiplication result in the case of such a singular calculation. FIG. 19 is a circuit diagram showing an example of a multiplication device having such a correction means (hereinafter, referred to as “conventional example 1”). In this example, a singularity calculation detector 7 is provided to detect a singularity calculation of “8000h × 8000h”, and a detection signal DETB output from the singularity calculation detector 7 is used to detect a singularity calculation by a circuit including an AND gate, a NAND gate, and an inverter. multiplication result output from the bit of the multiplier 6 P ₃₀ ~P ₀ (multiplicand x ₁₅ ~
x ₀ and the multipliers y _{15 to} y ₀ ). And
The multiplication result PM ₃₀ Pm ₀ after the correction is set to the multiplication result of the multiplier of FIG. 19 (Note that when the specific calculation is not detected, P ₃₀ to P ₀ is equal to PM ₃₀ ~PM _0).

According to the above configuration, the multiplicand X and the multiplier Y
Is "8000h", the output of the singular calculation detector 7 is DETB = 0. Thus, the sign bit P ₃₀ of the multiplication result output from the multiplier 6 is "0", all bits P ₂₉ to P ₀ of the numerical part becomes "1", as a result of multiplication PM ₃₀ Pm ₀ after the correction "3FFFFFFFh" is obtained. When the position of the decimal point is immediately to the right of the sign bit as shown in FIG. 18, in a digital signal processor (DSP) or the like using the multiplier of this example, the multiplication result is 32 bits.
In order to match the bits, the corrected multiplication result is shifted leftward (upper direction) by one bit. Thereby, “7FFFFFFFh” is obtained as the final multiplication result.

FIG. 20 is a circuit diagram showing another example of a multiplication device having means for correcting a multiplication result in the case of a singular calculation (hereinafter referred to as "conventional example 2"). In this example,
As in the first conventional example, a singular calculation detector 7 is provided to detect a singular calculation “8000h × 8000h”, and a multiplication obtained by a 16-bit multiplier 6 is performed by using a detection signal DETB output from this circuit. Correct the result. However, in this example, the multiplication results P _{30 to} P ₀ output from the multiplier 6
Example 1 in which is directly corrected using the detection signal DETB
Unlike, by modifying the least significant bit x ₀ of the multiplicand X by the circuit consisting of NAND gates and inverters using the detection signal DETB, corrects the multiplication result output from the multiplier 6.

According to the above configuration, the multiplicand X and the multiplier Y
There when both of "8000h", the output of a specific calculation detector 7 DETB = 0, and the least significant x ₀ bits of multiplicand X to be input to the multiplier 6 is modified to "1". This allows
In the case of the singular calculation of “8000h × 8000h”, the multiplier 6 performs the multiplication of “8001h × 8000h”, and the multiplication result P ₃₀
Value "3FFF8000h" is output as ~P _0. FIG.
2 indicates the multiplication process at this time. Here, FIG.
When the position of the decimal point is immediately to the right of the sign bit as shown in (2), in a DSP or the like using the multiplier of this example, the "3FFF8000h"
Is shifted leftward by one bit.
As a result, “7FFF0000h (=
+ 0.9999695 ≒ + 1) "is obtained. That is, when the position of the decimal point is set as shown in FIG.
As a result of the singular calculation “8000h × 8000h” meaning “× (−1)”, “7FF” meaning “+0.9999695 (≒ + 1)”
F0000h ”will be obtained.

[0016]

The above-mentioned prior art 1 (FIG. 1)
In 9), in order to correct the multiplication result in the case of the singular calculation, each bit P indicating the multiplication result output from the multiplier 6 is set.
Every ₃₀ to P _0, and requires correction circuit comprising a NAND gate or an AND gate or an inverter, because it is also necessary wiring area for these connections, there is a problem that the circuit scale becomes large.

On the other hand, according to Conventional Example 2 (FIG. 20), the configuration of the correction circuit in the case of singular calculation is simple, and the circuit scale does not increase. In Conventional Example 2, if the position of the decimal point is set to the right of the sign bit (see FIG. 18), in the case of singular calculation, “(−1) × (−1)”
As a result of multiplication, “+0.9999695 (≒ + 1)” is obtained. Therefore, the error in this case is e = 3.05 × 10 ⁻⁵ , and the multiplication result has an effective precision of about 4 digits in decimal. DSP using such a multiplication device is 16
In many cases, bits are used as the basic word length, and the frequency of performing singular calculations is extremely low. Therefore, it is considered that this effective precision is sufficient.

However, in the DSP, in order to execute a product-sum operation frequently used in signal processing at a high speed, for example, as shown in FIG. 23, a product of data sequentially read from the data RAM 8 and a coefficient sequentially read from the data RAM 9 is used. Is obtained by a multiplier 6 and the product is cumulatively added by a circuit comprising an adder 10 and a register 11, and the adder 10 in this configuration has a relatively large number of bits of, for example, 40 bits. Can be calculated by The multiplication result (product) output from the multiplier 6 is also 3
It is one bit. Furthermore, in applications such as audio products, the accuracy of 16 bits per data is insufficient, and DSPs of 24 bits per data are predominant. In this case, the arithmetic precision of about 6 decimal digits is required. Become.

Also, the singular calculation should be checked and corrected by software by a program creator such as a DSP. In the case of a singular calculation, it is worthwhile even if the correction as in the conventional example 2 is performed. There is an idea that there is. However, in the configuration of the conventional example 2, a result is obtained with a predetermined accuracy even for a singular calculation.
There is a possibility that a problem (insufficient accuracy) caused by the result of the singular calculation may not be noticed.

Further, when performing an address operation, it is necessary to perform the multiplication strictly, and the accuracy in the second conventional example is insufficient. For example, in the case of a so-called table look-up method in which an address is generated by an operation value and a corresponding value is read from a table stored in advance in a program RAM, the operation value becomes the address of the program RAM as it is. With such a rounding operation, there is a possibility that correct data cannot be read.

As described above, Conventional Example 2 has the advantage that the configuration of the correction circuit is simple, but the accuracy of the multiplication result obtained by correction in the case of singular calculation is not sufficient.

Therefore, an object of the present invention is to provide a multiplication device which can correct a multiplication result with a simple configuration in a case of a singular calculation and can obtain a highly accurate multiplication result by the correction. .

[0023]

In order to solve the above-mentioned problems, a first multiplier according to the present invention is a multiplier which multiplies a signed binary number by a Booth's method to calculate a product. A booth decoder that inputs a value of a plurality of bits that are a part of a bit sequence forming a multiplier and outputs an operation signal that specifies an operation on the multiplicand; and performs an operation specified by the operation signal on the multiplicand. And a partial product generating means for generating a partial product according to the following formula: and a partial product output from the partial product generating means by inputting a value of each of a plurality of bits, which are each part of a bit string constituting a multiplier, to a Booth decoder. And a partial product adding means for obtaining a multiplication result, and detecting a singular calculation in which a correct product cannot be obtained as the multiplication result based on the multiplier and the multiplicand. In a multiplication apparatus including a singular calculation detection unit and a correction unit that corrects the multiplication result when it is detected that the case is a singular calculation, the correction unit uses the Booth decoder to correct the multiplication result. And a booth decoder output correction means for correcting the value of the operation signal output from the control unit.

In the second multiplying device according to the present invention, in the first multiplying device, the Booth decoder output correcting means may correct the multiplication result by using the Booth decoder in the lowest order of the multiplier. The method is characterized in that a value of the operation signal output for a plurality of bits is corrected to a value that specifies obtaining a complement of the multiplicand.

In a third multiplication device according to the present invention, in the first or second multiplication device, the correction means further includes a multiplicand correction means for correcting the multiplicand to correct the multiplication result. It is characterized by:

The fourth multiplying device according to the present invention comprises the third multiplying device.
Wherein the multiplicand correcting means corrects the least significant bit of the multiplicand to “1” in order to correct the multiplication result.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a 16-bit multiplication device,
The ideal multiplication result (31-bit product) output for the singular calculation is “7FFFFFFFh”. Conventional example 2 already described
Replaces the multipliers and multiplicands in the case of singular calculations with values that are close to them, so that the ideal value "7FFFFF
FFh ”. However, the result of multiplication in the case of singular calculation obtained by this method is
It cannot be the ideal value "7FFFFFFFh", but it is necessarily an approximate value.

On the other hand, in the case of the singular calculation, the lower 15 bits of the multiplication result "3FFF8000h" (the value before shifting to match 32 bits) obtained by the conventional example 2 are forcibly set to "1". It is possible. FIG.
An example of a multiplication device configured based on such a concept is shown. In this example, the lower 1 of the output of the conventional example 2 (FIG. 20) is used.
A circuit including a NAND gate and an inverter is added to each of the five bits P _{14 to} P ₀ , whereby
In the case of the singular calculation, the lower 15 bits of the 31-bit outputs P _{30 to} P ₀ from the multiplier 6 using the detection signal DETB (= 0).
The bit is set to “1”. According to this configuration, "3FFFFF
FFh ”is obtained, and the position of the decimal point is immediately to the right of the sign bit (see FIG. 18).
In the SP or the like, the corrected multiplication result “3FFFFFFFh” is shifted leftward by one bit in order to match the multiplication result to 32 bits. As a result, “7FFFFFFFh” is obtained as a final multiplication result.

As described above, according to the configuration shown in FIG. 21, an ideal multiplication result of "7FFFFFFFh" can be obtained in the case of the singular calculation. However, in this configuration, the conventional example 2
In addition to the circuit of FIG. 20, NAN is applied to each of the lower 15 bits of the 31 bits forming the multiplication result.
A correction circuit including a D gate and an inverter is required, and the circuit scale becomes large.

Therefore, in the present embodiment, in the case of the singular calculation, instead of directly correcting the multiplication result output from the multiplier 6, the output of the Booth decoder, that is, the operation signal for the multiplicand is corrected. The concept of correcting the output multiplication result to obtain a multiplication result as close as possible to the ideal value “7FFFFFFFh” is introduced. Hereinafter, details of such an embodiment will be described.

<Structure of Embodiment> FIG. 1A is a block diagram showing the overall structure of a multiplier according to an embodiment of the present invention. This multiplier consists of the multiplicand X (x _k ~x 2 binary two's complement of _zero) and the multiplier Y (y _n ~y ₀ 2
And a product P (a binary number represented by two's complement consisting of P _{k + n-1 to} P ₀ ) with a binary number represented by a complement of the second order, based on a secondary Booth's method. 20, in addition to the singularity calculation detector 7 for detecting the singularity calculation, the NAND gate 102 and the inverter 101 for correcting the value of the multiplicand X in the case of the singularity calculation as in the conventional example 2 shown in FIG. And a multiplicand correction circuit.

The configuration of the multiplier 6 in the present multiplier is shown in FIG.
This is as shown in FIG. The multiplier 6 generates an operation signal C for generating each partial product based on the second-order Booth method.
Booth decoders 1 and 2 that create X, C2X, Ccomp,
It comprises a partial product generating unit 3 for generating each partial product by performing an operation specified by the operation signals CX, C2X, and Ccomp on the multiplicand X, and a partial product adding unit 4 for adding each partial product. Have been. Here, each partial product based on the second-order Booth's method is represented by Expression (3) and is as follows. (Y _2j-1 + y _2j -2y _{2j + 1} ) 2 ^2j · X (j = 0,1,2, ...,
(n-1) / 2, where n is an odd number)

Of the Booth decoders in the multiplier 6 having the above structure, the partial product (y _-1 + y ₀ -2y ₁ ) 2 ^2j · X = (y ₀ -2y ₁ ) 2 ^2j · X corresponding to j = 0 is calculated. 1 (booth decoders of the first stage) booth decoder for creating an operation signal for generating to the formula (8) to (10), that CX = y ₀ C2X =! (Y ₀ +! Y ₁ ) Performs the logical operation represented by Ccomp = y ₁ and can be realized by the circuit shown in FIG. However, in this embodiment,
A singular calculation detector 7 is provided. In the case of singular calculation, the booth decoder 1 of the first stage uses the detection signal DETB output from the singular calculation detector 7 to correct the multiplication result.
The operation signals CX, C2X, and Ccomp output from are modified. That is, in the present embodiment, the configuration shown in FIG. 2 is employed instead of the configuration shown in FIG. 3 as the configuration of the booth decoder 1 in the first stage, and in the case of singular calculation (when the detection signal DETB = 0). In the operation signals, CX and Ccomp are as follows. CX = 1, Ccomp = 1 ... (15)

The booth decoders of the second and subsequent stages, that is, j = 1,
The booth decoder 2 corresponding to the partial product (y _2j-1 + y _2j -2y _{2j + 1} ) 2 ^2j · X in the case of 2,..., (N−1) / 2 has the following formulas (5) to (7). CX = y _i-1 (+) y _i C2X =! ｛(Y _i-1 (+) y _i ) +! (Y _i (+)
y _{i + 1} )｝ Performs the logical operation represented by Ccomp = y _{i + 1} and can be realized by the circuit shown in FIG. Here, i = 2j.

The partial product generating section 3 calculates each partial product (y _2j-1 + y _2j -2y _{2j + 1} ) 2 ^2j × X (j = 0,1,2,...,
(n-1) / 2, where n is an odd number), and one portion is provided for each partial product. Corresponds to 1. Each partial product generation unit 3
As shown in FIG. 5, bits PP _m to PP
The configuration is such that the partial product bit generation circuits 5 for generating PP ₀ are provided by the number of bits of each partial product, and the operation signals CX, C2X, Cc supplied from the corresponding booth decoders 1 and 2 are provided.
The operation specified by omp is performed on the multiplicand X.
Here, the operation signal CX indicates whether or not to output the multiplicand X as it is. Further, the operation signal C2X indicates whether to double the multiplicand X. In the present embodiment, when C2X = 1, the multiplicand X is doubled by shifting the multiplicand X leftward by one bit. The operation signal Ccomp indicates whether to reverse the sign of the multiplicand X, that is, whether to obtain a two's complement. The two's complement of the multiplicand X is obtained by inverting each bit of X and adding “1” to the least significant bit. However, when the addition operation of this “1” is performed by the partial product generation unit 3, the hardware amount Will be increased. Therefore, in the present embodiment, when the operation signal Ccomp = 1, each partial product generation unit 3
Inverts each bit of the multiplicand X, and the partial product adder 4 performs an addition operation of “1”, thereby obtaining a two's complement of the multiplicand X.

FIG. 7 is a truth table showing the operation of the partial product generation unit 3 for generating a partial product using the operation signals CX, C2X, and Ccomp designating the above operations. “PP _i ” in the table represents an output of each partial product bit generation circuit 5 constituting the partial product generation unit 3. The partial product bit generation circuit 5 that performs the operation indicated by the truth table can be realized by the circuit shown in FIG.

The partial product adder 4 adds the partial products generated by the respective partial product generators 3 to form a product P of the multiplicand X and the multiplier Y from bits P _{k + n−1 to} P _0. Generated as a two's complement binary number. At this time, if the addition is performed without sign extension for the lower partial product, a correct product P cannot be obtained, but the sign extension increases the amount of hardware. Therefore, the partial product adder 4 inverts the most significant bit (sign bit) of the partial product as described above,
By adding “1” to a predetermined bit position (FIG. 15)
), And correct product P is obtained by performing addition of partial products without sign extension.

<Operation of Embodiment> The operation of the multiplication device of this embodiment will be described below. In this multiplier, first, the equation
Booth decoders 1 and 2 corresponding to the respective partial products indicated by (3) use a plurality of bits y _2j−1 , y _2j and y _{2j + 1} corresponding to the partial products in the bit string forming the multiplier Y. Operation signals CX, C2X, and Ccomp are generated. These operation signals CX, C2X,
Ccomp is input to the corresponding partial product generation unit 3, and each of the partial product generation circuits 3 receives the input operation signals CX, C2X, and Ccom.
The operation specified by p is performed on the multiplicand X. In this way, the respective partial product generation circuits 3 operate in parallel, whereby the respective partial products represented by Expression (3) are independently generated. Each of the generated partial products is added in the partial product adder 4, whereby a product P of the multiplicand X and the multiplier Y is obtained. According to the multiplication apparatus based on the secondary Booth's method, the number of partial products added by the partial product adding unit 4 is about half as compared with the method of generating a partial product with the multiplicand for each bit of the multiplier. (See equation (2)), so that the multiplication can be executed at high speed.

Next, the operation of the present multiplication apparatus when the combination of the multiplicand X and the multiplier Y is a singular calculation will be described. In this case, a singular calculation is detected by the singular calculation detection unit 7 from the multiplicand X and the multiplier Y, and the detection signal DETB is set to “0”.
Is output. By this detection signal DETB, the multiplicand X
Of the least significant bit x ₀ of the multiplier 6
(See FIG. 1A). The other bits x _{k to} x ₁ of the multiplicand X and the multiplier Y are directly input to the multiplier 6.

The detection signal DETB is input to the booth decoder 1 at the first stage, and is also used for correcting the output of the booth encoder 1. That is, the detection signal DET
The B (= 0), the operation signal CX outputted from Booth decoder 1 of the first stage, Ccomp is, CX = 1, Ccomp = 1 ... (15) , whereas for specific computation y ₀ = y ₁ = ₀ Therefore, the operation signal C2x becomes C2X = 0 (see FIG. 2). Here, assuming that the output of the booth decoder 1 is expressed using the notation of “state” shown in FIG. 7, the output of the booth decoder 1 in the first stage is “−X” (hereinafter, this notation is used). Represents the output of the Booth decoder). Booth decoder 2 in the second and subsequent stages
Is the same as in the case of non-singular calculation, the output of the booth decoder 2 other than the last stage is “0”, and the output of the last stage booth decoder 2 is “−2X”.
Becomes

Based on the outputs of the booth decoders 1 and 2 as described above, each partial product is generated using the corrected multiplicand X (see FIG. 1) of the least significant bit x ₀ , and the generated partial products are By the addition performed by the partial product adder 4, a highly accurate multiplication result can be obtained even in the case of singular calculation.

For example, if the multiplicand X and the multiplier Y are 16 bits, in the case of the singular calculation, the multiplicand X and the multiplier Y are both "8000h", and the least significant bit of the multiplicand X is corrected to "1" and X = 8001h Is input to the multiplier 6 as it is. Then, using these input values, the output “−−” of the booth decoder 1 in the first stage is used.
X ", the partial product corresponding to the output" 0 "of the second to seventh stages of the booth decoder 2, and the output" -2X "of the final stage, the eighth stage booth decoder 2. Corresponding partial products are respectively generated and the partial products are added. At this time, in order to avoid sign extension of the lower partial product, the most significant bit (sign bit) of the partial product is inverted, and “1” is added to a predetermined bit position (FIG. 15,
See FIG. 16). As a result, the addition of the partial products is as shown in FIG. 8, and the multiplication result (31-bit product P) is “3FFF
FFFFh "is obtained. Here, as shown in FIG. 18, when the position of the decimal point is immediately to the right of the sign bit, in a DSP or the like using the present multiplication device, the multiplication result "3FFFFFFFh" Shift left by one bit. At this time, “0” is input to the least significant bit, and “7FFFFF” is output as the final multiplication result.
FEh (= + 0.9999 ...) "is obtained. This is "(-
In the singular calculation of “1) × (−1)”, it means that an arithmetic precision of about 9 digits in a decimal number is obtained.

Since the ideal multiplication result in the above singular calculation is “7FFFFFFFh”, the least significant bit “0” must be set to make the multiplication result “7FFFFFFEh” obtained by the above configuration ideal. It needs to be modified to "1". For this purpose, when shifting the product P output from the multiplier 6 to the left by one bit, if a singular calculation is detected, “1” is input to the least significant bit instead of “0”. May be adopted. Such a configuration can be realized with a simple circuit.

<Effects of the Embodiment> In the above embodiment, the hardware used for correcting the multiplication result in the case of the singular calculation includes the singular calculation detector 7 and the multiplicand correcting circuit (correcting the least significant bit of the multiplicand X). Inverter 101, NA
ND gate 102) and first stage booth decoder 1
(See FIG. 2), which performs the multiplication as shown in FIG. 8 in the case of singular calculation. Therefore, according to the above-described embodiment, a highly accurate multiplication result can be obtained even with a singular calculation by adding a small amount of hardware.

In the above description, 16 bits × 16
Although multiplication of bits is taken as an example, at present 32 bits × 3
Two-bit multiplication has become unusual. When the number of calculation bits increases in this manner, the amount of hardware for correction increases in the conventional example 1 (FIG. 19) and the like, but such an increase is not seen in the above embodiment, and the number of calculation bits increases. Accordingly, the above embodiment becomes more advantageous.

<Modification> In the above embodiment, the Booth decoder whose output is corrected in the case of the singular calculation is only the first stage. However, the present invention is not limited to this. The output of the booth decoder in another stage may be modified so that an ideal multiplication result or a multiplication result close thereto is obtained (there may be a plurality of booth encoders to be modified).

In the above embodiment, a plurality of booth decoders and partial product generators are provided, and each partial product is generated in parallel. However, a configuration in which partial products based on the Booth method are sequentially generated. Is also conceivable. Even in such a sequential multiplication device, the multiplication result can be corrected by correcting the output of the Booth decoder in the case of the singular calculation in the same manner as in the above embodiment, and the same effect as in the above embodiment can be obtained. Is obtained.

[0048]

According to the present invention, in the case of singular calculation, unlike the conventional multiplication device in which correction is performed for each bit of the multiplication result, the operation signal output from the Booth decoder is modified. Since the multiplication result is corrected,
The correction means can be realized with a small amount of hardware (see the first multiplier). At this time, by appropriately selecting the booth decoder for correcting the operation signal and the correction content of the operation signal, for example, the value of the operation signal of the first-stage booth decoder is corrected to a value that specifies the complement of the multiplicand. Thereby, the accuracy of the corrected multiplication result in the case of the singular calculation can be improved (see the second multiplication device). Further, when the multiplicand correcting means is further provided, the degree of freedom of correcting the multiplication result in the case of the singular calculation is increased by adding a small amount of hardware, whereby a highly accurate multiplication result can be easily obtained (third multiplication). Device). For example, in the case of the singular calculation, the value of the operation signal of the first-stage Booth decoder is corrected to a value that determines the complement of the multiplicand, and the least significant bit of the multiplicand is corrected to “1” by the multiplicand correcting unit. Then, since the lower bits of the multiplication result become “1”, an ideal multiplication result or a multiplication result close to the ideal multiplication result is obtained (see the fourth multiplication device).

As described above, in the address operation, the multiplication must be strictly performed. For example, in the case of the table lookup system in which the operation value is the address of the program RAM as it is, the conventional rounding of the multiplication result of the singular calculation is performed. In some cases, correct data could not be read depending on the correction that involved the operation. However, if the present invention is applied to such an address operation, a highly accurate multiplication result can be obtained even in the case of a singular calculation. Therefore, such a problem is solved, and correct data can always be read by the address which is the operation result. Become like

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiplication device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a first-stage Booth decoder in the multiplication device of the embodiment.

FIG. 3 is a circuit diagram showing a configuration of a first-stage booth decoder in a conventional multiplication device.

FIG. 4 is a circuit diagram showing a configuration of a booth decoder of the second and subsequent stages in the multiplication device of the embodiment.

FIG. 5 is a block diagram showing a configuration of a partial product generation unit in the multiplication device of the embodiment.

FIG. 6 is a circuit diagram showing a configuration of a partial product bit generation circuit in a partial product generation unit.

FIG. 7 is a diagram showing a truth table showing an operation of the partial product generation unit.

FIG. 8 is a diagram showing a multiplication process in the case of a singular calculation in the multiplication device of the embodiment.

FIG. 9 is a diagram showing a multiplication process by a conventional general multiplication method.

FIG. 10 is a diagram showing a multiplication process by a secondary booth method.

FIG. 11 is a diagram showing a truth table defining the output of the Booth decoder in the multiplier based on the second-order Booth method.

FIG. 12 is a diagram showing a truth table defining the output of the first-stage Booth decoder in the multiplier based on the secondary Booth method.

FIG. 13 is a diagram illustrating sign extension when adding partial products.

FIG. 14 is a diagram for explaining a method of performing addition of partial products without performing sign extension.

FIG. 15 is a diagram showing a method of performing addition of partial products without sign extension.

FIG. 16 is a diagram showing a method of performing addition of partial products without sign extension in 16-bit multiplication.

FIG. 17 is a diagram showing a multiplication process when no correction is performed in the case of singular calculation.

FIG. 18 is a view showing a setting of a decimal point position in a 16-bit binary number represented by two's complement.

FIG. 19 is a diagram showing a conventional example (conventional example 1) of a multiplication device having a correction unit.

FIG. 20 is a diagram showing another conventional example (conventional example 2) of a multiplication device having a correction unit.

FIG. 21 is a diagram showing a configuration of a multiplication device obtained by improving the multiplication device of Conventional Example 2.

FIG. 22 is a diagram showing a multiplication process in the multiplication device of the second conventional example.

FIG. 23 is a block diagram showing a configuration for executing a product-sum operation at high speed in a DSP.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Booth decoder (1st stage) 2 ... Booth decoder (2nd stage and after) 3 ... Partial product generation part 4 ... Partial product addition part 6 ... Multiplier 7 ... Singular calculation detection part X ... Multiplicand Y ... Multiplier P ... Product DETB…
Detection signal CX, C2X, Ccomp ... Operation signal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-287220 (JP, A) JP-A-7-93134 (JP, A) JP-A 8-234965 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 7/52 G06F 7/38

Claims (4)

(57) [Claims] 1. A multiplication apparatus for multiplying a signed binary number by a Booth's method to calculate a product, wherein a multi-bit value which is a part of a bit sequence forming a multiplier is input to define an operation on a multiplicand. A booth decoder that outputs an operation signal to perform the operation, a partial product generation unit that generates a partial product by performing an operation defined by the operation signal on the multiplicand, and a plurality of bits each of which is a part of a bit string that forms the multiplier. Is input to the Booth decoder to accumulate the partial products output from the partial product generation means to obtain a multiplication result, and a singular calculation for which a correct product is not obtained as the multiplication result. A singular calculation detecting means for detecting the case based on the multiplier and the multiplicand; and correcting the multiplication result when the singular calculation is detected. A multiplication device comprising a correction means, wherein the correction means has a Booth decoder output correction means for correcting the value of the operation signal output from the Booth decoder in order to correct the multiplication result. Multiplication device. 2. The multiplication apparatus according to claim 1, wherein the Booth decoder output correction means outputs the plurality of least significant bits of the multiplier by the Booth decoder in order to correct the multiplication result. Multiplying the value of the operation signal to a value that specifies obtaining a complement of the multiplicand. 3. The multiplication device according to claim 1, wherein said correction means further includes a multiplicand correction means for correcting said multiplicand in order to correct said multiplication result. apparatus. 4. The multiplication device according to claim 3, wherein the multiplicand correcting means corrects the least significant bit of the multiplicand to “1” in order to correct the multiplication result. .