JP2914813B2 - Error correction decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoding device for correcting and decoding errors in received information in a digital recording device or digital communication device.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional error correction decoding apparatus shown in a paper "High-speed operation circuit of Euclidean mutual division method" published in, for example, "Electronic Information and Communication Society Autumn National Convention 1988" A-60. FIG. 2 is a block diagram showing a basic operation circuit of the Euclidean algorithm operation device, in which 101 and 102 are storage devices for storing data;
Reference numeral 104 denotes a flag storage device that stores flags of the contents stored in the storage devices 101 and 102, respectively.
108 is a selector circuit, 109 and 110 are multiplication circuits on the Galois field, and 111 is an addition circuit on the Galois field.

FIG. 8 is a block diagram showing a conventional Euclidean algorithm operation device.
Are the basic operation circuits shown in FIG.
Is an arithmetic processing circuit unit having basic arithmetic circuits 112 to 119, 121 is a control circuit, 122 is a state flag storage device,
123 is an end determination circuit. Note that the basic operation circuit 11
2 to 119 are connected between the storage devices 101 and 102 and the flag storage devices 103 and 104 in FIG. The number of stages in which the basic operation circuits are arranged in parallel is 2t in the case of a t-symbol error correction code.

Next, the principle of the Euclidean algorithm will be described. Hereinafter, a case of an error correction code of t symbols will be described. Let the syndrome polynomial be S (x). A (x) = x ^2t , B (x) = S as initial values
(X), L (x) = 0 and M (x) = 1. Also, the highest order coefficients of the polynomials A (x) and B (x) are β,
Let it be α . When the degree (degA) of the polynomial A (x) is equal to or greater than the degree (degB) of the polynomial B (x)

[0005]

(Equation 1)

## EQU1 ## and the order of the polynomial A (x) (d
egA) is smaller than the degree (degB) of the polynomial B (x)

[0007]

(Equation 2)

## EQU1 ## and the polynomial A (x) or B
This calculation is repeated until the order of (x) becomes less than t. At this time, among the polynomials A (x) and B (x), the polynomial whose degree is less than t is an error numerical polynomial, and de
When g (A (x)) <t, L (x) and deg (B
When (x)) <t, M (x) is an error locator polynomial.

Next, the operation of the Euclidean algorithm will be described. First, for the basic arithmetic circuits 112 to 119 in the arithmetic processing circuit unit 120 in FIG. 8, the storage device 101 in FIG. 7 stores the coefficients of the polynomials A (x) and M (x) in the order of the degree. 102 has a polynomial B
The coefficients of (x) and L (x) are stored in order of order. In addition, the flag storage device 103 stores the corresponding storage device 101.
Holds “1” when the content of the polynomial A (x) stores the coefficient of the polynomial A (x), and holds “0” when the content of the polynomial M (x) stores the coefficient of the polynomial A (x). The flag storage device 104 holds “0” when the content of the corresponding storage device 102 stores the coefficient of the polynomial B (x), and the polynomial L (x)
When the coefficient is stored, "1" is held.

When the content of the flag storage device 103 is “1”, the multiplication circuit 109 receives the output of α from the selector circuit 105, multiplies that α by the content of the storage device 101, and outputs the result. When the content of the flag storage device 103 is “0”, the multiplication circuit 109 receives the output of β from the selector circuit 105 and stores the β in the storage device 101.
And output the result. On the other hand, when the content of the flag storage device 104 is “1”, the multiplication circuit 110 inputs the output of β from the selector circuit 105, multiplies that β by the content of the storage device 102, and outputs the result. When the content of the flag storage device 104 is “0”, the multiplication circuit 11
0 inputs the value that has been output by the selector circuit 105,
The α is multiplied by the contents of the storage device 102.

Next, in the selector circuits 106 and 107, when the contents of the corresponding flag storage devices 103 and 104 match, the addition processing is not performed in the addition circuit 111 and the outputs of the multiplication circuits 109 and 110 are stored in the storage device 10 respectively.
1, 102 is input. On the other hand, when the contents of the corresponding flag storage devices 103 and 104 do not match, the addition circuit 1
At 11, the sum of the multiplication circuits 109 and 110 is calculated, and “1” is calculated based on the value held in the state flag storage device 122.
Is held (degA ≧ degB), the output of the adder circuit 111 is input to the storage device 101. When “0” is held (degA <degB), the output of the adder circuit 111 is input to the storage device 102. I do.

The polynomial A of the storage devices 101 and 102
“0” where the highest order coefficient of (x) is stored
Is stored, the contents of the storage device 101 and the flag storage device 103 are shifted. If “0” is stored where the highest order coefficient of B (x) is stored, the contents of the storage device 102 and the flag storage device 104 are shifted.

The condition for terminating the operation is a flag storage device 103,
104, the polynomial A (x) or the polynomial B
When the degree of (x) becomes less than t, the end determination circuit 12
3, the Euclidean algorithm operation is terminated. The control in the above operation is performed by the control circuit 121.

[0014]

Since the conventional error correction decoding apparatus is constructed as described above, each of a plurality of basic operation circuits is separately operated in one operation according to the contents of the state flag storage device. Have to work,
Therefore, there is a problem that control of the basic arithmetic circuit and the like becomes complicated, and it is difficult to improve the speed of the decoding process. In addition, since a component for performing erasure error correction for correcting an error of lost data in a received word, for example, a storage device for storing an erasure position is not provided, such erasure error correction cannot be performed. However, there is a problem that the error correction capability is reduced as a whole. Therefore, erasure error correction can be realized by adding a component for performing erasure error correction. However, since the control of the basic arithmetic circuit and the like is complicated as described above, high-speed erasure error correction is performed. There is a problem that a special processing cannot be expected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. By making each of a plurality of basic arithmetic circuits perform the same operation in one arithmetic operation, the basic arithmetic circuit and the like are provided. It is an object of the present invention to provide an error correction decoding device which facilitates control of the decoding process to improve the speed of decoding processing, enables erasure error correction, and can execute error correction processing at high speed.

[0016]

An error correction decoding apparatus according to the present invention comprises a received word storage means (received word storage device 24) for storing a received word, and a syndrome calculation means (syndrome) for calculating the syndrome of the received word. Computing device 25)
And a plurality of basic arithmetic circuits 1a to 1h each comprising one Galois field multiplication means for generating an error locator polynomial and an error numerical polynomial based on the syndrome.
An Euclidean algorithm operation means (Euclidean algorithm operation device 26) having one and a Galois field division means; a Chien search means (Chen search circuit 27) for obtaining an error position of the received word from a coefficient of the error locator polynomial; An error value calculating means (error value calculating circuit 28) for calculating an error value from the error locator polynomial and the error value polynomial, and an error in the received word is corrected based on the error value and stored in the received word storage means. An error correction means (error correction device 29), and a Galois field multiplication means in the Euclidean algorithm operation means so that the operation of the error locator polynomial and the error numerical polynomial on the Galois field in the Euclidean algorithm can be performed for each polynomial unit. A plurality of basic arithmetic circuits 1a to 1h composed of one are connected in parallel. Arrangement, and the dividing means of said Galois field
The coefficients of the divisor polynomial and Hijo polynomial whenever the polynomial division by those configured to directly output to the multiplication unit of the Galois field of the basic operation circuit.

The error correction decoding apparatus according to the present invention further comprises an erasure position storage means (erasure position storage device 33) for storing an erasure position which is the position of the erasure data in the received word, and stores the erasure position in the Euclidean algorithm. The configuration is such that erasure error correction and normal error correction are performed in parallel by inputting to an arithmetic means.

[0018]

Since a plurality of basic arithmetic circuits 1a to 1h are arranged in parallel, it is possible to perform the operation of the error locator polynomial and the error numerical polynomial without using a flag for each polynomial unit .
The control of the basic arithmetic circuits 1a to 1h can be made the same.

The lost position is stored in a lost position storage means,
The Euclidean algorithm operation means performs erasure error correction based on the erasure position, and also performs normal error correction in parallel.

[0020]

[Embodiment 1] FIG. 1 is a block diagram showing a configuration of a Euclidean algorithm operation device as Euclidean algorithm operation means in an error correction decoding device according to one embodiment of the present invention. In FIG. 1, 1a to 1h
Is a plurality of basic arithmetic circuits arranged in parallel so that operations such as an error locator polynomial on a Galois field and an error numerical polynomial in the Euclidean algorithm can be performed for each polynomial unit; 2 is a division circuit for dividing the coefficients of the polynomial; Is an order calculation circuit for calculating the order of the divisor polynomial, 4 is an order calculation circuit for calculating the order of the dividend polynomial, and 5 is the processing of the Euclidean algorithm operation device based on the order of the divisor polynomial calculated by the order calculation circuit 3. An end determination circuit for determining whether or not to perform the operation; 6 a subtraction circuit for calculating the difference between the order from the order calculation circuit 3 and the order from the order calculation circuit 4; 7 a control circuit for controlling the operation of the Euclidean algorithm; 8
Is the input terminal of the Euclidean algorithm operation device, 9
Is an output terminal of the Euclidean algorithm operation device.

FIG. 2 is a block diagram showing the configuration of the basic operation circuit in the Euclidean algorithm operation device of FIG. In FIG. 2, reference numerals 10 to 14 denote coefficient storage devices for storing polynomial coefficients for performing a polynomial operation, 15 denotes a multiplication circuit on a Galois field, 16 and 17 denote addition circuits on a Galois field, and 18 to 23 denote inputs. Is a selector circuit for selecting one of the two.

FIG. 3 is a block diagram showing the configuration of an error correction decoding apparatus according to one embodiment of the present invention. In FIG. 3, reference numeral 24 denotes a received word storage device serving as a received word storage unit for storing a received word, 25 denotes a syndrome calculation device serving as a syndrome calculation unit for calculating a syndrome of the received word,
Reference numeral 26 denotes a Euclidean algorithm operation device as Euclidean algorithm operation means having a plurality of basic operation circuits 1a to 1h (see FIG. 1) for performing operations such as an error locator polynomial and an error numerical polynomial generated based on the syndrome. A Chien search circuit as a Chien search means for obtaining an error position of a received word from a coefficient of the error locator polynomial; 28, an error value calculation circuit as an error value calculation means for calculating an error value from the error position polynomial and the error value polynomial; 29 is an error correction device as an error correction means for correcting an error in the received word based on the error value and storing it in the received word storage device 24; 30 is an address calculation circuit for calculating the address of the received word storage device 24; Input / output terminal of the error correction decoding device.

Next, the operation of this embodiment will be described.
In the following, received words of n symbols (r _n , r _n−1 ,...)
r ₁ ), the generator polynomial is

[0024]

(Equation 3)

The error correction operation when the design distance is 2t + 1 will be described. In FIG. 3, first, a received word is input from the input / output terminal 31 to the received word storage device 24. Next, the received word is read out from the received word storage device 24 to the syndrome calculation device 25, and the syndrome is calculated.

[0026]

(Equation 4)

Is calculated. Syndrome calculation device 25
Is input to the Euclidean algorithm arithmetic unit 26, and an error is obtained by performing a mutual operation between the two polynomials x ^2t and the syndrome polynomial until one of the orders of the two polynomials becomes t or less. The position polynomial σ (x) and the error value polynomial η (x) are calculated.

Next, the coefficients of the error locator polynomial σ (x) calculated by the Euclidean algorithm calculator 26 are input to the Chien search circuit 27, where i = 1, 2,.
A calculation for substituting α- ⁱ for n is performed, and an error position is calculated. On the other hand, the error numerical value calculation circuit 28 has an odd-order and error numerical value polynomial η (x) of the error position polynomial σ (x) calculated by the Euclidean algorithm operation device 26.
Is input, and for i = 1, 2,..., N,
formula

[0029]

(Equation 5)

A calculation is performed by substituting α- ⁱ for the error value. Next, the address of the received word storage device 24 is calculated by the address calculation circuit 30 from the error position calculated by the Chien search circuit 27, and
The symbol of the received word whose error is detected from
9, the error value calculated by the error value calculation circuit 28 is added, and the corrected symbol is written to the received word storage device 24 and output to the input / output terminal 31.

Next, the operation of the Euclidean algorithm operation device will be described in detail with reference to FIGS. The basic operation circuit 1 in FIG. 2 is configured by 2t + 1 stages. Hereinafter, a polynomial having a value stored in the coefficient storage device 10 as a coefficient is R0 (x), and a polynomial having a value stored in the coefficient storage device 11 as a coefficient is A0.
(X), a polynomial using a value stored in the coefficient storage device 12 as a coefficient is R1 (x), a polynomial using a value stored in the coefficient storage device 13 as a coefficient is A1 (x), and the coefficient storage device 14 is used. A polynomial whose coefficient is the value stored in
(X).

First, initial values are set in the coefficient storage devices 10 to 14 provided in the basic operation circuit 1 in FIG. In FIG. 2, the selector circuit 18 inputs the syndrome from the input terminal 8 (FIG. 1) of the Euclidean algorithm operation device to the coefficient storage device 10, and R0 (x) = S (x).
(S (x) is a syndrome polynomial). In the coefficient storage devices 11, 12, 13, and 14, A0 (x) =
1, R1 (x) = x ^2t , A1 (x) = 0, M (x) = 0
The initial values are respectively set to the selector circuits 19 and 2 so that
Select and input with 0, 21, and 23.

The values stored in the coefficient storage devices 10 and 12 of the basic operation circuit 1 are substituted into the degree calculation circuits 3 and 4, respectively, to obtain the degree deg (R0) of the polynomial R0 (x).
And the degree deg (R1) of the polynomial R1 (x) are calculated. The order calculation circuits 3 and 4 are constituted by combinational logic circuits, and the coefficient storage device 1 is used as an input.
If the contents of 0 and 12 are not “0”, enter “1” ,
The order is calculated by weighting and output. For example, FIG.
Is an example of an order calculation circuit capable of determining the order of 7th order or less. The order calculated by the order calculation circuit 3 is input to the end determination circuit 5. In the end determination circuit 5, when the output of the degree calculation circuit 3 is less than t, the Euclidean algorithm operation is ended. On the other hand, when the output of the degree calculation circuit 3 is equal to or larger than t, the operation of the Euclidean algorithm is continued.

Next, the subtraction circuit 6 subtracts the degree difference deg (R) from the degree calculated by the degree calculation circuits 3 and 4.
1) Calculate and set -deg (R0). Division circuit 2
Performs a division D = M (R1) / M (R0) on the Galois field for calculating the highest order coefficients M (R0) and M (R1) of the polynomial R0 (x) and the polynomial R1 (x). .

The order difference P by the subtraction circuit 6 is positive or zero.
In the case of, perform the following operation. The contents of the coefficient storage device 10 are selected by the selector circuit 22 in the basic operation circuit 1, and the selected value is divided by the division circuit 2 input to the basic operation circuit 1.
Is multiplied by the multiplication circuit 15 on the Galois field, and the result of the multiplication is selected by the selector circuit 23 and stored in the coefficient storage device 14. Then, the high-order basic arithmetic circuit 1 is shifted by the number of times of the value calculated by the subtraction circuit 6. Then, the content stored in the coefficient storage device 14 and the content stored in the coefficient storage device 12 are added in the addition circuit 16 on the Galois field, and the result of the addition is selected by the selector circuit 20. 12 is stored.

Selector circuit 22 in basic operation circuit 1
, The content of the coefficient storage device 11 is selected, the value is multiplied by D calculated by the division circuit 2 input to the basic operation circuit 1 in the multiplication circuit 15 on the Galois field, and the result of the multiplication is selected by the selector circuit. 23, the coefficient storage device 1
4 is stored. Then, the high-order basic arithmetic circuit is shifted by the number of times of the value calculated by the subtraction circuit 6. Then, the contents stored in the coefficient storage device 14 and the contents stored in the coefficient storage device 13 are added in the addition circuit 17 on the Galois field, and the result of the addition is selected by the selector circuit 21. 13 is stored. Next, the order of the polynomials R0 (x) and R1 (x) is calculated, the difference between the orders is calculated, and the next operation is determined.

When the order difference P by the subtraction circuit 6 is negative, the following operation is performed. In all the basic arithmetic circuits 1, an operation of exchanging the contents of the coefficient storage devices 10 and 12 and exchanging the contents of the coefficient storage devices 11 and 13 is performed. Next, the polynomials R0 (x), R
The order of 1 (x) is calculated, the difference between the orders is calculated, and the next operation is determined.

As a result of the above operation, when the Euclidean algorithm calculation operation is completed by the completion determination circuit 5, the polynomial R0 (x) having the contents stored in the coefficient storage device 10 as a coefficient becomes an error numerical polynomial, The polynomial A0 (x) having the content stored in the storage device 11 as a coefficient is the error location polynomial. These operations are controlled by a control signal line from the control circuit 7.

Embodiment 2 FIG. Further, in the above embodiment, the case where there is no data loss in the received word has been described. However, even in the case where there is data loss, an error correction decoding device can be configured. FIG. 4 shows a Euclidean algorithm operation device capable of erasure error correction. In FIG. 4, reference numeral 32 denotes a selector circuit, and reference numeral 33 denotes an erasure position storage means for storing an erasure position which is a position of erasure data in a received word. The device 34 is an erasure position address calculation circuit. The same numbers have the same functions and the same configurations as those shown in FIG.

Next, the operation of this embodiment will be described.
Hereinafter, e errors ε erasure error correction codes having a design distance of 2t + 1 will be described. However, here, 2e +
Let ε <2t + 1. When performing the erasure error correction, the erasure position polynomial e (x) and the modified syndrome polynomial S (x) e before performing the Euclidean algorithm operation device.
(X) (modx ^2t ) is generated, and the contents of the register are then calculated according to the polynomial used in the first embodiment as R0 (x) = S
(X) e (x) (mod ^x2t ), R1 (x) = ^x2t ,
The Euclidean algorithm operation must be performed with A0 (x) = e (x) and A1 (x) = 0 as initial values.

Therefore, after the syndrome generation operation is completed, the number of erasures is set in the erasure position address calculation circuit 34,
R0 (x) = S (x), R1 (x) as initial values in the coefficient storage device in the basic arithmetic circuit as in the first embodiment.
= X ^2t , A0 (x) = 1, A1 (x) = 0. Next, when the contents of the erasure position address calculation circuit 34 are not “0”, the contents of the erasure position storage device 33 are output. Further, the output value of the subtraction circuit 6 is set to “1”.

When the output of the subtraction circuit 6 is "1", the selector circuit 32 selects the value output from the erasure position storage device 33 and performs the following operation. Basic operation circuit 1
, The contents of the coefficient storage device 10 are selected by the selector circuit 22, the multiplication circuit 15 on the Galois field multiplies the value input to the basic operation circuit 1, and the result of the multiplication is selected by the selector circuit 23. It is stored in the coefficient storage device 14. Then, the high-order basic operation circuit 1 is caused to perform a shift operation the number of times of the output value of the subtraction circuit 6, that is, only once. Then, the content stored in the coefficient storage device 14 and the content stored in the coefficient storage device 12 are added in the addition circuit 16 on the Galois field, and the result of the addition is selected by the selector circuit 20. 12 is stored.

Selector circuit 22 in basic operation circuit 1
, The content of the coefficient storage device 11 is selected, the multiplication circuit 15 on the Galois field multiplies the value input to the basic operation circuit 1, the result of the multiplication is selected by the selector circuit 23, and the result is stored in the coefficient storage device 14. Remember. Then, the high-order basic arithmetic circuit 1 is shifted by the number of times of the value calculated by the subtraction circuit 6. Then, the content stored in the coefficient storage device 14 and the content stored in the coefficient storage device 13 are added in the addition circuit 17 on the Galois field, and the result of the addition is selected by the selector circuit 21. 13 is stored. Next, the output value of the subtraction circuit 6 is reduced by "1".

When the output of the subtraction circuit 6 is "0", "1" is selected in the selector circuit 32, and the following operation is the same operation as when the output of the subtraction circuit 6 is "1". Do.

When the order difference P by the subtraction circuit 6 is negative, the following operation is performed. In all the basic arithmetic circuits 1, the contents of the coefficient storage devices 12 and 13 are stored in the coefficient storage devices 10 and 11, respectively.
Is operated to store "0". Next, the polynomial R0
(X), the order of R1 (x) is calculated, the output of the subtraction circuit 6 is set to “1”, and the output of the erasure position address calculation circuit 34 is reduced by “1”. The result of performing the above operation until the value of the erasure position address calculation circuit 34 becomes “0” is R
0 (x) = S (x) e (x) and A0 (x) = e (x). Then, by performing the Euclidean algorithm operation described in the first embodiment, the error position polynomial and the error numerical polynomial are calculated. However, the end determination condition of the Euclidean algorithm in this case is deg (R0) <
In the end determination circuit 5, the end determination condition is set to be variable depending on the number of disappearances so that the process is performed until [t + ε / 2] ([a] is the maximum integer not exceeding a).

Embodiment 3 FIG. Further, in the above embodiment, the Euclidean algorithm operation device, the Chien search circuit, and the error value calculation circuit are separated from each other. However, by sharing a storage device, an error correction decoding device that can obtain the same effect can be formed. . FIG. 5 is a block diagram of a basic operation circuit in which the storage device of the Euclidean algorithm operation device and the storage devices of the Chien search circuit and the error value calculation circuit are shared. In FIG. 5, 35 and 36 are constant multiplication circuits on the Galois field. In addition, about the same number, FIG.
It has the same function and the same configuration as those shown in FIG.

Next, the operation will be described. For the Euclidean algorithm calculation operation, the same operation as that described in the first embodiment is performed. In the Chien search operation and the error numerical value calculation operation, the outputs of the selector circuits 18 and 19 are switched so that the coefficient storage device 10 The multiplication result of the constant multiplication circuit 35 is output, the multiplication result of the coefficient storage device 11 and the multiplication result of the constant multiplication circuit 36 are output, and stored in the coefficient storage devices 10 and 11, respectively. A decoding device is configured.

As described above, according to the present embodiment, the operation in the Euclidean algorithm operation device having the basic operation circuits arranged in parallel is performed in units of polynomials, and the erasure position storage device is provided. By inputting the signal to the circuit, high-speed erasure error correction can be performed.

Further, the control of all the basic arithmetic circuits is changed by calculating the difference between the degrees of the two polynomials, and the control of the basic arithmetic circuits in the Euclidean algorithm arithmetic unit is made the same, whereby the control is performed. Becomes easier. That is, the degree calculation circuit for calculating the degree of the polynomial is constituted by a combinational logic circuit, and the control of the operation of the basic operation circuit is changed based on the difference between the degrees of the two polynomials, thereby obtaining the basic operation circuit in one operation. Operation becomes the same operation, and control becomes easy.

Further, a division circuit for performing division by the highest order coefficient of two polynomials and a multiplication circuit for multiplying the result of the division in polynomial units enable high-speed decoding, and furthermore, the erasure position can be determined by the Euclidean algorithm. Erasure error correction becomes possible by inputting to the arithmetic unit.

Further, by sharing the storage means in the Euclidean algorithm operation device, the storage means in the Chien search circuit and the storage means in the error value calculation circuit, the circuit scale can be reduced and high-speed processing can be performed.

[0052]

As described above, according to the present invention, since a plurality of basic arithmetic circuits in the Euclidean algorithm arithmetic means are arranged in parallel, arithmetic can be performed in polynomial units, and a plurality of basic arithmetic circuits can be operated in one arithmetic operation. Can perform the same operation, so that control of the basic arithmetic circuit and the like can be easily performed, and the effect of improving the decoding processing speed can be obtained. Further, in the configuration of the basic arithmetic circuit, the number of Galois field multiplication means is one, and the Galois field division
Each time the division of the polynomial by the arithmetic means is performed, the coefficients of the divisor polynomial and the polynomial to be divided are directly output to the Galois field multiplication means of the basic arithmetic circuit so that the coefficient is not set in the storage means of the basic arithmetic circuit. Therefore, a specific storage unit for setting the coefficient is not required. Therefore, the circuit configuration can be simplified, and the number of operations is one division operation and m times
The multiplication operation enables the control of the basic arithmetic circuit, so that the decoding processing speed can be improved.

Further, according to the present invention, the erasure position storage means is provided, the erasure position is input to the Euclidean algorithm operation means, and the erasure error correction and the normal error correction are performed in parallel. Therefore, the effect that the error correction capability is improved and the error correction process can be executed at high speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a Euclidean algorithm operation device in an error correction decoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a basic operation circuit in the Euclidean algorithm operation device according to one embodiment of the present invention.

FIG. 3 is a block diagram showing an error correction decoding device according to one embodiment of the present invention.

FIG. 4 is a block diagram of a Euclidean algorithm operation device according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a basic operation circuit in a Euclidean algorithm operation device according to another embodiment of the present invention.

FIG. 6 is a block diagram showing an order calculating circuit in the Euclidean algorithm operation device.

FIG. 7 is a block diagram showing a basic operation circuit in a conventional Euclidean algorithm operation device.

FIG. 8 is a block diagram showing a conventional Euclidean algorithm operation device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Basic operation circuit in Euclidean algorithm operation device 2 Division circuit on Galois field 3 to 4 order calculation circuit 5 Termination determination circuit 6 Subtraction circuit 7 Control circuit 8 Input terminal of Euclidean algorithm operation device 9 Output terminal of Euclidean algorithm operation device 10 14 Coefficient storage device 15 Multiplication circuit on Galois field 16-17 Addition circuit on Galois field 18-23 Selector circuit 24 Received word storage device (received word storage means) 25 Syndrome calculation device (syndrome calculation means) 26 Euclidean algorithm calculation device (Euclidean algorithm operation means) 27 Chien search circuit (Chen search means) 28 Error value calculation circuit (Error value calculation means) 29 Error correction device (Error correction means) 30 Address calculation circuit 31 Input / output terminal of error correction decoding device 32 Selector circuit 33 erasure position storage device (erasure position storage means) 34 erasure position address calculation circuit 35 to 36 constant multiplier circuit in a Galois field

Continuation of front page (56) References JP-A-1-276825 (JP, A) JP-A-2-58432 (JP, A) JP-A-62-186620 (JP, A) JP-A-63-156430 (JP) JP-A-63-157529 (JP, A) JP-A-63-316524 (JP, A) JP-A-63-316525 (JP, A) JP-A-63-132532 (JP, A) 63-167527 (JP, A)

Claims (2)

(57) [Claims] 1. An error correction decoding apparatus for correcting and decoding an error in received information, comprising: a received word storage means for storing a received word; a syndrome calculating means for calculating a syndrome of the received word; a Euclidean algorithm arithmetic means for chromatic and dividing means of the error locator polynomial and the plurality of basic operation circuit Galois field multiplication means is constituted by one for generating the error value polynomial and one Galois Te, the Chien search means for determining the error position of the received word from the coefficient of the error locator polynomial,
Euclidean error calculating means for calculating an error value from the error locator polynomial and the error value polynomial, and error correcting means for correcting an error in the received word based on the error value and storing the error in the received word storage means. A plurality of basic arithmetic circuits each composed of one Galois field multiplication means in the Euclidean algorithm arithmetic means are provided so that an operation for generating the error locator polynomial and the error numerical polynomial on the Galois field in the algorithm can be performed for each polynomial unit. Arranged in parallel, and each time the polynomial is divided by the Galois field division means , the coefficients of the divisor polynomial and the polynomial to be divided are directly output to the Galois field multiplication means of the basic arithmetic circuit. An error correction decoding device characterized by the above-mentioned. 2. An error correction decoding apparatus for correcting and decoding an error in received information, comprising: a received word storage means for storing a received word; a syndrome calculating means for calculating a syndrome of the received word; a Euclidean algorithm arithmetic means for chromatic and dividing means of the error locator polynomial and the plurality of basic operation circuit Galois field multiplication means is constituted by one for generating the error value polynomial and one Galois Te, the Chien search means for determining the error position of the received word from the coefficient of the error locator polynomial,
Euclidean error calculating means for calculating an error value from the error locator polynomial and the error value polynomial, and error correcting means for correcting an error in the received word based on the error value and storing the error in the received word storage means. A plurality of basic arithmetic circuits composed of one Galois field multiplication means in the Euclidean algorithm arithmetic means are arranged in parallel so that the operations of the error locator polynomial and the error numerical polynomial on the Galois field in the algorithm can be performed for each polynomial unit. Arranged, further provided with erasure position storage means for storing the erasure position which is the position of the erasure data in the received word, and by inputting the erasure position to the Euclidean algorithm operation means, erasure error correction and normal error correction It is configured to be performed in parallel, and the above Galois field is divided
An error correction decoding apparatus characterized in that the coefficient of the divisor polynomial and the coefficient of the polynomial to be deleted are directly output to the Galois field multiplication means of the basic arithmetic circuit every time the polynomial is divided by the means .