JP2800598B2 - Error correction decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoding device for correcting an error occurring in information encoded by an error correction code, and particularly to reproduction and reception in a digital video recording device and an optical disk device. The present invention relates to an error correction decoding device for processing an error occurring in a digital signal at a high speed.

[0002]

2. Description of the Related Art In an error correction decoding apparatus having a large design distance, an error locator polynomial and an error numerical polynomial are generated from a syndrome obtained from a received signal by a Berlekamp-Massy algorithm or a Euclidean algorithm. Hereinafter, a method of obtaining an error position polynomial and an error numerical polynomial for the RS code having the design distance d by the Euclidean algorithm will be described.

[0003] The Euclidean algorithm refers to the syndromes S ₀ , S ₁ ,
.., S _d-2 , the polynomial A (Z) = Z ^d-1 and the polynomial B
(Z) = S ₀ + S ₁ Z +... + S _{d−2 With} Z ^d−2 as an initial value,

A (Z) / B (Z) = Q0 (Z) Remainder R0 (Z) B (Z) / R0 (Z) = Q1 (Z) Remainder R1 (Z) R0 (Z) / R1 (Z) = Q2 (Z) Remainder R2 (Z)

[0005] This operation is repeated until the degree of the remainder polynomial satisfies a certain condition.

FIG. 7 is a flowchart for obtaining an error locator polynomial and an error numerical polynomial by the Euclidean algorithm. In FIG. 7, first, an initial value is set in the F1 section. Next, the calculation specified by the F2 and F3 parts is performed. Then, it is determined in F4 whether or not the degree of the remainder polynomial satisfies the termination condition. If the termination condition is not satisfied, the polynomial is set in F5, and the calculations in F2 and F3 are repeated.

When the degree of the remainder polynomial satisfies the termination condition in the F4 part, the error locator polynomial σ
(Z) and the error numerical polynomial ω (Z) are obtained. In addition,
In the figure, <> represents the quotient of division, and [] represents the largest integer that does not exceed the value in parentheses.

These calculations have a problem that the calculation time increases as the design distance d increases, and that the circuit configuration becomes complicated. Therefore, a method is generally used in which a Galois field arithmetic unit for performing a product-sum operation and a division operation on a Galois field is configured by hardware and controlled by a microprogram.

FIG. 8 shows an error locator polynomial and an error value polynomial generator in a conventional error correction decoder. In FIG. 8, reference numeral 101 denotes a program R for controlling the operation.
OM built-in program control means, 102 and 103 are RAMs for storing intermediate results of calculation of error locator polynomials and error numerical polynomials, 104 is address generation means for generating addresses of RAM 102, and 105 is RAM 10
3 is an address generating means for generating the address No. 3.

Reference numeral 106 denotes an order storage means for storing an order of a polynomial for calculating an error numerical polynomial having a value stored in the RAM 102 as a coefficient, and reference numeral 107 denotes an error numerical polynomial having a value stored in the RAM 103 as a coefficient. Degree storage means 108 for storing the degree of a polynomial for calculating
Is an order calculating means for calculating the order, 109 is a Galois field arithmetic means for performing a product-sum operation or a division operation on a Galois field, 110, 111, 112 are RAM 102, RA
Value read from M103 and Galois field arithmetic means 10
9 is a register for temporarily holding the output, and 113 is a ROM for outputting the inverse of the Galois field.

Next, the operation will be described. At this time, R
Both the AM 102 and the RAM 103 have a 2d-byte RA
M. When the contents of the degree storage means 106 and 107 become equal to or less than [(d-1) / 2], the operation of generating the error locator polynomial and the error numerical polynomial is terminated by a command from the program controller 101. ing.

First, when an operation start signal is input,
By operating the address generation means 104 and 105, respectively, the initial values are sequentially written to the specified addresses of the RAM 102 and the RAM 103.

At this time, the coefficient of M2 (Z) and the coefficient of U11 (Z) in the F1 section of FIG. 7 are written in the RAM 102, and the M1 (M1) in the F1 section of FIG.
The coefficient of (Z) and the coefficient of U10 (Z) are written. RAM
FIG. 9 shows the relationship between the address to be written to the RAM 102 and the RAM 103 and the initial value. Also, the degree storage means 1
06 stores the degree of the syndrome polynomial S (Z), and the degree storage means 107 stores d-1.

Next, the contents stored in the order storage means 106 and 107 are stored in the address generation means 104 and 107, respectively.
105 respectively. Address generation means 104
The value pointed by the RAM 102 by the register 1
Write to 10. RAM by address generation means 105
The pointed value of 103 is written to the register 111. And the Galois field arithmetic means 109 and the inverse ROM 11
The division on the Galois field is performed by 3 using the output of the register 110 as a divisor and the output of the register 111 as a dividend, and storing the result in the register 110. this is,
Perform polynomial division in F2 portion in FIG. 7, it corresponds to the operation for obtaining the coefficients of the quotient polynomial Q (Z).

Next, the contents stored in the order storage means 106 and the order storage means 10
7, the value of (2d-1) is set in the address generating means 105 on the side of the RAM 103 which stores the coefficients of the polynomial to be removed, and the coefficients of the polynomial are stored. Address generation means 104 of the side RAM 102
Is set to a value obtained by subtracting the output value of the degree calculating means 108 from (2d-1).

The address generating means 104 and 1
The information of the address specified in 05 is stored in the RAM 10
2 and 103 to the registers 111 and 112. The output of the register 111 is multiplied by the coefficient of the quotient polynomial stored in the register 110 and the output of the register 112 by the Galois field arithmetic means 109, and the result is added to the output of the register 112. RA
The data is written to the address pointed to by the address generation means 105 of M103.

Hereinafter, the sequential address generation means 104, 10
5 is decreased by one, and the same operation is performed by the Galois field arithmetic means 109. This operation corresponds to a product-sum operation of a polynomial in the F2 and F3 sections of FIG. Then, when the output of the address generating means 104 on the divisor polynomial side becomes 0, the contents of the degree storage means 107 on the polynomial side to be diminished are decreased by 1, and the next division operation is performed.

When the magnitude relations of the degree storage means 106 and 107 are reversed, one polynomial division operation is completed, and the coefficient of the polynomial to be divided is stored in the RAM 102. Assuming that the coefficient of the divisor polynomial is stored in the RAM 103, a polynomial division operation similar to the above-described arithmetic operation is performed.

Hereinafter, the same operation is repeatedly performed under the control of the program control section 101 until the condition of the F4 section in FIG. 7 is satisfied. As a result, the RAM 102 or R
The coefficients of the error position polynomial and the error numerical polynomial are stored in the AM 103.

[0020]

Since the conventional error correction apparatus is configured as described above, one Galois field arithmetic processor must generate an error locator polynomial and an error numerical polynomial. The time required for calculation has increased.

Further, since the control is performed by the microprogram, it is necessary to fetch, decode, and execute the instruction code from the program ROM to execute one process. There is a problem in that a long time is required for processing, and it is not possible to generate an error locator polynomial and an error numerical polynomial at high speed.

In order to perform erasure correction, a microprogram must be provided with an erasure correction routine, which causes a problem that the capacity of the ROM is increased.

Further, when the parameter of the correction ability determined by the design distance d changes, another microprogram must be prepared according to the different parameter in the program ROM, and the capacity of the ROM increases. Was.

The present invention has been made to solve the above problems, and has as its object to provide an error correction decoding device which can operate at high speed and has a small circuit size.

[0025]

An error correction decoding apparatus according to the present invention is provided with a multiplying means for generating an error locator polynomial and a multiplying means for generating an error numerical polynomial.

Further, by providing storage means for storing d-1 with respect to the design distance d, error correction decoding can be performed for different codes.

Further, by providing the erasure position storage means for storing the erasure position information and the erasure position address generation means for generating the output address, the correction syndrome and the erasure position polynomial can be calculated so that the erasure error correction can be performed. It is made possible.

Further, by providing a one-to-one addition circuit for adding the held value and an externally input value to each bit of the first and second coefficient storage means, easy control is possible. It is assumed that.

Further, the control signal generating means is configured such that, when an operation start signal is input, a control code to be performed next is sequentially generated from the currently output control code and the state of the internal bus. .

[0030]

The error correction decoding apparatus according to the present invention uses two Galois field multiplication means to separately calculate an error locator polynomial and an error numerical polynomial, thereby generating an error locator polynomial and an error numerical polynomial. Can be performed at high speed.

Further, the storage means for storing parameters such as the code length, the design distance, and the number of erasure corrections,
Even for codes having different parameters such as product codes, the circuit scale can be reduced.

Further, by means for storing the erasure position addresses, to store the erasure position address, erasure locator address
Erasure position information specified by the error location polynomial
By inputting the data to the generating means and the error numerical polynomial generating means, the erasure position polynomial and the corrected syndrome polynomial can be calculated easily and at high speed, and the increase in the circuit scale is suppressed as much as possible.

Further, by providing a one-to-one addition circuit for adding the value held from the externally input value to each bit of the first and second coefficient storage means, easy control is possible. Becomes

In the process of generating the error locator polynomial and the error numerical polynomial, the next control code is sequentially executed from the output status of the internal bus and the currently output control code without performing control by a microprogram. Since the signals are performed by hardware, high-speed operation is possible.

[0035]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an error locator polynomial and an error numerical polynomial generator in the error correction decoding device. In FIG. 1, reference numeral 1 denotes coefficient storage means for storing two polynomial coefficients for calculating an error numerical polynomial, and 2 denotes coefficient storage for storing two polynomial coefficients for calculating an error position polynomial. Means 3, 3 and 4 are multiplication means for performing multiplication on the Galois field, 5 is an inverse ROM which outputs an inverse on the Galois field with respect to the output of the coefficient storage means 1,
6 is a selector, 7 is storage means for temporarily storing intermediate results of the operation, 8 is output address generation means for generating output addresses of the coefficient storage means 1 and the coefficient storage means 2, and is a coefficient storage means. 1 and the same address are generated for the coefficient storage means 2.

9 is a coefficient storage means 1 and a coefficient storage means 2
This is an address generating means for generating the same input address for the coefficient storage means 1 and the coefficient storage means 2. 10 and 11 are degree storage means for storing the degrees of two polynomials each having a coefficient as a value stored in the coefficient storage means 1, 12 is a switching means for switching the combination of input and output by a control signal,
13 is storage means for storing the degree of the polynomial for the end condition of the Euclidean algorithm, and 14 is storage means 13
Comparison means for comparing the magnitudes of the degree storage means 10 and 11; operation signal generation means 15 for generating a signal for performing operation control; and 16 for storing the difference between the contents stored in the degree storage means 10 and 11. Order difference storage means.

The coefficient storage means 1 and 2 both have the block configuration shown in FIG. 2. In FIG. 2, reference numeral 17 denotes a decoder for decoding input address information;
Is a 2-1 selector, 19 is a register, 20 is an output selector, and 21 is an adding means comprising an EXOR circuit. In the case of an RS code having a design distance d on GF (2m), the register 19 is constituted by a register of at least 2d words (1 word = m bits).

When an input address is specified to the decoder 17, a selection signal is sent to the corresponding 2-1 selector 18, and the 2-1 selector 18 switches to input from outside and the contents currently stored in the register 19. Are added by the adding means 21, and the data is latched. When the input address for selecting the 2-1 selector 18 is not specified to the decoder 17, the register 19 latches the currently stored content as it is. When the output address is specified, the contents held in the register 19 of the address specified by the selector 20 are output.

Next, the operation will be described. Below,
A process of generating an error locator polynomial and an error numerical polynomial of an RS code having a design distance d on GF (2 ^m ) will be described. First, when a start signal for generating an error locator polynomial and an error numerical polynomial is input, coefficient storage units 1 and 2, order storage units 10 and 11, and end order storage unit 1
3. The initial value is input to the order difference storage means 16. Coefficient notation
Regarding the initial values of storage means 1 and 2 , addresses 0 to (2d
For -1), the contents shown in FIG. 3 are stored. That is, the coefficients of M1 (Z) and M2 (Z) in the F1 part of the flowchart of FIG. The coefficient storage means 2 stores U10 (Z) and U11 (Z) in the F1 part of the flowchart of FIG.
Are stored all at once. The degree storage means 10 stores d-1 and the degree storage means 11 stores d-2. In addition, [(d−
1) / 2], and 1 is stored in the degree storage means 16.

Next, a polynomial division operation is repeatedly performed. Division operation of the polynomial varies in odd-numbered and even-numbered, will be described first odd-numbered division operation. The contents stored in the degree storage unit 11 are loaded into the output address generation unit 8 through the switching unit 12 in accordance with the control signal generated by the control signal generation unit 15. Next, the content pointed to by the output address generation means 8 is output from the coefficient storage means 1 and the inverse ROM 5 takes the inverse of the output content on the Galois field. This inverse element is stored in the storage means 7 through the selector 6.

If the content stored in the storage means 7 is 0, the content of the order storage means 11 is decreased by 1 and the content of the order difference storage means 16 is increased by 1. The comparing means 14 compares the contents of the storing means 13 with the order storing means 10 and the contents of the storing means 13 and the order storing means 11, and when the content of the storing means 13 becomes larger than any of the contents of the storing means 10 and 11, the control signal is outputted. A command is issued to the generation means 15 to end the operation. If the operation does not end, the above operation is repeated.

If the content stored in the storage means 7 is not 0, the content of the degree storage means 10 is again input to the output address generation means 8 through the switching means 12. Next, a value obtained by adding d to the input content is output. Then, the contents of the coefficient storage unit 1 pointed to by the output address generation unit 8 are output. Then, the contents stored in the storage means 7 are multiplied by the Galois field multiplication means 3 and stored in the storage means 7 through the selector 6.

Next, the contents of the degree storage means 11 are loaded into the output address generation means 8 by the switching means 12. On the other hand, the input address generating means 9 loads a value obtained by adding d to the contents of the degree storing means 10. The contents pointed to by the output address generation means 8 are output to the coefficient storage means 1 and 2, respectively, and the contents of the storage means 7 are multiplied by the multiplication means 3 and 4 on the Galois field, respectively.

The results are input to the coefficient storage means 1 and 2 as input data, and the input data and the value pointed by the input address generation means 9 are added to the addition means 2.
1 is added and latched. Then, the same operation is repeated by decreasing the values output by the output address generation means 9 and the input address generation means by 1 until the output of the output address generation means 8 becomes 0.

If the contents of the order difference storing means 16 are not 0, the contents of the order storing means 10 and the contents of the order difference storing means 16 are decreased by one. Then, the above-mentioned odd-numbered polynomial division operation is repeated again.

When the content of the order difference storage means 16 is 0, the content of the order storage means 10 is reduced by one, and the order difference storage means 16 is loaded with 1; Perform the operation. As a result, one division operation is completed, and if it is not completed in the end determination, the following even-numbered polynomial division operation is performed.

The following operation is performed for the even-numbered polynomial division. In accordance with the control signal generated by the control signal generating means 15, a value obtained by adding d to the content stored in the degree storing means 10 is loaded into the output address generating means 8 through the switching means 12. Next, the content pointed to by the output address generation means 8 is output from the coefficient storage means 1, and
An inverse element on the Galois field of the output content is obtained by the inverse element ROM 5. The inverse is passed through the selector 6 and the storage means 7
Is stored.

When the content stored in the storage means 7 is 0, the content of the order storage means 10 is decreased by 1 and the content of the order difference storage means 16 is increased by 1. The comparing means 14 compares the contents of the storing means 13 with the order storing means 10 and the contents of the storing means 13 and the order storing means 11, and when the content of the storing means 13 becomes larger than any of the contents of the storing means 10 and 11, the control signal is outputted. A command is issued to the generating means 15 to end the operation. If the operation does not end, the above operation is repeated.

If the content stored in the storage means 7 is not 0, the content of the degree storage means 11 is loaded into the output address generation means 8 again. Next, the content pointed to by the output address generation means 8 is output from the coefficient storage means 1. Then, the contents stored in the storage means 7 are multiplied by the Galois field multiplication means 3 and stored in the storage means 7 through the selector 6.

Next, in the output address generating means 8,
Order storage means 1 loaded by switching means 12
Add d to the contents of 0. On the other hand, the contents of the degree storage means 11 are loaded into the input address generation means 9. The contents pointed to by the output address generation means 8 are output to the coefficient storage means 1 and 2, respectively, and the output contents are multiplied by the multiplication means 3 and 4 on the Galois field with the contents of the storage means 7, respectively. Then, the value pointed by the input address generation means 9 is added to the result, and
Latch.

The same operation is repeated by decreasing the values of the output address generation means 8 and the input address generation means by 1 until the output of the output address generation means 8 becomes d. If the contents of the order difference storage means 16 are not 0, the contents of the order storage means 11 and the contents of the order difference storage means 16 are decreased by one. Then, the even-numbered polynomial division operation described above is repeated again.

When the content of the order difference storage means 16 is 0, the content of the order storage means 11 is reduced by one, and 1 is loaded into the order difference storage means 16. Perform the operation. As a result, one polynomial division operation is completed, and if it is not completed in the end determination, the odd-numbered polynomial division operation is performed.

As a result of performing the above operation, when an odd number of polynomial division operations are performed, the error numerical polynomial is stored at (2d-1) from the address d of the coefficient storage means 1, and The position polynomial is stored at (2d-1) from address d of the coefficient storage means 2.
When an even number of polynomial division operations are performed, the error numerical polynomial is stored at addresses 0 to (d-1) of the coefficient storage means 1, and the error position polynomial is stored in the address of the coefficient storage means 2. From 0 to (d-1).

Embodiment 2 FIG. In the above embodiment, correction of a normal error has been described. However, the configuration shown in FIG. 4 enables decoding even when an erasure error and a normal error are mixed. In FIG. 4, reference numeral 22 denotes a lost position information storage unit for storing lost position information. In the lost position information storage unit 22, e pieces of lost position information from addresses 0 to (e-1) are written in advance. I have. Reference numeral 23 denotes an address generation unit representing an output address of the lost position information storage unit 22, and reference numeral 24 denotes a selector. The components having the same reference numerals as those in FIG. 1 are the same as those described in the first embodiment.

Next, the operation will be described. Below,
A process of generating an error locator polynomial and an error numerical polynomial for an RS code having e erasures and a design distance of d will be described. First, when an operation start signal is input, an initial value is set.

Here, (e-1) is set in the erasure position address generation means 23. Further, the end degree storage means 13
Stores [(d-1 + e) / 2]. Coefficient storage means 1 and 2, degree storage means 10 and 11, and degree difference storage means 1
6 is set to the same value as the initial value described in the first embodiment.

The contents (d-2) of the degree storage means 11 are loaded into the output address generation means 8 through the switching means 12. The input address generation means 9 includes a switching means 1
2, the contents (d-1) of the degree storage means 10 are loaded. The storage unit 7 stores the value pointed by the erasure position address generation unit 23 in the erasure position storage unit 2.
2 and stored through the selector 24.

In the coefficient storage means 1 and 2, the value indicated by the output address generation means 8 is output. Then, the contents stored in the storage means 7 are multiplied by the multiplication means 3 and 4 on the Galois field, respectively, and added to the value stored at the position indicated by the input address generation means 9 and stored.

Next, the contents stored in the output address generation means and the input address generation means are reduced by one,
Perform the same operation. This operation is performed by the output address generation means 8
Is repeatedly performed until the content stored in the file becomes zero.

Then, the erasure position output address generation means 2
3 is decremented by one, and the lost position information storage means 2
2 is stored in the storage means 7, and the multiplication operation on the Galois field is repeatedly performed. This operation is performed until the output of the erasure position output address generating means 23 becomes 0. Then, the content of the address (d-1) of the coefficient storage means 1 is set to 0.

As a result, the address 0 of the coefficient storage means 1
(D-1) stores the coefficients of the modified syndrome polynomial, and the addresses 0 to 0 of the coefficient storage unit 2 are stored.
In (d-1), the coefficients of the erasure position polynomial are stored. For the subsequent operation, the operation described in the first embodiment is performed, and the operation is repeated until the comparison unit 14 detects the end condition.

Embodiment 3 FIG. FIG. 5 shows the control signal generating means 15.
In the figure, reference numeral 25 denotes control code storage means for performing the next step, 26 denotes a decoder for generating a control signal, and 27 denotes a control for generating a control code to be stored in the storage means 25. Code generation means.

Next, the operation will be described. In the process of obtaining the error locator polynomial and the error numerical polynomial, instruction numbers are assigned to the respective operations described in the first and second embodiments. First, when the operation start signal is input, the control code generating means 27 sets the state in which the first operation is performed to an assigned value, and causes the control code storage means 25 to store the value.

In the next step, control code storage means 2
5 is decoded by the decoder 26 and output as a control signal for generating an error position polynomial and an error numerical polynomial. The signal decoded by the decoder 26 is also input to the control code generation means 27, and the control code generation means 27 calculates the following based on the state of the internal output signal for calculating the error locator polynomial and the error numerical polynomial. To generate a signal to perform the operation,
It is stored in the control code storage unit 25. Hereinafter, a control signal is generated by repeating the same operation. When the operation is completed, a signal for performing no operation is output until the next operation start signal is input.

Embodiment 4 FIG. FIG. 6 is a block diagram showing a configuration in which decoding can be performed even when a code parameter is arbitrarily changed. In FIG. 6, reference numeral 28 denotes storage means for storing (d-1) with respect to a design distance d; A subtracter for subtracting 1 from the output of the storage means 28; a storage means 30 for storing the number of erasure corrections; a comparison means 31; a subtractor 32 for subtracting 1 from the output of the storage means 30; In addition,
The same reference numerals as those in FIG. 1 or FIG.
Or, it has the same configuration as that described in the second embodiment.

Next, the operation will be described. Storage means 28
, A value of (d-1) is preset from the outside with respect to the design distance d. Further, the actual number of erasures e and a threshold eh for performing erasure correction set in advance are input to the comparing means 31. When e ≦ eh in the comparing means 31, e is input to the storage means 30, and e> e
In the case of h, 0 is input to the storage means 30.

When the operation start signal of the Euclidean algorithm is input, the contents of the storage means 28 are input to the degree storage means 10 as they are. Further, a value obtained by subtracting 1 from the value stored in the storage unit 28 by the subtractor 29 is input to the order storage unit 11. Also. A value obtained by subtracting 1 from the value stored in the storage unit 30 by the subtractor 32 is input to the erasure position output address generation unit 23. The following operations are the same as those described in the first or second embodiment, so that decoding can be performed even when the parameters of the design distance and the number of erasure corrections are changed.

[0068]

As described above, according to the present invention, the multipliers for obtaining the error locator polynomial and the error numerical polynomial are respectively arranged, and the multipliers are configured to operate simultaneously. Thus, an error correction decoding device capable of calculating an error position polynomial and an error numerical polynomial can be obtained.

Further, by providing storage means for storing d-1 with respect to the design distance d, error correction decoding can be performed for different codes. The erasure position polynomial can be calculated so that erasure error correction can be performed.

In addition to normal errors as well as errors including erasures, decoding can be performed at high speed by directly reading from the means for storing erasure position information to the error locator polynomial and error value polynomial generator. is there.

Further, an addition circuit for adding the held value and the value inputted from the outside to each bit of the first and second coefficient storage means is provided on a one-to-one basis, or the control signal generation means is provided. In the configuration, when the operation start signal is input, the control code to be performed next is sequentially generated from the control code currently output and the state of the internal bus.
Control for calculation becomes easy.

[Brief description of the drawings]

FIG. 1 is a block diagram of an error locator polynomial and an error value polynomial generator in an error correction decoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram of the coefficient storage means in the error locator polynomial and error value polynomial generator according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating the contents of initial values of coefficient storage means in an error locator polynomial and an error value polynomial generator according to one embodiment of the present invention.

FIG. 4 is a block diagram of an error locator polynomial and an error value polynomial generator in an error correction decoding device according to another embodiment of the present invention.

FIG. 5 is a block diagram of a control signal generator in an error locator polynomial and error value polynomial generator according to another embodiment of the present invention.

FIG. 6 is a block diagram of a code parameter setting portion according to another embodiment of the present invention.

FIG. 7 is a flowchart of a Euclidean algorithm for performing calculations when generating an error locator polynomial and an error numerical polynomial.

FIG. 8 is a block diagram of an error locator polynomial and an error value polynomial generator in a conventional error correction decoding device.

FIG. 9 is a block diagram of an error locator polynomial and an error value polynomial generator in a conventional error correction decoding device.

[Explanation of symbols]

 1, 2 coefficient storage means 3, 4 multiplier on Galois field 5 inverse element ROM 6 selector 7 storage means 8 output address generation means 9 input address generation means 10, 11 order storage means 15 control signal generation means 16 order difference comparison means 17 Input address decoder 22 Erasure position information storage means 23 Erasure position output address generation means 28 Design distance storage means 30 Erasure correction number storage means

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yoshiyuki Inoue 1 Baba Zosho, Nagaokakyo-shi Inside Mitsubishi Electric Corporation R & D Center (72) Inventor Makoto Kumano 1st Baba Library in Nagaokakyo-shi Mitsubishi Electric Corporation Electronic product development In the laboratory (56) References JP-A-3-195216 (JP, A) JP-A-5-165662 (JP, A) IEICE, Vol. J73-A, No. 2, p. 261-268 IEEE Trans. Com. Vol. 37, No. 10, p. 1273-80 IEEE Trans. Com. Vol. 34, no. 5, p. 393-403 (58) Field surveyed (Int. Cl. ⁶ , DB name) H03M 13/00-13/22

Claims (5)

(57) [Claims] 1. An error correction decoding device that calculates an error position polynomial and an error numerical polynomial and performs an error correction operation, wherein first coefficient storage means for storing a polynomial coefficient for calculating the error numerical polynomial ; A first multiplying means for multiplying the content output from the first coefficient storage means on a Galois field, and an inverse element on a Galois field for the content output from the first coefficient storage means; Inverse element generating means, second coefficient storing means for storing coefficients of a polynomial for calculating an error locator polynomial, and multiplication on the Galois field to the contents outputted from the second coefficient storing means For the second multiplying means and the first and second coefficient storing means, respectively.
Calculated by the first multiplication means and the second multiplication means.
Adding means for adding the stored value to the stored value ; input address generating means for generating an input address for the first and second coefficient storing means; and adding to the first and second coefficient storing means. An error correction decoding device comprising: an output address generation unit for generating an output address for the output signal; and a control signal generation unit for generating a control signal for sequentially controlling the operation. 2. A storage device for storing a numerical value of d-1 with respect to a design distance d, wherein the input address generating unit and the input address generating unit
The output address generating means generates the address based on the numerical value of the storage means.
Generate input and output addresses, respectively, and use different
Error correction decoding apparatus according to claim 1, wherein the perform error correction decoding even for the item. A erasure position storage means for wherein storing erasure position information, Bei example the erasure position address generating means for generating an output address of the erasure position storage means, the erasure error correction
The first multiplying means and the second multiplying means
Multiplication is performed using the lost position information,
2. The error correction decoding apparatus according to claim 1, wherein a drome polynomial and an erasure position polynomial are calculated . 4. The apparatus according to claim 1, further comprising a one-to-one adder circuit for adding a value held and an externally input value to each bit of said first and second coefficient storage means. Item 7. The error correction decoding device according to Item 1. 5. The control signal generator according to claim 1, wherein when an operation start signal is input, a control code to be performed next is sequentially generated from a control code currently output and a state of an internal bus. 2. The error correction decoding device according to 1.