JPH05268101A - Chain search circuit - Google Patents

Abstract

PURPOSE:To make the algorithm complete through the search by a code length by arranging multipliers of higher-degree coefficients from a latch circuit latching a coefficient of a term of a higher-degree of an error location polynomial after high/low-degree of coefficients of the polynomial are replaced. CONSTITUTION:The circuit is provided with 8-bit registers 1a-1i latching coefficients of an error location polynomial or values with which elements of a Galois field are multiplied, adder circuits 2a-2h adding outputs of the 8-bit registers 1a-1i, an input terminal 3 from which coefficients of the error location polynomial are inputted to the 8-bit registers 1, an 8-bit bus line 4 used to input the coefficients of the error location polynomial to the 8-bit registers 1, and an alpha<75> multiplier 5-alpha<67> multiplier 13 multiplying elements alpha<75>-alpha<67> of a Galois field with each input as the coefficients. That is, the multipliers for higher-degree coefficients multiplying coefficients of continuous elements of a Galois field expressed in exponent representation are arranged from a position latching coefficients of higher-degree terms of the error location polynomial obtained by replacing high/low-degree of coefficients of the error location polynomial.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chain search circuit,
That is, the present invention relates to an improved circuit for solving an error locator polynomial according to the Chien search algorithm when decoding a Reed-Solomon code on the Galois field GF (2 ⁿ ).

[0002]

2. Description of the Related Art The ISO standard (IS
O: International Organization for Standardizatio
In n), the continuous servo system and the sample servo system are recognized as the servo system, and the Reed-Solomon code is adopted as the error correction code in the continuous servo system. The Galois field is GF (2 ⁸ ) and the primitive polynomial p
(X) is

P (X) = X ⁸ + X ⁵ + X ³ + X ² +1 ...
(1)

Reed-Solomon code generator polynomial Gr
(X) is

[0005]

[Equation 1]

However, α ⁱ = (β ⁱ ) ⁸⁸ , and β is defined as an element of the primitive polynomial.

The Chien search algorithm utilizes the finite number of Galois field elements and sequentially substitutes them into a polynomial. Whether or not the value of the polynomial becomes 0 determines whether or not the element is a solution. The decision is made, and this is executed for all elements to solve the polynomial.

Further, the error locator polynomial indicates the information corresponding to the error position of the data, and the error position of the data can be detected by solving it according to the Chien search algorithm.

FIG. 2 shows, for example, the optical disc IS described above.
A chain search circuit used in a decoding circuit for an error correction code conforming to the O standard continuous servo system, in the figure, 1a to 1i hold the coefficients of the error locator polynomial, or those obtained by multiplying this by the element of the Galois field. 8-bit register 2a to 2h for performing 8-bit register 1a to 1i
An adder circuit 3 for adding the outputs of 3 is an input terminal for inputting the coefficient of the error locator polynomial to the 8-bit register 1, and 4 is an 8-bit register used for inputting the coefficient of the error locator polynomial to the 8-bit register 1. Bus line, 15, 16, 1
7,18,19,20,21,22,23 are the solutions of the code generation polynomial of the Reed-Solomon code to the inputs, respectively, and the elements α ¹²⁰ , α of the exponentially represented continuous Galois field.
¹²¹ , α ^{12 2} , α ¹²³ , α ¹²⁴ , α ¹²⁵ , α ¹²⁶ , α
An α ¹²⁰ multiplier that multiplies ¹²⁷ and α ¹²⁸ as its coefficients,
α ¹²¹ multiplier, α ¹²² multiplier, α ¹²³ multiplier, α ¹²⁴ multiplier, α ¹²⁵ multiplier, α ¹²⁶ multiplier, α ¹²⁷ multiplier, α
¹²⁸ multipliers, which can be composed of multiple exclusive OR gates. Reference numeral 14 is an output terminal for notifying the outside that the output results of the adders 2a to 2h, that is, the calculation result of the error locator polynomial is zero.

Generally, the error locator polynomial σ (X) is

Σ (X) = σ ₀ + σ ₁ X + σ ₂ X ² + ... + σ _t X ^t (3)

And t represents the number of symbols that can be error-corrected. In the ISO standard continuous servo system for optical discs (hereinafter simply referred to as optical disc standard), t =
Therefore, the equation (3) becomes

Σ (X) = σ ₀ + σ ₁ X + σ ₂ X ² + ... + σ ₈ X ⁸ (4)

[0014] If the error position when the head position of the data is 0 is at the position m, the error position 2 ⁸
If the element of the Galois field corresponding to -1-m is α _m ,
(4) can be expressed as follows.

Σ (X) = (X−α _m1 ) · (X−α _m2 ) _···· (X−α _m8 ) _·· (5)

However, the subscripts 1, 2, ..., 8 with respect to α _m depend on the number of errors, and in the case where the expression (4) is an eight-order expression of X having the maximum degree, the subscript takes 1 to 8, which is This means that there are eight solutions to equation (5).

Next, the operation will be described. First, α
When checking whether ⁰ (= 1) is the solution of the error locator polynomial (4), as shown in FIG.
As a shift register. That is, the coefficients of the error locator polynomial (4) σ ₈ , σ ₇ , σ ₆ , σ ₅ , σ ₄ , σ ₃ ,
If σ ₂ , σ ₁ , and σ ₀ are input in order from input terminal 3,
From the left side of FIG. 2 through the bit bus line 4, σ ₀ , σ
₁ , σ ₂ , σ ₃ , σ ₄ , σ ₅ , σ ₆ , σ ₇ , and σ ₈ are sequentially stored in the 8-bit register 1 according to the system clock. In the adder circuit 2, nine 8-bit registers 1 shown in FIG.
The nth bits (n = 1 to 8) are added to each other, and the output terminal 14 informs whether or not the outputs of these eight adder circuits 2 are all zero.

As described above, from the left side of the 8-bit register 1, σ ₈ , σ ₇ , σ ₆ , σ ₅ , σ ₄ , σ ₃ , σ ₂ , σ ₁ ,
When σ ₀ is stored, the output terminal 14 indicates that the outputs of the eight adders 2 are all zero (hereinafter, all the outputs of the eight adders 2 are zero. Is abbreviated as the output terminal 14 indicating the zero state), which means that α ⁰ (= 1) is the solution of the equation (4). When α ⁰ (= 1) is the solution of the equation (4), the error position is 2 ⁸ -1-0 (= 255).

Next, when it is examined whether or not α ¹ is the solution of the equation (4), the bus line 4 is turned on by a switch (not shown).
Separated from the bit register 1, and as shown in FIG.
The bit register 1 is made to function as an independent register. The coefficients of the error locator polynomial are already in the register from the left side of the figure σ ₈ , σ ₇ , σ ₆ , σ ₅ , σ ₄ , σ ₃ , σ ₂ , σ
₁ and σ ₀ are stored, and the value multiplied by the α ^{120 to} α ¹²⁸ multiplier is stored in each register according to the system clock. At this time, if the output terminal 14 indicates the zero state, α ¹ becomes a solution in the equation (4),
Error position is 2 ⁸ -1 -1 (= 254).

The reason is that when X = α ¹ is substituted in equation (4),

Σ (α ¹ ) = σ ₀ + σ ₁ α ¹ + σ ₂ α ² + ... + σ ₈ α ⁸ (6)

Thus, when α ¹ is the solution of equation (4), the equation
If (6) = 0 and Equation (6) = 0, the equation may be multiplied by α ^120, and the right side of Equation (6) is

Α ¹²⁰ (σ ₀ + σ ₁ α ¹ + σ ₂ α ² + ... + σ ₈ α ⁸ ) (7)

And the coefficients of the error locator polynomial σ ₈ and σ
It is possible to check at the output terminal 14 whether or not the result obtained by multiplying each of ₇ , σ ₆ , σ ₅ , σ ₄ , σ ₃ , σ ₂ , σ ₁ , and σ _{0 by} a multiplier α ^{120 to} α ¹²⁸ is zero. Because you can.

Next, when checking whether or not α ² is the solution of the equation (4), the same control as in the case of α ¹ is performed, and the coefficients of the error locator polynomial σ ₈ , σ ₇ , σ ₆ , σ ₅ , σ ₄ ,
σ ₃ , σ ₂ , σ ₁ , and σ ₀ are multipliers α ^{120 to} α, respectively.
It suffices to check at the output terminal 14 whether or not the result obtained by multiplying ¹²⁸ by two times is zero. This means whether or not the following formula (8) = 0 holds.

Α ²⁴⁰ (σ ₀ + σ ₁ α ² + σ ₂ α ⁴ + ... + σ ₈ α ¹⁶ ) (8)

If α ² is the solution of equation (4) = 0, then
(8) It can be seen that = 0.

Further, for α ^{3 and} after, control is performed in the same manner as above, and a solution satisfying the equation (4) = 0 is obtained.

Assuming that the obtained solution is α ⁱ , the corresponding position in the codeword is expressed as 2 ⁸ −1-i, so that for all elements α ⁰ , α ¹ ..., α ²⁵⁴ of the normal Galois field,
The multiplication is performed a total of 255 times to obtain the solution α ⁱ of the equation (4) = 0, and then the error position 2 ⁸ -1-i in the code word is calculated.

Regarding the element 0 of the Galois field, the output of the output terminal 14 becomes 0 in the initial state, that is, in the state where each 8-bit register is cleared, so it can be determined that this is the solution.

Here, Table 1 shows the configuration of the multiplier using the exclusive OR gate when the Galois field element related to error correction defined in the continuous servo system of the optical disc ISO standard is used as the coefficient of the multiplier. The method and the minimum required number of exclusive-OR gates are represented by vectors for each of α ^{120 to} α ¹²⁸ . In Table 1,
The nth bit of the bit configuration represents the nth bit of the multiplier output, where LSB is the 0th bit and MSB is the 7th bit. For example, the bit configuration of the multiplier α ¹²⁰ is “A2”
(Hexadecimal number), which is expressed as “101000010” in binary number, and the 0th bit and the 2nd bit of the input
By taking the exclusive OR of the 6th bit and the 6th bit
^This means that the 0th bit output of the ¹²⁰ multiplier can be configured. Since the 0th bit output of the α ¹²⁰ multiplier takes the exclusive OR of the 0th bit, the 2nd bit and the 6th bit of the input, at least two exclusive OR gates are required. When the other bit outputs (1st bit to 7th bit) are also taken into consideration, it is shown that the minimum number of exclusive OR gates required for the multiplier α ¹²⁰ is 17 in total.

[0032]

[Table 1]

When the degree of the error locator polynomial (4) is less than the eighth degree, for example, if the degree is the second degree, the equation (4) is expressed as follows.

Σ (X) = σ ₀ + σ ₁ X + σ ₂ X ² (9)

To input this to the Chien search circuit,
In FIG. 2, σ ₀ , σ ₁ , σ ₂ , 0, 0, 0, 0,
0, 0 is input in order from the input terminal 3, and from the left side of FIG. 2 through the bus line 4, 0, 0, 0, 0, 0, 0, σ ₂ , σ
After storing ₁ and σ ₀ in the 8-bit register 1, the solution of the error locator polynomial is obtained by the method described above.

[0036]

Since the conventional Chien search circuit is configured as described above, after checking whether or not it is the solution of the error locator polynomial for all the elements of the Galois field, the error is detected. There is a problem that it is necessary to perform conversion to a position, and it takes time to solve the error locator polynomial.

The present invention has been made to solve the above-mentioned problems, and it is not necessary to check whether all elements of the Galois field are solutions of the error locator polynomial, and at the same time, it is provided in the Chien search circuit. The multiplier can be configured with a small number of gates, and the lower the order of the error locator polynomial, the faster the solution locating operation of the error locator polynomial can be reached, and the error position i and the solution α ^{i of the} error locator polynomial can be obtained. The purpose is to obtain a Chien search circuit which has the characteristic that the algorithm is completed by searching for the code length as it is.

[0038]

The Chien search circuit according to the present invention has an exponent from the side that holds the coefficient of the higher order term of the error locator polynomial obtained by reversing the coefficient of the error locator error locator polynomial. The circuit for multiplying the original coefficient of the continuous Galois field represented is arranged from the higher order coefficient.

Further, the Chien search circuit according to the present invention holds the coefficient of the higher order term of the error locator polynomial obtained by inverting the height of the coefficient from the input side of the circuit.

Further, the chain search circuit according to the present invention, in the error correction defined by the continuous servo system of the optical disc ISO standard, is the original coefficient of the exponentially represented continuous Galois field which constitutes the chain search circuit. Α
^{67 to} α ⁷⁵ .

[0041]

In the Chien search circuit according to the present invention, the coefficient of the error locator polynomial obtained by reversing the coefficient of the error locator polynomial is reversed, and the coefficient of the higher-order term of the error locator polynomial is held by the element of the continuous Galois field expressed in exponential form. Since the circuit for multiplying the coefficient of is arranged higher than that of the higher-order coefficient, the Chien search algorithm can be applied to the expression in which the height of the coefficient of the error locator polynomial is reversed, and the error position i and the error The solution α ^{i of the} position polynomial directly corresponds, and the algorithm ends with the search for the code length.

Further, in the Chien search circuit according to the present invention, the original coefficients of the exponentially expressed continuous Galois field that form the circuit are arranged by exponential expression by arranging those having higher-order coefficients from the input side of the circuit. Since the multiplier for multiplying the original coefficient of the continuous Galois field is arranged with the coefficient of higher order than the input side of the Chien search circuit, the lower the order of the error locator polynomial, the more The solution operation of the error locator polynomial can be reached quickly.

Further, the Chien search circuit according to the present invention, in the error correction defined by the continuous search method of the optical disk ISO standard, is the original coefficient of the exponentially represented continuous Galois field which constitutes the Chien search circuit. Since α is set to α ^{67 to} α ⁷⁵ , the number of gates required for the configuration of the coefficient multiplier is small.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a chain search circuit applied to an optical disc standard according to an embodiment of the present invention. In the figure, 1
a to 1i are 8-bit registers for holding the coefficients of the error locator polynomial or those obtained by multiplying the elements of the Galois field, 2a to 2h are adder circuits for adding the outputs of the 8-bit registers 1a to 1i, and 3 is an error Input terminals for inputting the coefficient of the position polynomial to the 8-bit register 1, 4 are 8-bit bus lines used when inputting the coefficient of the error position polynomial to the 8-bit register 1, 5, 6, 7, 8 , 9,
10, 11, 12, and 13 have Galois field elements α ⁷⁵ , α ⁷⁴ , α ⁷³ , α ⁷² , α ⁷¹ , α ⁷⁰ , α ⁶⁹ , and
α ⁷⁵ multiplier that multiplies α ⁶⁸ and α ⁶⁷ as its coefficient, α ⁷⁴
They are a multiplier, an α ⁷³ multiplier, an α ⁷² multiplier, an α ⁷¹ multiplier, an α ⁷⁰ multiplier, an α ⁶⁹ multiplier, an α ⁶⁸ multiplier, and an α ⁶⁷ multiplier. Reference numeral 14 is an output terminal for notifying the outside that the output results of the adders 2a to 2h, that is, the calculation result of the error locator polynomial is zero.

For the error locator polynomial (4), a coefficient obtained by reversing the coefficient applied to X from a higher order to a lower order is given by equation (10).

/ Σ (X) = σ ₀ X ⁸ + σ ₁ X ⁷ + σ ₂ X ⁶ + ... + σ ₈ (10)

If X is the solution in equation (4), it can be seen that 1 / X is the solution in equation (10). As mentioned above, σ
When (α ⁱ ) = 0, the error position is 2 ⁸ -1-i. Therefore, if / σ (α ⁱ ) = 0, the error position is i.

Next, the operation will be described. First, α
When checking whether ⁰ (= 1) is the solution of the error locator polynomial (4), as shown in FIG.
As a shift register. That is, the coefficients of the error locator polynomial (10) σ ₈ , σ ₇ , σ ₆ , σ ₅ , σ ₄ , σ ₃ ,
When σ ₂ , σ ₁ , and σ ₀ are input in order from the input terminal 3, σ ₀ , σ ₁ , σ ₂ , and σ ₂ from the left side of FIG.
σ ₃ , σ ₄ , σ ₅ , σ ₆ , σ ₇ , and σ ₈ are stored in the 8-bit register 1. The adder circuit 2 adds the nth bits of the nine 8-bit registers 1 of FIG. 1, and the output terminal 14 informs that the outputs of these eight adder circuits 2 are all zero. As described above, from the left side of the 8-bit shift register 1, σ ₀ , σ ₁ , σ ₂ , σ ₃ ,
When σ ₄ , σ ₅ , σ ₆ , σ ₇ , and σ ₈ are stored and the output terminal 14 indicates the zero state, this is α ⁰
We show that (= 1) is the solution of equation (10). In addition, α ⁰ (=
When 1) is the solution of equation (10), the error position is 0.

Next, when checking whether or not α ¹ is the solution of the equation (10), the bus line 4 is separated from the 8-bit register 1 by a switch (not shown), and the 8-bit register 1 is set as an independent register as shown in FIG. To function as. Already in the register the coefficients of the error locator polynomial σ ₀ , σ ₁ ,
σ ₂ , σ ₃ , σ ₄ , σ ₅ , σ ₆ , σ ₇ , and σ ₈ are stored from the left side of the figure, and the values of the registers multiplied by the multipliers α ^{75 to} α ⁶⁷ are stored according to the system clock. Is stored. At this time, if the output terminal 14 indicates the zero state, α ^{1 is the} solution in the equation (10), and the error position is 1. Substituting X = α ¹ in equation (10),

/ Σ (α ¹ ) = σ ₀ α ⁸ + σ ₁ α ⁷ + σ ₂ α ⁶ + ... + σ ₈ (11)

When α ¹ is the solution of equation (10), equation (1
1) = 0. If Expression (11) = 0, the expression may be multiplied by α ^67, and the right side of Expression (11) is

Α ⁶⁷ (σ ₀ α ⁸ + σ ₁ α ⁷ + σ ₂ α ⁶ + ... + σ ⁸ ) ... (12)

And the coefficients of the error locator polynomial σ ₀ , σ ₁ ,
It is possible to check at the output terminal 14 whether or not the result obtained by multiplying each of σ ₂ , σ ₃ , σ ₄ , σ ₅ , σ ₆ , σ ₇ , and σ _{8 by} a multiplier α ^{75 to} α ⁶⁷ is zero.

When it is checked whether or not α ² is the solution of the equation (10), if the same control as that of α ¹ is performed, the coefficients σ ₀ , σ ₁ , σ ₂ , σ ₃ and σ of the error locator polynomial are ₄ , σ ₅ , σ ₆ ,
σ ₇ and σ ₈ may be checked at the output terminal 14 whether or not the result of multiplying the multipliers α ^{75 to} α ⁶⁷ twice is zero at the output terminal 14, which is obtained by the following equation (13): It will be checked whether it is 0 or not.

Α ¹³⁴ (σ ₀ α ¹⁶ + σ ₁ α ¹⁴ + σ ₂ α ¹² + ... + σ ⁸ ) ... (13)

If α ² is the solution of equation (10) = 0, then equation (1
It can be seen that 3) = 0. The same control is performed for α ^{3 and} thereafter, and a solution that satisfies the equation (10) = 0 is found. If the obtained solution is α ⁱ (corresponding to α ^-i in Equation (4)), the corresponding position in the codeword is expressed as i, and the search count of the Chien search algorithm and the error position match. This means that the solution operation (the number of searches) needs to be performed from α ⁰ for the code length (8 bits in the optical disc standard).

When the error locator polynomial (4) has a degree of less than 8, for example, if the degree is quadratic, the equation (10) is expressed as follows.

/ Σ (X) = σ ₀ X ⁸ + σ ₁ X ⁷ + σ ₂ X ⁶ (14)

To input this to the Chien search circuit,
In FIG. 1, first, after clearing nine 8-bit registers 1, they are operated as a shift register, and σ ₂ ,
sigma _1, when the order from the input terminal 3 the sigma ₀ to enter through the bus line 4, sigma from left 8 bit register 1 _0,
This means that σ ₁ , σ ₂ , 0,0,0,0,0,0 are stored. After that, the solution of the error locator polynomial is obtained by the same operation as described above. This is only 3 of σ ₂ , σ ₁ , and σ ₀
It means that the solution operation of the error locator polynomial is reached by the number of inputs, and it is necessary to input σ ₀ , σ ₁ , σ ₂ , ₀ , ₀ , ₀ , ₀ , ₀ , ₀ in order. However, it is possible to reach faster by the coefficient setting operation, and eventually the solution solving operation,
Moreover, the effect becomes larger as the order of the error locator polynomial becomes lower.

Further, Table 2 shows a multiplier by an exclusive OR gate when the element of the Galois field for error correction defined by the continuous servo system of the optical disc ISO standard in this embodiment is a multiplier. 2 shows a vector representation of the construction method and the required minimum number of exclusive OR gates for each of α ^{67 to} α ⁷⁵ .

[0061]

[Table 2]

With respect to α ^{67 to} α ⁷⁵ , with respect to the error correction as described above, the necessary minimum number of gates is calculated for all elements of 9 exponentially continuous Galois fields by using an electronic computer. As a result, the one having the minimum total gate number was obtained, and the total number of gates was 150 (= 17) even when compared with the conventional case of α ^{120 to} α ^128.
From + 15 + 16 + 15 + 17 + 8 + 18 + 17 + 17) to 126 (= 10 + 15 + 15 + 10 + 18 + 9 + 15)
It has significantly decreased to + 14 + 10).

In the above embodiment, the original coefficients of the continuous Galois field represented by the exponential which constitutes the Chien search circuit are arranged so that the higher coefficients are arranged from the input side of the circuit. Error location polynomial coefficients σ ₀ , σ ₁ , σ ₂ ,
By reversing the order of inputting σ ₃ , σ ₄ , σ ₅ , σ ₆ , σ ₇ , and σ ₈ , it is possible to arrange a circuit having a lower order coefficient from the input side of the circuit. In this case, there is an effect that the error locator polynomial can be solved by a search having the same length as the code length, but when the order of the error locator polynomial is low, the effect that the coefficient setting operation can be executed quickly cannot be obtained.

In each of the above embodiments, the Galois field is GF.
I explained only the case of (2 ⁸ ), but the Galois field is G
Needless to say, it can be applied to the case of F (2 ⁿ ), and the same effects as those of the above-mentioned respective embodiments can be obtained.

[0065]

As described above, according to the present invention, the coefficient of the error locator polynomial is multiplied by the element of the continuous Galois field expressed in exponential form, and the multiplication result for each term of the error locator polynomial is added. In a Chien search circuit that obtains the solution of the error locator polynomial by using a multiplier having a higher coefficient than that of the holding circuit that holds the coefficient of the term with a high degree of the error locator polynomial after the high and low coefficients are reversed. Since it is arranged, the Chien search algorithm can be applied to an expression in which the height of the coefficient of the error locator polynomial is reversed.
The error position i and the solution α ⁱ of the error position polynomial directly correspond to each other, and there is an effect that the algorithm can be ended by searching for the code length.

Further, according to the Chien search circuit according to the present invention, the coefficient of the higher order term of the error locator polynomial obtained by reversing the coefficient level from the input side of the circuit is held, and thereby the element of the Galois field is held. Since the multiplier for multiplying the coefficient of is arranged with higher-order coefficient than the input side of the Chien search circuit, the lower the order of the error locator polynomial, the faster the error locator polynomial solution operation. There is an effect that can be reached.

Further, according to the Chien search circuit of the present invention, the element of the continuous Galois field expressed by the exponential is selected so that the number of gates required for the configuration of the multiplier is minimized. This has the effect of reducing the number of gates required to construct the coefficient multiplier.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a chain search circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional chain search circuit.

FIG. 3 is a diagram showing a connection state of registers when checking that α ^{0 is a} solution.

FIG. 4 is a diagram showing a connection state of registers when it is checked that α ⁱ other than α ⁰ is a solution.

[Explanation of symbols]

1 8-bit Register 2 Adder Circuit 3 Input Terminal 4 Bus Line 5 α ⁷⁵ Multiplier 6 α ⁷⁴ Multiplier 7 α ⁷³ Multiplier 8 α ⁷² Multiplier 9 α ⁷¹ Multiplier 10 α ⁷⁰ Multiplier 11 α ⁶⁹ Multiplier 12 α ⁶⁸ Multiplier 13 α ⁶⁷ Multiplier 14 Output terminal

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 18, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

FIG. 2 shows, for example, the optical disc IS described above.
A chain search circuit used in a decoding circuit for an error correction code conforming to the O standard continuous servo system, in the figure, 1a to 1i hold the coefficients of the error locator polynomial, or those obtained by multiplying this by the element of the Galois field. 8-bit register 2a to 2h for performing 8-bit register 1a to 1i
An adder circuit 3 for adding the outputs of 3 is an input terminal for inputting the coefficient of the error locator polynomial to the 8-bit register 1, and 4 is an 8-bit register used for inputting the coefficient of the error locator polynomial to the 8-bit register 1. Bus line, 15, 16, 1
7,18,19,20,21,22 and 23 are the solutions of the primitive polynomial of the Reed-Solomon code to the inputs, respectively, and the elements α ¹²⁰ and α of the continuous Galois field expressed in exponential
¹²¹ , α ¹²² , α ¹²³ , α ¹²⁴ , α ¹²⁵ , α ¹²⁶ , α
An α ¹²⁰ multiplier that multiplies ¹²⁷ and α ¹²⁸ as its coefficients,
α ¹²¹ multiplier, α ¹²² multiplier, α ¹²³ multiplier, α ¹²⁴ multiplier, α ^{12 5} multiplier, α ¹²⁶ multiplier, α ¹²⁷ multiplier, α
¹²⁸ multipliers, which can be composed of multiple exclusive OR gates. Reference numeral 14 is an output terminal for notifying the outside that the output results of the adders 2a to 2h, that is, the calculation result of the error locator polynomial is zero.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

Next, the operation will be described. First, α
When checking whether ⁰ (= 1) is the solution of the error locator polynomial (4), as shown in FIG.
As a shift register. That is, the coefficients of the error locator polynomial (4) σ ₀ , σ ₁ , σ ₂ , σ ₃ , σ ₄ , σ ₅ ,
When σ ₆ , σ ₇ , and σ ₈ are input in order from input terminal 3, 8
From the left side of FIG. 2 through the bit bus line 4, σ ₈ , σ
_{7, σ 6, σ 5,} σ 4, σ 3, σ 2, σ 1, σ 0 is store the 8-bit register 1 according to the system clock. In the adder circuit 2, the nth bits (n = 1 to 8) of the nine 8-bit registers 1 in FIG. 2 are added together, and at the output terminal 14, are all the outputs of these eight adder circuits 2 zero? Tell whether or not.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

Next, when checking whether or not α ² is the solution of the equation (4), the same control as in the case of α ¹ is performed, and the coefficients of the error locator polynomial σ ₈ , σ ₇ , σ ₆ , σ ₅ , σ ₄ ,
Each of σ ₃ , σ ₂ , σ ₁ , and σ ₀ has a multiplier α ^{120 to} α
It suffices to check at the output terminal 14 whether or not the result obtained by multiplying ¹²⁸ by two times is zero. This means whether or not the following formula (8) = 0 holds.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

Assuming that the obtained solution is α ⁱ , the corresponding position in the codeword is expressed as 2 ⁸ −1-i, and therefore, normally , Galois field elements α ⁰ , α ¹ ..., for all alpha ^254, is performed a total of 25 4 multiplications, the solution of equation (4) = 0 alpha
ⁱ is obtained, and then the error position in the codeword is 2 ⁸ −1−
i is being calculated.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Delete

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

[0038]

Means for Solving the Problems] Chien search circuit according to the present invention, from the side for holding the coefficients of the higher order terms of the error locator polynomial obtained by reversing the high and low coefficients of locator polynomial Ri erroneous, exponential expression The circuit for multiplying the original coefficient of the continuous Galois field is arranged from the higher coefficient circuit.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

Further, the Chien search circuit of this invention, a multiplier for multiplying the original coefficient of the Galois field continuous, which is the number of finger represented that make up the circuit, the high-order coefficients from the input side of the Chien search circuit I decided to place things, so
The lower the order of the error locator polynomial, the faster it can reach the solution operation of the error locator polynomial.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

[0043] Further, the Chien search circuit in the present invention, in the error correction defined in the continuous servo method standard optical disc ISO, the original Galois field continuous, which is exponential expression constitute a Chien search circuit Since the coefficients are set to α ^{67 to} α ⁷⁵ , the number of gates required for constructing the coefficient multiplier is small.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction content]

When it is checked whether or not α ² is the solution of the equation (10), if the same control as that of α ¹ is performed, the coefficients σ ₀ , σ ₁ , σ ₂ , σ ₃ and σ of the error locator polynomial are ₄ , σ ₅ , σ ₆ ,
It is sufficient to check at the output terminal 14 whether or not the result of multiplying each of σ ₇ and σ _{8 by} the multipliers α ^{75 to} α ⁶⁷ twice is zero. This is because the following equation (13) is given by equation (13) = It will be checked whether it is 0 or not.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0056

[Correction method] Change

[Correction content]

If α ² is the solution of equation (10) = 0, then equation (1
It can be seen that 3) = 0. The same control is performed for α ^{3 and} thereafter, and a solution that satisfies the equation (10) = 0 is found. If the obtained solution is α ⁱ (corresponding to α ^-i in Equation (4)), the corresponding position in the codeword is expressed as i, and the search count of the Chien search algorithm and the error position match. This means that the solution finding operation (the number of searches) needs to be performed from α ⁰ for the code length .

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0059

[Correction method] Change

[Correction content]

To input this to the Chien search circuit,
In FIG. 1, first, after clearing nine 8-bit registers 1, they are operated as a shift register, and σ ₂ ,
sigma _1, when the order from the input terminal 3 the sigma ₀ to enter through the bus line 4, sigma from left 8 bit register 1 _0,
This means that σ ₁ , σ ₂ , 0,0,0,0,0,0 are stored. After that, the solution of the error locator polynomial is obtained by the same operation as described above. This is only 3 of σ ₂ , σ ₁ , and σ ₀
It means that the solution operation of the error locator polynomial is reached by inputting the number of input, and it is necessary to input 0 , 0 , 0 , 0 , 0 , 0, σ ₂ , σ ₁ , and σ ₀ in order. and, calculated solution reached it can faster operation, yet the effect is large enough degree of the error location polynomial is low order.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0062

[Correction method] Change

[Correction content]

With respect to α ^{67 to} α ⁷⁵ , with respect to the error correction as described above, the necessary minimum number of gates is calculated for all elements of 9 exponentially continuous Galois fields by using an electronic computer. results, which one whose total number of gates becomes a minimum value is obtained, even in comparison with the conventional alpha ¹²⁰ to? ^128, the total number of gates 1 4 0 (= 17
From + 15 + 16 + 15 + 17 + 8 + 18 + 17 + 17) to 1 16 (= 10 + 15 + 15 + 10 + 18 + 9 + 15)
It has significantly decreased to + 14 + 10).

[Procedure Amendment 14]

[Document name to be amended] Statement

[Name of item to be corrected] 0066

[Correction method] Change

[Correction content]

Further, according to the Chien search circuit of the present invention, the coefficient of the higher-order term of the error locator polynomial obtained by reversing the level of the coefficient from the input side of the circuit is held, and the exponential expression is performed. The multiplier that multiplies the original coefficients of consecutive Galois fields is arranged with higher-order coefficients than the input side of the Chien search circuit. Therefore, the lower the order of the error locator polynomial, the faster the error. There is an effect that the solution operation of the position polynomial can be reached.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a chain search circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional chain search circuit.

FIG. 3 is a diagram showing a connection state of registers when checking that α ^{0 is a} solution.

FIG. 4 is a diagram showing a connection state of registers when it is checked that α ⁱ other than α ⁰ is a solution.

[Explanation of symbols] 1 8-bit register 2 adder circuit 3 input terminal 4 bus line 5 α ⁷⁵ multiplier 6 α ⁷⁴ multiplier 7 α ⁷³ multiplier 8 α ⁷² multiplier 9 α ⁷¹ multiplier 10 α ⁷⁰ multiplier 11 α ⁶⁹ multiplier 12 α ⁶⁸ multiplier 13 α ⁶⁷ multiplier 14 output terminal 15 α ¹²⁰ multiplier 16 α ¹²¹ multiplier 17 α ¹²² multiplier 18 α ¹²³ multiplier 19 α ¹²⁴ multiplier 20 α ¹²⁵ multiplier 21 α ¹²⁶ multiplication Unit 22 α ¹²⁷ Multiplier 23 α ¹²⁸ Multiplier

Claims (3)

[Claims] 1. A circuit for solving an error locator polynomial when decoding a Reed-Solomon code on a Galois field GF (2 ⁿ ) is expressed as an exponent, which is a solution of a code generation polynomial of a Reed-Solomon code. A multiplier provided for each term of the error locator polynomial that multiplies the elements of the continuous Galois field as a coefficient with the input, and an error locator polynomial obtained by reversing the high and low of the coefficient of the error locator polynomial. Holding circuit for holding the coefficient of the above or the output of the multiplier in the order of the order of the term and outputting the holding result to the multiplier, the holding circuit provided corresponding to each term of the error locator polynomial, and the holding circuit. And an adder that outputs the calculation result of the error locator polynomial after the coefficient reversal, and the multiplier is a coefficient of a term with a high degree of the error locator polynomial after inverting the level of the coefficient. Keep Chien search circuit, characterized in that formed by arranging things higher coefficient than the side that. 2. The chain search circuit according to claim 1, wherein the side holding the coefficient of the term having a high coefficient of the error locator polynomial after reversing the level of the coefficient is the input side of the chain search circuit. circuit. 3. The chain search circuit according to claim 1, wherein elements of the continuous Galois field expressed by the exponential are selected so that the number of gates required for the configuration of the multiplier is minimized.