JPS62111362A - Data processor - Google Patents

Abstract

PURPOSE:To improve processing speed and to reduce the number of steps by executing processing for adding/subtracting a binary number having a n-bit code to/form data exceeding (n) bits only by one step. CONSTITUTION:The address of a starting point is stored in a register (EAR) 2 provided with an incrementer/decrementer and a register (AR) 1 so that the EAR 2 indicates upper two bits. Two complement numbers, that is a number to be added at the time of addition and a number to be subtracted at the time of subtraction are stored in a general register (GR) groups 3. The contents of the AR1 and GR3 are inputted to the registers 5, 6 and added to each other by an arithmetic unit (ALU) 4 and the added result is stored in the AR1. When the contents of the GR3 is a positive number, i.e. MSB=0, '1' is added to the EAR 2 by a signal forming circuit 9 if the carry of the ALU 4 is '1'. When the contents of the GR3 is a negative value, i.e. the MSB is '1', '1' is subtracted from the contents of the EAR 2 if the carry is '0'. Thus, the addition/subtraction can be completed only by one step.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing apparatus for processing image data stored in a bitmap memory.

BACKGROUND OF THE INVENTION Recently, office information equipment has been required to have high-speed image editing functions. Image information opens a two-dimensional space in a one-dimensional memory, and is stored and processed in a part of this space. FIG. 5 shows an example in which an image whose horizontal and vertical dimensions are X and y, respectively, is stored in a space with a width of W words (16 bits/word).

In FIG. 5, 1 is a two-dimensional memory, and 2 is a stored image. a -%-e each has one word (16
bit). The width of l is W word.

If the address in the first line is n, the address in the second line is n-)-w, and the address in the m-th line is n0mw. In other words, to move from b to C, you only need to add W, and conversely, from l] to C
To move to , just subtract W.

As the resolution increases, the amount of image information becomes enormous. For example, in the case of a resolution of 16 lines per word, A, one document requires approximately 1 megaword of memory.

Since the integer value that can be expressed in 16 bits is 65535, the address when processing a large capacity memory requires 20 bits or more if access is performed in units of 16 bits.

FIG. 6 is for explaining a method for specifying one point in the memory when a 24-bit address register and a 4-bit bit position register are provided. EA1%60
'l is 8 bits, AR602 is 16 bits, BPR60
3 is a 4-bit register, EAR601 and AR60.
2 constitutes a 24-bit address, points to one word a in the 16 megaword memory 4, and any one bit in a 6
05 using BPR603. The row movement explained in FIG. 5 is performed using B P I (.

Since the contents of 603 do not change, EAR601 and AR6
This is achieved by adding and subtracting the width W to 24 bits concatenated with 02.

FIG. 7 is a block diagram of a conventional 16-hinoto take processing device equipped with the renovator shown in FIG. 701 is All, 702 is J No. All, 703 is a general purpose register (GIt), and for convenience of explanation, BPR, 603
is assigned to this block.

An arithmetic unit (ALU) 704 performs arithmetic operations, logical operations, etc. between 16-bit data stored in registers 705 and 706 at a certain timing. 41 is a flag signal reflecting the calculation result. A microprogram control block (MPC) 707 includes a microprogram memory, a microinstruction decoder, and various timing generators. This data processing device has two internal buses, A bus 80 and 13 bus 81, and reads the contents of two registers with one machine processor.
It is possible to transfer the data to the ALU 706 and perform calculations in the ALU 704.

The operation of the off-diagram data processing device will be explained using the timing chart of FIG.

In FIG. 8, T1 to T4 represent four-phase clocks, and each part is controlled by this clock.

One man cycle is from T1 to T4, and 7oIA
The operation of adding W to R and storing the result in 1% 701 is executed in one machine cycle.

The above operation will be explained below.

a represents the contents of the microinstruction register (M i R) and is updated on the leading edge of T I. In the on-n cycle, it is assumed that an instruction (ADD) to add AR701 and W is stored. The output of MiR is fed to the decoder in ~1PC707, and the ADD signal of b is decoded and latched at the leading edge of T3. Internal lotus 80.
81, the contents of AR701, which is an augend, and W, which is an addend, are outputted. Internal bus information is stored in registers 705 and 706 at T3, and at the same time AL[J70
Addition is started at 4 and the output state is as shown in e. Note that in FIG. 8, the oblique portion indicates that the value is indefinite.

That is, the output of AL[J is determined at the trailing edge of '1'4. Also, since the AR701 is the storage location for the results, a signal I-
・I) Al(, the signal becomes 1 as shown in ('') by 'r3.

The storage in Lenosf is L D A, r(, and ′I″I
This is achieved with a signal that is logically ANDed with
R701 is updated. In this way, a normal instruction is ■
Can be executed in machine cycles. In the data processing device shown in FIG. 4, when processing data exceeding the bit width that can be processed by the ALU 704 in 17 cycles,
More than machine cycles are required.

Additions and the like are executed at the timings described above.Next, the case where image 2 in FIG. 5 is processed by the off-diagram data processing device will be described using FIG. 9.

FIG. 9 is a diagram showing the program flow when image 2 in FIG. 5 is processed line by line in the direction from b to d and in case it is processed line by line in the direction from d to b. First, the starting point is determined in process 10, and the processes are changed in steps b and d. b
In this case, in step 20, the addresses of 1ull, tAI(, and 1b) are set. At this time, it is assumed that an appropriate value has been stored in advance for BP.
1. (The same applies to .) If the starting point is d, the address of d is set in EAR and AR in step 21. In order to process one line in next process 30.31 and move to the next line to be processed in process 40.41, in process 40, width W is added to AR, and in process 41, A
Subtract W from R. In steps 50 and 51, the carry of the operation result is determined, and if the starting point is b and the carry is 1, 1 is added to EAR in step 60. When the starting point is d, if the carry is 0, 1 is subtracted from EAR in process 61. Next, in steps 70 and 71, it is determined whether the processing of row Y has been completed, and if it has not been completed, processing of the next row is performed in steps 30 and 31.
Return to If it has finished, the process ends.

Problems to be Solved by the Invention However, with the above configuration, when the starting point of processing changes, two loops are required for high-speed processing, and furthermore, in order to perform addition and subtraction of data exceeding one word, This solves the problem that steps 40 to 60 and 41 to 61 are required, and not only the capacity of the entire program is large, but also the minimum processing loop is long.

The present invention solves the above problem by adding and subtracting data exceeding one word in one step, thereby shortening the minimum loop and reducing the capacity of the entire program.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention adds an incrementer/decrementer to the second information holding means (EA), and decodes the decode information of the instruction to add or subtract AR. EAI% is updated based on the incrementer/decrementer operation mode and its result from the carry information from the arithmetic unit and 1VISB of the B bus (1V1sB of the addend or subtraction, indicating the sign bit of the signed binary number). The above objective is achieved by adding means for generating information for determining whether or not to do so.

Effect: With the above configuration, the present invention allows data exceeding n bits to be
The process of adding and subtracting signed binary numbers of bits is executed in one step, thereby improving the processing speed and reducing the number of steps.

Embodiment FIG. 1 is a block diagram of a data processing apparatus in an embodiment of the present invention.

In Figure 1, 1 is a register (AR), 2 is a register with an incrementer/decrementer (IIU%)
, 3 is a group of general-purpose registers assigned to BPR,
4 is an ALU, 41 is status information that reflects the calculation results of the ALU 4, 5 and 6 are registers that hold data to be calculated by the ALU 4, and 7 is a microprogram control unit (MPC) including a decoder. 71 is a microinstruction decode signal, which in this case is a signal for adding or subtracting ARt.

80 and 81 are the A bus and B bus, respectively, and in the case of addition and subtraction, the data on the B bus becomes the addend and subtraction.

9 is the signal from the decoder (AI for addition) (1) AR1 (8t for subtraction) information) 82, the operation mode of the incrementer/decrementer, and the EArL
A circuit (CONtJ) that generates a signal 91 that determines whether or not to update the data of No. 2 with the calculation result of the incrementer/chik IJ mentor.

FIG. 2.2 is a block diagram illustrating EEAIL2 in FIG. 1 in further detail.

In FIG. 2, 21 is a register that holds the value of EAR2, and 22 is an incrementer/decrementer that increments its contents by +1 or -1 according to a signal from C0NT9 in FIG. 23 is a selector for selecting data to be supplied to EAR2.

LDI;AI” (is the output of ~IPC7 in Figure 1,
LDI; At% power month, from ABS, IDEA1'J
tFigure 1 (7) One of the signals from CONT9,
When IDEAR is 1, output 22 is selected and supplied to EAR. EAR2 does not update data when both LDICAI (and IDEAR are not 1). Incrementer/decrementer 22 uses ADDAI (
When is I, increment (E/l+1) is performed, and when is 0, decrement ([AR, -1) is performed. Since the incrementer/decrementer is only a +r or -1 circuit, it is smaller than the ALU4. Since the gate delay in calculation is one stage per bit even if one ripple carry type is used, in this embodiment there are 8 stages for 8 bits, and the calculation speed can also be faster than that of ALU4.

ADDAE3J, IDE,l, becomes 1 under the following conditions.

Al) DAB is (1) When the instruction adds to AR and the addend is a positive number.

IDEAfL is (2) an instruction to add to ARI, and when the addend is a positive number and the carry is 1, and (31AkL+
When the instruction adds to , the addend is a negative number, and the carry is 0.

becomes. In (3), the two's complement of the addend is taken and added. That is, this is equivalent to subtracting the value before taking the two's complement.

The operation of the above configuration will be explained below. Figure 3 shows f! :A) Width W is the value that connects 12 and AH1
is added to the register WkL (VVR is assigned to general-purpose register 3) that stores E A I-(2
This is a diagram explaining the timing of the operation of storing data into A I'(, 1. The MSB of wrt is assumed to be O.

In FIG. 3, (al to Ig) are similar to the timing chart in FIG. 8, which explains one operation of the data processing device in FIG. h is the carry ((,1)LY) of the status information of the ALU 4, and the ALU of a normal data processing device uses a foresight raising method, and the value of C1tY is determined before the calculation result. (For example, Texas Instruments I'TL IC 5N742
83) I is the content of the EAR, and CM
Since it is logical 1, the contents are updated as 'v]. j is the output of the incrementer/decrementer,
Here, since A Rl addition is performed, it operates as an incrementer. k is from the values of b and h.
It represents information on whether to update E A 1% with the output of the incrementer of I L) EAR, and here, b
Since both and h are 1, It) EAR is also 1. Since k became 1, EAtt of ``at the timing of ``r1''
A value of +1 is stored in the EAR as 1.

In addition, in the case of subtraction, it is sufficient to take the decimal point of 2 of the contents of WR, make W a negative number such as -W, and then add.

In this way, the operation of adding WR directly to f, which is the concatenation of EAR2 and ARI, and storing the result in EAR2 and AH,1 is as follows:
It can be executed in one machine cycle, ie, one step.

A case in which the image shown in FIG. 5 is processed by the data processing apparatus of this embodiment will be explained with reference to FIG. 4.

FIG. 4 is a flowchart when the data processing device of FIG. 1 performs processing similar to the processing in FIG. 9. In FIG. 4, first, in process 10, the width W is set in the register WR.
Store it. In process 20, the starting point of the process is determined,
If the starting point is d, the process goes to process 31, takes the two's complement of VVI (and stores it in wR, and then stores the address of d in EAL (and AR?) in r!l!41. Meanwhile, in process 20, the start point is If is b, leave VVR as is and go to process 40 and store the address of b in gAl (and AR. Process 40
．． After 41, go to process 50. After processing one line, go to process 60.
and executes a microinstruction that adds WR to AR. In process 60, the content of Wll is a positive number, that is, MSB is 0.
If the carry is 1 as a result of A[(, +W11., then E]'uI(, is +1. Also, if the content of WR is a negative number,
That is, when the MSB is 1, if the carry is 0 as a result of AIL-1-WR, EAR is -1. Next, in process 70, it is determined whether the process has been completed Y times, and if it has not been completed, the process returns to process 50 and processes the next line.

In this way, compared to the flowchart in Figure 9, the minimum loop in Figure 8 is the process 3x → 4x → 5x (→6x) → 7x → 3x
(X indicates 0 or 1), and in FIG. 4, the processing is improved as follows: 50→60→70→50.

As described above, according to this embodiment, an incrementer/decrementer is added to ENL''-2, and the operation mode of the incrementer/decrementer is determined from the information for adding ARI, the sign information of the addition/subtraction number, and the carry in the operation. At the same time, by deciding to update EAR with the result of the operation, it is possible to complete the operation in one step even when adding or subtracting a number of bits that exceeds the processing unit of the ALU.Moreover, depending on the direction of processing, the two's complement of the addend can be If you keep it, you can process in either direction in the same loop,
It allows high-speed processing and reduces the number of program steps.

Effects of the Invention As described above, the present invention adds an incrementer/decrementer to the BAR, and stores the decode information of the instruction to add or subtract, the carry information from the arithmetic unit, and the MSB (addition) of the B bus. From the MSB of the number or subtraction, which indicates the sign bit of the signed binary number ('to), the operating mode of the incrementer/decrementer and its result are EAR,
By simply adding a means to generate information that determines whether or not to update the program, the capacity of the program can be reduced and the
Data calculations that exceed words can be processed in one step.
The effect is great.

[Brief explanation of drawings]

Fig. 1 is a block wiring diagram of a data processing device according to an embodiment of the present invention, Fig. 2 is a block wiring diagram of main parts of the data processing equipment, Fig. 3 is a signal timing diagram of main parts of the data processing equipment, Figure 4 is an operation flowchart of the data processing device, and Figure 5
The figure is a conceptual diagram when information is stored by converting a one-dimensional memory to two-dimensional, Figure 6 is a conceptual diagram when expressing one bit in memory, and the off-line diagram is a block wiring diagram of a conventional data processing unit.
FIG. 8 is a signal timing diagram of the main parts of the data processing apparatus, and FIG. 9 is an operation flowchart of the data processing apparatus. 1...Register ('AR,), 2...Register (E
l(), 3,...Register (GR), 4...Arithmetic unit (
ALU), 7... Macro program control block (M
PC), 9... signal generation circuit (CONT). Name of agent: Patent attorney Toshi Nakao (1 person)
S 3 Figure 47 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] first, second, and third information holding means that hold information of n bits or less; first calculation means that calculates n-bit information; A signal circuit that generates a second selection signal that determines whether or not the information of the second calculation means is to be stored in the second information storage means. ,
The first calculation means performs a calculation between the information of the first information holding means and the third information holding means, stores the result in the first information holding means, and at the same time performs the second calculation. If the first selection signal has a first value, the means increases the information in the second information holding means by 1, and if the first selection signal has a second value, the second information If the information in the holding means is -1 and the second selection signal is the first value, the result of the second calculation means is stored in the second information holding means, and the second selection signal is A data processing device characterized in that it does nothing if the signal is a second value.