JPH0434191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector processing device, and particularly to a vector processing device suitable for processing access to sparse matrix data at high speed in processing matrix format data.

[Conventional technology]

In vector processing devices, in large-scale matrix calculations that occur in scientific and technical calculations, the data handled is so large that it may not fit into main memory in its original form. Furthermore, in matrix calculations that handle sparse matrices, only a small number of nonzero elements are involved in the calculation results. Therefore, by providing a function to store matrix data in a compressed format in main memory and decompress and transfer it to a vector register during calculation, it is possible to solve the memory capacity constraint and perform matrix calculation. We are trying to speed up the process.

In this type of vector processing device, a mask register is provided to indicate the validity of the decompressed data on the vector register. mask·
Each bit in the register indicates the validity of the corresponding element in the vector register. Mask bit VMR corresponding to the nth element of the vector register
When (n) has the value “1”, the element is valid, “0”
It is indicated that it is invalid when .

The compressed data on the main memory is addressed as follows by an address register VAR that holds the start address and an increment register VIR that holds the interval value. The address of the nth element is a _o = VAR + ( _o-1 〓 ⁱ⁼⁰ VMR(i)) * VIR ... (1). In the main memory, only valid elements before the nth element are compressed and placed in the main memory, so n
The address of the th element is the value obtained by multiplying the count of "1" mask bits before the element by an increment and adding the start address.

Transfers between compressed data on main memory and decompressed data on vector registers are controlled by the contents of the mask register. For the nth element, mask bits VMR(n)
When takes the value "1", a load from the main memory to the vector register or a store from the vector register to the main memory is performed. If the value is "0", no loading or storing is performed. As described above, memory request control is performed using mask bits, and data is sequentially transferred starting from the first element.

In a vector processing device with such a configuration,
Conventionally, address calculations are performed sequentially as follows.

a _o = a _o-1 + VMR (n-1) * VIR...(2) where a _o is the main memory address of the nth element,
ao _-1 is the main memory address of the immediately preceding (n-1)th element. For this reason, data transfer was performed sequentially using a single load/store pipeline.
Note that related devices of this type include, for example, Japanese Patent Application Laid-Open No. 58-214963.

[Problems to be Solved by the Invention] The above-mentioned conventional technology does not take into account the suitability of the element-parallel multiple pipeline system, and there is a problem in that the multiplexed pipelines are not used effectively. That is, in modern vector processing devices, to increase the ability to transfer data from main memory to vector registers, multiple load/store pipelines are installed to process multiple elements of data in parallel at once. There is a mechanism for transferring. However, in the case of the compression/expansion type data transfer described above, addresses to access the main memory are generated only sequentially under the control of mask bits indicating the validity of the data. For this reason, data could only be transferred using one of the multiple load/store pipelines installed.

An object of the present invention is to provide a vector processing device that calculates main memory addresses of multiple elements in parallel and executes compression/expansion type data transfer in parallel with the elements in multiple installed load/store pipelines. There is a particular thing.

[Means to solve the problem]

The present invention is achieved by configuring the address calculation circuits of each pipeline so that the main memory addresses of the elements to be processed in each pipeline can be calculated in parallel.

The address calculation circuit of each pipeline is configured by a counter that recognizes the element number to be processed in each pipeline, selects a mask bit, and counts the effective number of mask bits, and an element interval value based on the contents of the counter. A multiple generation circuit that generates a multiple of an increment, and by adding the multiple generated above to the main memory address of the element processed in the previous stage in each pipeline, the element to be processed in that stage in each pipeline It consists of a multi-input adder that calculates the main memory address of .

[Effect]

In order to perform address calculation in parallel in each pipeline in an element-parallel multiple pipeline, the following calculation must be performed.

Here, M is the number of multiple pipelines, a _o ~
ao _+M-1 is the main memory address of the element to be processed in this stage, and _aoM to _ao-1 are the main memory addresses of the elements processed in the previous stage. VMR(i) is the mask bit corresponding to the i-th element, and VIR is the element spacing value, increment. Looking at one pipeline, n processed in the previous stage
The difference between the main memory address a _o+jM of the +j-Mth element and the main memory address of the n+jth element to be processed in this stage is a multiple of the increment VIR ( _o+j-1 〓 ^i=n+jM VMR -(i)) *VIR. This multiple is M corresponding to the elements processed in the previous stage.
Among the mask bits, the number of effective mask bits corresponding to the element whose element number is after the element processed by the pipeline _{is o-1} 〓 ^i=n+jM VIR(i) and processed by the stage. Among the M mask bits corresponding to the element, the number of effective mask bits corresponding to the element whose element number is earlier than the element processed by the pipeline _o+j-1 〓 ⁱ⁼ⁿ With VMR(i) Made from Japanese.

Therefore, in the address calculation circuit of each pipeline, a counter counts the number of effective bits, a multiple generation circuit generates a multiple of the increment VIR based on the count value, and an adder generates a multiple of the increment VIR. Main memory address a _o+jM of the n+j−Mth element processed in the previous stage of the pipeline
The main memory address of the n+j element to be processed in the next stage of the pipeline
Find a _o+j . As described above, main memory addresses of multiple elements can be obtained in parallel in multiple pipelines.

If the mask bit corresponding to the element to be processed in each pipeline is "1", a memory request is issued to the main memory using the main memory address obtained by the above address calculation, and the load is executed. Perform store processing. If the mask bit is "0", address calculation is performed but memory requests are suppressed. In this case, only the main memory address held within the address calculation circuit is updated.

The number of remaining elements to be processed is obtained by subtracting the number of elements to be processed in one stage (this is equal to the number of pipelines) from the current number of remaining elements. Then, the detector detects that the number of remaining elements has become non-positive, and the load/store process ends.

〔Example〕

Hereinafter, the content of the present invention will be explained using figures.

FIG. 1 shows the overall configuration of a vector processing device to which the present invention is applied. In Figure 1,
1 is main memory (MS), 2 is vector register (VR), 3 is mask register (VMR), 4 is load/store pipeline (LS), 5 is arithmetic unit (ALU), 6 is data distribution The circuit 7 is a data selection circuit. Each of the vector registers 2 has a capacity to store L elements, and a total of eight vector registers 2 are provided as shown by VR ₀ to VR ₇ . One L-bit mask register 3 is provided. One bit in mask register 3 indicates the validity of one element in vector register 2. In this embodiment, one mask register is used for simplicity, but there may be a plurality of mask registers. The load/store pipeline 4 has eight lines indicated by LS ₀ to _{LS 7} ,
There are eight computing units 5, indicated by ALU ₀ to _{ALU 7} .

Each load/store pipeline sequentially calculates the main memory address of each element of matrix-type data on the main memory, and issues a memory request to the main memory. The calculation result of the main memory address is obtained for each stage, which is the basic unit of pipeline operation, and memory requests are also issued at one stage pitch. When a load instruction or a store instruction is activated, the eight load/store pipelines 4, LS ₀ , LS ₁ , . . . , LS ₇ simultaneously start load/store processing. In the first stage, number 0,
Main memory addresses a ₀ , a _{1 ,} of elements No. 1, ..., No. 7
..., _a7 are calculated simultaneously in eight pipelines 4, and eight memory requests are issued to the main memory 1. In the second stage, numbers 8 and 9
No.,..., main memory address of element No. 15 a ₈ , a ₉ ,
..., a ₁₅ are computed simultaneously in eight pipelines 4, and eight memory requests are sent to main memory 1.
issued to. Below, 8 for each stage
The main memory addresses of 8 elements are calculated simultaneously in 8 load/store pipelines 4, and 8
memory requests are issued to main memory 1. and based on the memory request,
Data transfer of 8 elements is performed between main memory 1 and vector
This is done with register 2.

In the case of a load instruction, the address of data on main memory is sent from load/store pipeline 4 to main memory 1 via path 8, and the data is sent from main memory 1 to main memory 1 via path 9. It is taken out to line 4. Further data enters the data distribution circuit 6 via path 10 and is written via path 11 to the vector register 2 specified by the instruction.

In the case of a store instruction, data on the vector register 2 specified by the instruction is read out to the data selection circuit 7 via path 12 and enters the load/store pipeline 4 via path 15.
In the load/store pipeline 4, a main memory address is given, the main memory address is carried on a path 8, and the data is carried on a path 16 and sent to the main memory 1.

Operations are performed on the data after it is loaded into vector register 2 and before it is stored. An operation is performed between the three registers specified by the operation instruction. Three vectors
Operands are stored in two of the registers, and the operands are read out via the data selection circuit 7 and input to the arithmetic unit 5 via the path 13. The calculation result is output from the calculation unit 5 and passed through the path 14.
The data is written to the vector register 2 via the data distribution circuit 6. If the operation instruction is a mask generation instruction that generates mask bits corresponding to elements, the mask bits obtained as the operation result are written into the mask register 3.

Load/store processing in the load/store pipeline 4 is controlled by mask bits in the mask register 3 for each element. Therefore, the contents of the mask register 3 are read out for each stage by the number of pipelines, that is, 8 bits at a time, and distributed to each pipeline via the path 17.

Next, FIGS. 2 and 3 show the transfer processing operation between compressed data on the main memory and expanded data on the vector register.

Figure 2 shows l pieces of compressed data on main memory.
This figure shows the process of expanding and loading a ₀ , a ₁ , ..., a _l-1 onto a vector register. Before the load process, L mask bits are set in mask register 3 for L elements of vector register 2. The number of “1”s in the mask bits that indicate that the element is valid is:
Equal to the number of compressed data elements in main memory 1. The data on main memory 1 is loaded into the element position of vector register 2 corresponding to mask bit "1" in order from the first element. Element positions corresponding to mask bits "0" are not loaded.

FIG. 3 shows the process of compressing L pieces of expanded data a ₀ , a ₁ , . . . , a _L-1 on the vector register 2 and storing them in the main memory 1. Before store processing, L mask bits are set in mask register 3 for L elements of vector register 2. Contrary to loading, data at element positions of vector register 2 corresponding to mask bit "1" are stored in main memory 1 in order from the beginning.

FIG. 4 shows the configuration of an address calculation circuit with one load/store pipeline, and address calculation in compression/expansion type load/store processing will be explained. This figure shows the configuration when the multiplicity of equation (3) is M=8. In this case, eight elements in the data are loaded and stored in each stage, which is a unit of pipeline operation of processing. Each pipeline is given a value from 0 to 7 called a requester number via a signal line 33. Each pipeline operates by recognizing the sequence of elements to be processed based on the value of the requester number. In the pipeline with requester number 0, elements a ₀ , a ₈ , a ₁₆ , . . . are sequentially loaded and stored.

When the instruction decoding circuit 20 decodes a load/store instruction that instructs data transfer between the compressed data on the main memory 1 and the decompressed data on the vector register 2, the instruction decoding circuit 20 decodes the data on the main memory 1. Information for addressing compressed data is set in registers 21, 22, and 24. The start address of the data is set in the address register VAR21, the data interval value is set in the increment register VIR22, and the length of the data is set in the length register VLR24. Along with the setting of data-related information, a signal to start data load/store processing is sent via the signal line 37, and the latch 39 is set to "1". The output of latch 39 is an AND circuit 40 that controls memory requests.
and begins sending memory requests for load/store processing.

Eight mask bits for the number of pipelines are read out in parallel from mask register VMR3 in synchronization with load/store processing, and pass 1
7 to the register 18. mask·
Bit reading is performed for each stage, similar to the unit of pipeline operation for load/store processing. The mask bits entered in register 18 are transferred to register 19 in the next stage. The outputs of the registers 18 and 19 are sent to the bit selection circuit 35,
36, only a certain range of bits determined by the requester number are extracted, and the bits are input to the counter 23.
will be forwarded to. The counter 23 counts the number of "1" bits in the selected mask bit, controls the multiple generation circuits 26 and 27 from the number obtained by counting, and sets the increment register VIR22 to 0.
Generates multiples of ~7x. The multiple generation circuit 26 generates multiples of 8, 4, and 0 times, and the multiple generation circuit 27 generates multiples of 2, 1, 0, and -1, respectively.
By combining the two, a multiple of 0 to 8 times can be obtained.

In the first stage of load/store processing, the start address of the data is in address register VAR2.
1 to the carry save adder CSA 29 via the selector 25. Increment register VIR based on the number of mask counts simultaneously
The multiple of
Input to save adder CSA29. Both are added by the carry save adder CSA 29 and the parallel adder PA 30 immediately following it, and become the main memory address of the element processed in the first stage. From the second stage onwards, the main memory address of the element processed in the previous stage is set to selector 2.
5 to the carry save adder CSA 29 and used to calculate the main memory address to be processed in this stage. In address calculations from the second stage onwards, the address register
The only difference is that the main memory address obtained in the previous stage is used instead of the contents of VAR21.

FIG. 5 shows an example of address calculation in the load/store pipeline of requester number 3. The mask bits corresponding to the 8 elements following element _ao-8 are "10110100", and the mask bits corresponding to the 8 elements following element _ao to be processed in the next stage are "01011001". Suppose there is. In the pipeline of requester number 3, load/store processing is performed for elements a _o+3-8 and element a _o+3 during two stages. The main memory address of element a _o+3 is the main memory address of element a _o+3-8 and the mask.
It is obtained from the bit VMR(i) (i=n+3-8 to n+2) as follows. First, the bit selection circuit 35 selects the five elements after element a _o+3-8.
Mask bit “10100” corresponding to a _o+3-8 , a _o+4-8 , a _o+5-8 , a o _+6-8 , a _o+7-8 is selected, and Effective number of bits _o-1 〓 ^i=n+3-8 VMR(i)=2 is obtained.
Next, the bit selection circuit 36 selects the mask bit "010" corresponding to the three elements _ao , _ao+1 , and _ao+2 before the element _ao+3 ; Effective number of bits _o+2 〓 ⁱ⁼ⁿ VMR(i)=1 is obtained. counter 23
Both are counted and their sum _o+2 〓 ^i=n+3-8 VMR(i)=
The multiple 3*VIR is generated based on 3. The multiple generating circuit 26 generates 4*VIR, and the multiple generating circuit 27 generates (-1)*VIR, both of which are generated by the Charlie save adder CSA29 and the parallel adder PA3.
0 and a _o+3-8 are added to obtain a _o+3 .

a _o+3 = a _o+3-8 + ( _o-1 〓 ^i=n+3-8 VMR(i) + _o+2 〓 ⁱ⁼ⁿ VMR(i)) *VIR = a _o+3-8 +(2+1)*VIR =a _o+3-8 +3*VIR =a _o+3-8 +4*VIR+(-1)*VIR...(4) In FIG. In addition to selecting bits for determining values, mask bits corresponding to elements to be processed in the pipeline are also selected. The mask bit position corresponding to the processing element is determined from the requester number, the mask bit is extracted, and the AND circuit 40
send to The AND circuit 40 outputs the memory request issue signal from the latch 39 and the bit selection circuit 3.
It is ANDed with the mask bit from 5 and sent to main memory 1 on path 13 as a memory request. If the mask bit corresponding to the element to be processed is "1", a memory request is issued, and the corresponding element is read from or written to the main memory 1. If the mask bit is 0, memory requests are suppressed. When issuing a memory request, the main memory address calculated by the carry save adder CSA 29 and parallel adder PA 30 is sent to the main memory 1 along with the memory request on the path 13.

The length register VLR 24 stores the length of data prior to load/store processing. Each time the load/store process progresses by one stage, the contents of the length register VLR are decremented by 8 by the subtraction circuit 28. In one stage of load/store processing, the same number of elements as the number of pipelines (8) are processed at one time, so the value is -8. When the load/store process is executed for all elements, the subtraction result becomes 0 or less. Then, the sign detection circuit 31 detects the end of the process, resets the latch 40 to "0" by the end signal 38, and closes the AND circuit 40. Since the AND circuit 40 is closed, subsequent transmission of memory requests is stopped.

According to this embodiment, data transfer between compressed data on the main memory and decompressed data on the vector register can be executed by a plurality of load/store pipelines installed in parallel. Therefore, the data transfer speed can be increased by the same amount as the number of pipelines.

〔Effect of the invention〕

According to the present invention, in a vector processing device equipped with an element-parallel multiple load/store pipeline, data transfer between compressed data on main memory and decompressed data on a vector register is also possible. It becomes possible to execute in element parallel form. Therefore, the data transfer speed corresponding to the number of pipelines installed in parallel can be obtained similarly to a normal simple load/store. As a result, matrix calculations for sparse matrices that require compressed/expanded data access can be processed at high speed.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a vector processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the process of decompressing and loading data compressed on main memory onto a vector register, and FIG. 3 is a diagram showing the process of compressing and storing the decompressed data on the vector register into main memory, Figure 4 is a diagram showing the configuration of the address calculation circuit of the load/store pipeline, and Figure 5 is the address calculation It is a figure showing an example. 2...Vector register, 3...Mask register, 4...Load/store pipeline,
21... Address register, 22... Increment register, 35, 36... Bit selection circuit, 23... Counter, 26, 27... Multiple generation circuit, 29... Carry save adder, 30
...Parallel adder.

Claims (1)

[Claims] 1 Consists of multiple arithmetic units, multiple vector registers, multiple vector mask registers that indicate data validity, multiple load/store pipelines, and interleaved main memory To identify data to be processed by the pipeline in order to perform compressed/expanded data transfer between compressed data on the main memory and expanded data on the vector register in the vector processing device. a bit selection circuit that selects the contents of a mask register based on a requester number given to the pipeline; a counter that counts the number of valid bits in the selected bit string; A multiple generation circuit that generates multiple sets of data interval values, that is, multiples of increments, and a main memory address of data processed in the previous processing stage by the pipeline and multiples of multiples of increments from the multiple generation circuit. and a multi-input adder that calculates the main memory address of the data to be processed in the next stage by simultaneously adding them together, and generates the main memory address in parallel for each pipeline, creating an element-parallel multi-pipeline system. A vector processing device characterized by performing the compression/expansion type data transfer by operation.