JPS62226275A - Vector processor - Google Patents

Abstract

PURPOSE:To attain a fast processing with matrix calculation by securing an element parallel form even with the transfer of the compressed data stored in a main memory and the extended data stored in a vector register. CONSTITUTION:When a load or store instruction is started, the load/store pipelines 4 start the load/store processing at the same time. In a load instruction mode the address of the data on a main memory 1 is sent to the memory 1 through the pipeline 4 and data are extracted to the pipeline 4 out of the memory 1. Furthermore the data are written to a vector register 2 via a data distributing circuit 6. In a store instruction mode the data are read to a data selecting circuit 7 out of the register 2 and sent to the pipeline 4. Then data are loaded to the register 2 and stored there. Meanwhile the arithmetic operation is given to the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector processing device, and particularly to a vector processing device suitable for processing access to sparse matrix data at high speed in processing matrix format data.

[Conventional technology]

In vector processing devices, in large-scale matrix calculations that appear in scientific and technical calculations, the data handled is so large that it may not fit into main memory in its original form. In addition, in matrix calculations that handle sparse matrices, only a small number of nonzero elements are involved in the calculation results. Therefore, the matrix data is stored in a compressed format in the main memory, and the vector data is stored in the main memory in a compressed format.
By providing a function to expand and transfer onto a register, it eliminates storage capacity constraints and speeds up matrix calculations.

In this rice vector processing device, a mask O register is provided to indicate the validity of the decompressed data on the vector register. Each bit in the mask register indicates the validity of the corresponding element in the vector register. The element is valid when the mask bit VMR(n) corresponding to the th element of the vector register has the value 11';
10' indicates invalidity.

The compressed data on the main memory is addressed as follows by an address register VAR that holds the start address and an increment register VIR that holds the interval value. The address of the element 1 is compressed and placed in main memory, so the address of the element 2 is calculated by multiplying the count number of 11' mask bits before the element by an increment, and then The value is the addition of the address.

Transfers between compressed data on main memory and decompressed data on the vector fist register are controlled by the contents of the mask register. For the element with loop number H, when the mask pin (rL) takes the value ``19'', a load from the main memory to the vector register or a store from the vector register to the main memory is performed. value 10
? If you take , loading and storing are not performed. As described above, memory request control is performed using mask bits, and data is sequentially transferred starting from the first element.

Conventionally, in a vector processing device having such a configuration, address calculation is performed sequentially as follows.
Here, αU is the main memory address of the rth element, and α2° is the main memory address of the immediately preceding rL-1th element. Therefore, data transfer is performed sequentially through one load, store, and
It was done in a pipeline. Note that related devices of this type include, for example, Japanese Unexamined Patent Publication No. 58-214963.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration the suitability of the element-parallel multiple pipeline system, and there is a problem in that the multiplexed pipelines are not used effectively. In other words, in modern vector processing devices, in order to increase the ability to transfer data from main memory to vector registers,
Multiple load-store pipelines are installed to provide a mechanism to transfer multiple elements of data in parallel at once.

However, in the case of the compression/decompression type data transfer mentioned above,
Addresses to access main memory are generated only sequentially under the control of mask-bits that indicate the validity of the data. For this reason, data could only be transferred using one of the multiple load/store pipelines installed.

An object of the present invention is to store main memories τ k” I of multiple elements in a load/store pipeline installed in multiple
/ 2 k previous 2; It Iy -u 'Wit
I Subspecialty W PI If Ir Eclipse a
An object of the present invention is to provide a vector processing device that performs a block-type data transfer.

[Means for solving problems]

The present invention is achieved by configuring the address calculation circuits of each pipeline so that the main memory addresses of the elements to be processed in each pipeline can be calculated in parallel.

The address calculation circuit of each pipeline is configured by a counter that recognizes the element number to be processed in each pipeline, selects a mask bit, and counts the effective number of mask bits, and an element interval value based on the contents of the counter. A multiple generation circuit that generates a multiple of the increment. By adding the multiple generated above to the main memory address of the element processed in the previous stage in each pipeline, It consists of a multi-input adder that obtains storage addresses.

[Effect]

In an element-parallel multiple pipeline, in order to perform address calculation in parallel in each pipeline, the following calculation must be executed in parallel. Here, M is the number of multiple pipelines, α1 ~ αn+9-2 is the main memory address of the element to be processed in the stage, αN7~"rL-+ is the main memory address of the element processed in the nIJ stage. vMR(L) corresponds to the first element It is a mask fist bit, and v-R is the element interval value and increment.When looking at one pipeline, the main memory address αn+ of the +i−Mth element processed in the previous stage
i-□ and the stay(su)*VIR. This multiple is created from valid mask bits corresponding to elements whose element number is later than the element processed in the pipeline, among the M mask bits corresponding to the elements processed in the previous stage.

Therefore, in the address calculation time M of each pipeline, a counter counts the number of effective bits, a multiple generation circuit generates a multiple of the increment VIR based on the count value, and an adder generates a multiple of the increment VIR in the previous stage of the pipeline. By adding it to the main memory address αn+i−M of the +i−Mth element processed in the above, the main memory address αn+i of the +jth element to be processed in the next stage of the pipeline is determined. As described above, main memory addresses of multiple elements can be obtained in parallel in multiple pipelines.

Corresponding to the element to be processed in each pipeline - If the L6 mask Φ bit is wlt, a memory φ request is issued to the main memory using the main memory address obtained by the address calculation above, and the load session store processing is performed. conduct.

If the mask bit is MA07, address calculation is performed but memory requests are suppressed. In this case,
Only the main memory address held within the address calculation circuit is updated.

The number of remaining elements to be processed is obtained by subtracting the number of elements processed in one stage (this is equal to the number of pipelines) from the current number of remaining elements. and,
The detector detects that the number of remaining elements has become non-positive, and the load/store process ends.

〔Example〕

Hereinafter, the content of the present invention will be explained using figures.

FIG. 1 shows the overall configuration of a vector processing device to which the present invention is applied. In Figure 1, 1 is the main memory (M
S), 2 is a vector register (VR), 3 is a -r disk * v register (VMR), 4 is a load-O-store pipeline (LS), 5 is an arithmetic unit (ALU), 6 is a data distribution circuit, 7 is a data selection circuit. Vector register 2 each has a capacity to store L elements, and the total VR
, ~VR, are provided. One mask register 3 is provided with L bits. One bit in mask register 3 indicates the validity of one element in vector register 2. In this embodiment, for the sake of simplicity, there is one mask register, but there may be a plurality of mask registers. Load-store number pipeline 4 is L
5o-LS, 8 units, arithmetic unit 5 is ALU,
-A L U, there are 8 pieces.

Each load/store pipeline sequentially calculates the main memory address of each element of matrix-type data on the main memory, and issues a memory request to the main memory. The calculation result of the main memory address is obtained for each stage, which is the basic unit of pipeline operation, and memory requests are also issued at a pitch of one stage. When a load or store instruction is activated, eight load/store pipelines 4, LSo, LS, ..., LS, load and store simultaneously.
Start store processing. In the first stage, the main memory address α of elements numbered 0, 1, . . . , 7. ,α7,・
..., α, are calculated simultaneously in eight pipelines 4, and eight memory requests are issued to the main memory 1. In the second stage, No. 8, No. 9, ..., 1
Main memory address α3, α8, ..., α, of element number 5
5 are computed simultaneously in 8 pipelines 4, and 8
memory requests are issued to main memory 1. Thereafter, main memory addresses of eight elements are calculated simultaneously in eight load/store pipelines 4 for each stage, and eight memory requests are issued to the main memory 1. Data transfer of eight elements is then performed between main memory 1 and vector register 2 based on the memory request.

In the case of a load instruction, the address of the data on the main memory is sent from the load/store number pipeline 4 to the main memory 1 via path 8, and the data is sent from main memory 1 to the load/store number via path 9. - Taken out to pipeline 4. Furthermore, the data enters the data distribution circuit 6 via path 10, and is sent to the vector register 2 specified by the instruction via path 11.
written via.

In the case of a store instruction, data on the vector register 2 specified by the instruction is read out to the data selection circuit 7 via path 12 and enters the load/store pipeline 4 via path 15. In the load/store pipeline 4, the main memory address is given, the main memory address is placed on path 8, and the data is placed on path 16, main memory 1.
sent to.

Operations are performed on the data after it is loaded into vector register 2 and before it is stored. An operation is performed between the three registers specified by the operation instruction. Two of the five vector registers store operands, and the operands are sent to the data selection circuit 7.
The signal is read out via the path 13 and input to the arithmetic unit 5.

The calculation result is output from the calculation unit 5 and written to the vector Φ register 2 via the path 14 and the data distribution circuit 6. If the operation instruction is a mask generation instruction that generates mask bits corresponding to elements, the mask bits obtained as a result of the operation are written into the mask register 6.

The load/store processing in the load/store pipeline 4 is controlled by the mask bit of the mask register 5 for each element. Therefore, it is distributed to each pipeline via 717.

Next, FIGS. 2 and 3 show the transfer processing operation between compressed data on the main memory and decompressed data on the vector register.

FIG. 2 shows one piece of compressed data α on the main memory. , α1
・This shows the process of expanding and loading ゛~α2-1 onto a vector register. Before the load process, L-bit mask bits are set in the mask register 5 for the Lm element of the vector register 2.

Mask bits that indicate that the element is valid
The number v is equal to the number of compressed data elements in the main memory 1. The data on the main memory 1 is loaded into the element positions of the vector register 2 corresponding to the mask bitma 1v in order from the first element. Do not load into the element location corresponding to mask bit YQY.

FIG. 6 shows L pieces of expanded data α on vector register 2. , α1, ..., α, -1 are compressed and stored in main memory 1.
This figure shows the process of storing data in a file. Before store processing, L mask bits are set in mask register 3 for L elements of vector register 2. Contrary to loading, the data at the element positions of vector register 2 corresponding to mask bit w1F are stored in main memory 1 in order from the beginning.

FIG. 4 shows the configuration of an address calculation circuit with one load/store pipeline, and address calculation in compression/expansion type load/store processing will be explained. This figure shows the configuration of equation (3) when the multiplicity is M-8. In this case, eight elements in the data are loaded and stored in each stage, which is a unit of pipeline operation of processing. Each pipeline is given a value from 0 to 7 called a requester number via a signal line 33. Each pipeline recognizes and operates the sequence of elements to be processed based on the value of the quester number. In a pipeline with requester number 00, element α. , α6, α,6, . . . are sequentially loaded and stored.

When the instruction decoding circuit 20 decodes the load φ store instruction that instructs data transfer between the compressed data on the main memory 1 and the decompressed data on the vector register 2, the instruction decoding circuit 20 decodes the data on the main memory 1. Information for addressing compressed data is set in registers 21, 22, and 24. The start address of the data is set in the address register vAR21, the data interval value is set in the increment register VIR22, and the length of the data is set in the length register VLR24. Along with setting data-related information, data is loaded from signal line 37 iC.
A signal is sent to start the store process, and the latch 59 is set to 11.
Set to 1. The output of latch 59 opens A, N D circuit 40 that controls memory requests and loads.
Sending of memory request for store processing begins.

Eight mask bits for the number of pipelines are read in parallel from the mask 0 register VMR3 in synchronization with the load/store processing, and are read out from the register 18 via the bus 17.
is set to Reading of the mask bits is performed for each stage, similar to the unit of pipeline operation for load/store processing. The mask bits entered in register 1 are transferred to register 19 in the next stage. The outputs of registers 18 and 19 are input to bit selection circuits 35 and 36, and only bits within a certain range determined by the requester number are extracted and transferred to counter 23. Counter 23 counts the number of 111 bits in the selected mask bits, controls multiple generator circuits 26 and 27 from the counted number, and increments register VI
Generates a multiple of 0 to 7 times R22. Multiple generation circuit 2
6, the multiple is 8.4.0 times, and the multiple generation circuit 27 is 2.
．． Multiples of 1.0 and -1 are generated, respectively. By combining the two, a multiple of 0 to % can be obtained.

At the first stage of the load store process, the start address of the data is carried from the address register VAR21 via the selector 25 to the save adder CS A 29
is input. At the same time, based on the mask count number (the multiple of the increment register VIR is
．． 27 to the carry save fist adder CS A 29. Both are carry save adder CS A
29 and the parallel adder P A 30 immediately after it.
It becomes the main memory address of the element processed in the first stage. From the second stage onwards, the main memory address of the element processed in the previous stage is input again to the carry-save fist adder CS A 29 via the selector 25, in order to calculate the main memory address of the element processed in the stage. used. The only difference is that the address calculations in the second and subsequent stages use the main memory address obtained in the previous stage instead of the contents of the address register VAR21.

FIG. 5 shows an example of address calculation in the load/store pipeline of requester number 3. element α
The mask φ bit corresponding to the 8 elements following n-8 is '101101 Do', and the mask φ bit corresponding to the 8 elements following the element α to be processed in the next stage is '101101 Do'.
Assume that the bit is '01011001'. In the pipeline of requester number 5, element αn is added between two stages.
Road session store processing is performed for +5-II and element α1+5. The main memory address of element αn+5 is element αn
It is determined from the main memory address +&-8 and the mask bit VMR (s(i kill+5-8 to rule+2)) as follows.First, the bit selection circuit 65 selects the element αrL.
5 elements after +5-8 αrL+5-II %αW
+4-8% αW+5-! l % cLn, +6-J
Mask corresponding to %α1+7-6) '101
00' is selected. Next, the bit selection circuit 66 selects element α, the previous three elements a, rL1α, and 1.
, αrL and 2, the number generation circuit 26 has 4 *VIR,
The multiple generating circuit 27 generates (-1)*VIR, and both are added to αn+5-8 in the Charlie save adder CS A 29 and the parallel adder PA 30 to obtain cLrL+s.

*VIR −αn+s −a +(2+ 1 )*VI Rx a
n+,-,+! l * V I Rg αr,,+,
-, +4*VIR+(-1)*VIR...(4) In FIG. 4, the bit selection circuit 35 corresponds to the element to be processed in the pipeline, as well as the bit selection for determining the mask count value. Also performs mask bit selection. The mask bit position corresponding to the processing element is determined from the requester number.

The mask bits are extracted and sent to AND circuit 4o.

In the AND circuit 40, the memory request issue signal from the launch 39 and the mask e bit from the bit selection circuit 35 are ANDed and sent to the main memory 1 on the bus 16 as a memory request. If the mask number bit corresponding to the element to be processed is 117, a memory contention request is issued, and the corresponding element is read from or written to the main memory 1. mask·
If the bit is 0, memory contention requests are suppressed.

When issuing a memory session request, the main memory address calculated by the carry save fist adder CS A 29 and the parallel conflict adder PA3o is sent to the main memory 1 along with the memory request on the bus 13.

The length register VLR24 stores the length of data prior to load/store processing. Each time the load 0 store processing progresses one stage, the length
The contents of register VLR are subtracted by -8 by subtraction circuit 28K. In one stage of the load store process, the same number of elements as the number of pipelines (8) are processed at once, so the value is -8.

When the load/store process is executed for all elements, the subtraction result becomes 0 or less. Therefore, the sign detection circuit 3
1, the end of the process is detected, the end signal 38 resets the latch 40 to Jt, and the AND circuit 40 is closed.

Since the AND circuit 40 is closed, subsequent sending of memory requests is stopped.

According to this embodiment, data transfer between compressed data on the main memory and decompressed data on the vector register can be executed by a plurality of load/store pipelines installed in parallel.

Therefore, the data transfer speed can be increased by the same amount as the number of pipelines.

〔Effect of the invention〕

According to the present invention, in a vector processing device having an element-parallel multiple load/store pipeline, data between data compressed on main memory and data decompressed on a vector register is provided. Transfer can also be executed in element parallel form.Therefore, similar to normal simple load φ store, it is possible to obtain the data transfer speed equivalent to the number of pipelines installed in parallel.This allows compression/decompression Matrix calculations on sparse matrices that require type data access are processed quickly.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a vector processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the process of decompressing and loading data compressed on the main memory onto a vector register, and FIG.
The figure shows the process of compressing and storing the decompressed data on the vector register in main memory.
FIG. 5 is a diagram showing the configuration of the address calculation circuit of the store pipeline, and is a diagram showing an example of address calculation. 2...Vector register, 3...Mask register, 4...Load/store pipeline, 21...Address register, 22...Increment register, 35.36...
・Bit selection circuit, 25...Counter, 26.27...Multiple generation circuit, 29...Carry save adder, 30...Parallel adder. High 1 Figure, 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. Vector processing consisting of multiple arithmetic units, multiple vector registers, multiple vector mask registers that indicate data validity, multiple load/store pipelines, and interleaved main memory. In the apparatus, in order to transfer data between compressed data on main memory and decompressed data on a vector register, a method for identifying data to be processed in the pipeline in order to transfer data between compressed data on main memory and decompressed data on a vector register. a bit selection circuit that selects the contents of the mask register based on the requester number given to the bit string; a counter that counts the number of valid bits in the selected bit string; A multiple generation circuit that generates a plurality of multiples, and a multiplex generation circuit that simultaneously adds the main memory address of the data processed in the previous processing stage and the increment multiple of the multiple sets in the pipeline to generate the data to be processed in the next stage. 1. A vector processing device comprising a multi-input adder for calculating a main memory address, and performing the compression/expansion type data transfer using element parallel multiple pipeline operations.