JPS5834037B2 - address calculation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mechanism for calculating an address when accessing a language device in an electronic computer system.

Generally, the method used when accessing a series of data from a storage device is to have the control unit of the storage device write an address that contains the first data, an increment that is added to the previous address to calculate the address of the next data, and an increment that is added to the previous address to calculate the address of the next data. The address of the last data or the number of data to be accessed was given, and the data was extracted based on this and sent to the processing device in the pond.

As long as this method is used, the address of the data to be accessed in the storage device will increase unilaterally if the increment is positive, and if it is negative, it will be accessed as a continuous row of hectares or transferred to another device. are frequently required to do so.

In such cases, addressing in conventional computer systems requires operations on software, and addresses are calculated for each element.

Therefore, it was not efficient. This invention was made in consideration of these circumstances, and uses a modulo operation in mathematics, that is, an operation that takes a remainder, to calculate an address when accessing data to a storage device using a simple instruction word. It is an object of the present invention to provide an address calculation device that enables complicated data transfer and can perform calculations efficiently and in a short time.

Hereinafter, details of the present invention will be clarified by examples shown in the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Increment register 1 stores an increment for calculating the next address to the current address.

Address register 2 contains the address of the first data to be accessed.

Modulo register 3 stores a modulo when calculating an address.

When calculating an address, first the first address stored in the address register 2 is selected by the multiplexer 12 and transferred to the current address register 6.

At the same time, modulo register 3 and address register 2
The contents of are added by an adder 5 and inputted to a comparator 8.

The first data is accessed at the address of the current address register 6.

The address of the next data is the current address register 6.
The adder/subtracter 7 adds and subtracts the contents of the increment register 1 and the contents of the increment register 1 selected by the multiplexer 11, which is then selected by the multiplexer 12 and placed in the current address register 6 again.

Here, the contents of the current address register 6 and the result of the adder 5 are compared by the comparator 8.

The mode indicated by the operation mode register 4 is decoded by the mode selector 9, and if the mode is A2B, A2B is detected, or if the mode is A>B, when A>B is detected. , each performs a modulo calculation.

The modulo calculation is performed by subtracting the contents of the modulo register selected by the multiplexer 11 from the contents of the current address register 6 by using the adder/subtractor 7, selecting the result by the multiplexer 12, and inputting the result into the current address register 6 again. It will be done.

The above operations are controlled by control signals or timing signals given from the control unit 10.

An example of actual calculation is shown below.

In this case, a matrix stored as a series of column vectors is rearranged as a series of row vectors.

Now, starting from address 10 in the storage device, a 3×3 matrix A-(a
Suppose that ij) is stored as shown below.

The calculation mode specifies that the same number as the modulo is allowed as the remainder.

That is, in actual operation, modulo subtraction is performed only when A>B in comparator 8, and increment=3 and modulo=8 are specified.

The first address specifies 10, which contains "all".

Address calculation proceeds as shown below.

As shown here, data that was stored as a series of column vectors can now be retrieved as a series of row vectors.

Next, as another usage example, we will show a case where a synchronization function is created from only the data for synchronization.

From 0° to 3゛60° on the graph of y = S1nx in Figure 2
The sample value divided by 300 width is 00
It is assumed that they are stored in the storage device in this order from ■, ■, ■..., ■.

If the first data is at address O, then the arithmetic mode also allows the same number modulo as the remainder, and if increment = 1, modulo = 12, and first address = O, then as shown above , you can extract as many periodic functions as you need.

As in the example explained above, conversions that are generally processed on a program are processed efficiently and quickly on hardware, so for operations that require a lot of time, such as matrix operations, The structure of this mechanism is particularly effective.

Furthermore, as seen in the example of periodic functions, calculating a function value once and using it repeatedly is useful for saving storage capacity and shortening calculation time.

Next, an embodiment of the pond of the present invention will be described.

FIG. 3 is a block diagram showing an embodiment of the pond according to the present invention, and is an example in which only one adder/subtractor is used.

That is, the first address and the modulo are added using the adder/subtractor 7 for adding increments, and the result is put into the register 13, and the contents of this register 13 and the contents of the current address register 6 are compared by the comparator 8. The adder 5 in FIG. 1 is replaced with a register 13.

This embodiment also has the same effect as the previous embodiment since the remainder calculation can be performed.

FIG. 4 shows yet another embodiment of the invention, in which the divider 16 is used as defined to obtain the remainder.

In this embodiment as well, the same effects as in the previous embodiment can be obtained.

Various circuits can be considered that can perform the above-mentioned calculations.

As explained above, the present invention includes an increment register that holds the increment for calculating the next address for the current address, an address register that holds the address of the first data to be accessed, and a modulo value for calculating the address. An address calculation device characterized by comprising modulo registers that hold values and an arithmetic circuit that performs modulo calculations by selecting the contents of these registers in response to signals from a control unit and performing data transfer. be.

Therefore, according to the present invention, since processing performed on a program is generally processed at high speed on hardware, it is possible to provide an address calculation device that can efficiently calculate addresses in a short time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining the functions of the same embodiment, and FIGS. 3 and 4 are respectively the configuration of an embodiment of the pond of the present invention. FIG.

Claims (1)

[Claims] 1. Initial address data indicating the address to be accessed for the first time to the memory, increment data indicating the address difference between the current access address and the address to be accessed next time, and modulo data related to the address access order of the memory. After outputting the initial address data as current access address data,
The next access address data is created by adding the increment data to the current access address data.If the next access address data is smaller than the data set by adding the increment data to the previous initial address data, the next access address data is added. The data generated by subtracting the modulo data from the next access address data is output as the current access address data at the next access timing, and when the next access address data exceeds the setting data, the data generated by subtracting the modulo data from the next access address data is output as the current access address data at the next access timing. An address calculation device characterized by outputting data as data.