JPH05290080A - Parallel processor - Google Patents

Abstract

PURPOSE:To provide a highly reliable parallel processor at low cost by means of reducing a circuit amount. CONSTITUTION:The parallel processor having N-number of data processing parts is provided with N-number of first storage means 10 Which have mutually common address and independently operate, a second storage means 20 which has the storage parts of N-stages including an input stage and a final stage, inputs address data inputting data designating the address of the N-number of first storage means 10 in accordance with the N-number of data processing parts in serial to the input stage, shifts it to the direction of the final stage and supplies the outputs of the storage parts of the respective stages to the N-number of corresponding first storage means 10 as address signals, and a first selection means 30 outputting data which are read from the N-number of first storage means 10 based on the address signals from the respective storage parts in the second storage means to one of the N-number of data processing parts to which the address corresponds.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a parallel processing device used in a vector processor or the like. In recent years, the processing capacity of data processing devices has dramatically improved due to technological advances and the adoption of high-speed technologies such as pipeline systems. A method is widely used in which an independently operating arithmetic unit is provided, and the memory is divided into a plurality of independently operating banks to process data in parallel. Therefore, in a computer system that processes data stored in a memory having a bank configuration in parallel by a plurality of independent arithmetic units,
There is a demand for an efficient and economical parallel processing device.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of the essential parts of a vector computing device. The command buffer unit sets the instruction code read from the main memory or the buffer (or cache) memory (not shown) and output to the data bus in the instruction buffer and outputs it to the control unit. The control unit decodes the instruction code and controls the address unit and the vector unit based on the code to perform pipeline control of instruction fetch and execution. The address unit performs dynamic address translation (DAT) as necessary to generate a physical address to the main memory. The vector unit is a device to which the present invention is applied, and efficiently executes a vector operation by simultaneously operating a memory having a plurality of banks and a plurality of arithmetic units in parallel.

FIG. 5 is an explanatory view of the technical background of the present invention, in which the array of data on the bank is modeled for easy understanding. Memory 0 can operate independently
-3, the data is stored in banks 0-3 in an arrangement unique to a vector computer or the like. That is, the data to be supplied to the arithmetic units A to D are arranged in advance in the memory areas A to D extending over the banks 0 to 3 as shown in the figure by the compiler program. For example, a specific address of the physical addresses assigned to each bank is set to a, and the address considering the banks 0-3 is 0 / a-.
When expressed as 3 / a, the addresses of the data supplied to the arithmetic unit A are 0 / a, 1 / a, 2 / a, 3 / a, 0 / (a +
i), 1 / (a + i), 2 / (a + i), 3 / (a + i), 0 / (a + 2)
i), 1 / (a + 2i) ... Here, i is a predetermined value, and after accessing bank 0 to bank 3 for a certain address, the address is incremented by the increment i and updated. Similarly, the address of the data supplied to the arithmetic units BD is represented by replacing a with b, c and d, respectively.

FIG. 6 is a block diagram of a parallel processing circuit showing a conventional example.
Represents a circuit part that performs parallel processing. Throughout the drawings, the same reference numerals indicate the same or similar components.

The memory 10a is composed of independent banks B0-B3 capable of reading and writing simultaneously in parallel. counter
CNTA-CNTD hold the address of the memory 10a of the data supplied to the computing units 1A-1D, respectively. The load address signal LADR input from the outside is loaded and held at the timing of the load signals LDA-LDD corresponding to the arithmetic units 1A-1D. When accessing banks B0 to B3 and then returning to bank B0, the increments (Ia-Id) given by the externally input ENA-END signals, respectively.
After counting up, access continues.

The selectors SEL1A-SEL1D respectively select the addresses to be input to the banks B0-B3 with the selection signal SEL.
(For example, it is composed of 2 bits, and decimal values 0, 1, 2, and 3 are cyclically repeated). That is, FIG.
When the selection signal SEL takes a value (0-3) enclosed by a circle attached to the input of the selectors SEL1A to SEL1D, the input is selected and supplied to the banks B0 to B3, respectively.
For example, in the selector SEL1A, the selection signal SEL is 0, 1,
In case of 2 and 3, counters CNTA, CNTB, CNTC, CN in that order
Select the contents of TD and supply to bank B0.

Selectors SEL2A-SEL2D are selectors SEL
Similar to 1A-SEL1D, one set of data read from the banks B0-B3 is selected by the value of the selection signal SEL and supplied to the computing units 1A-1D, respectively. For example, when the selection signal SEL is 0, 1, 2, 3, the selector SEL2A selects the data read from the banks B0, B1, B2, B3 in that order and supplies it to the arithmetic unit 1A.

FIG. 7 is a timing chart of a conventional parallel processing circuit. (1) Address data a on the load address signal LADR
-D is input with the load signals LDA-LDD. (2) Address data ad are load signals LDA-LD
The counters CNTA-CNTD are set at the falling edge of the clock CLK when D is turned on. (3) The value of the counters CNTA-CNTD is then incremented by adding the increments Ia-Id given by the externally input ENA-END. (4) Selector SEL1A has select signal SEL 0, 1, 2,
When it changes to 3, the content a of the counter CNTA is selected and supplied to the banks B0, B1, B2 and B3 as addresses. In the figure, the address is 0 /
It is indicated as a, 1 / a, 2 / a, 3 / a. Further, the selector SEL1B selects the content b of the counter CNTB as the selection signal SEL changes to 1, 2, 3, 0, and selects the addresses 0 / b, 1 / b, 2 / b, 3 / b, Each,
Supply to banks B0, B1, B2, B3. Selector SEL1C and
SEL1D performs the same operation. (5) The selectors SEL2A-SEL2D also perform the same operation, and the selectors SEL1A-SEL1D sequentially select the data to be read from the banks B0-B3 to which the addresses are supplied and supply them to the computing units 1A-1D, respectively. To do. For example, selector S
The EL2A sequentially selects the data read from the addresses 0 / a-3 / a supplied by the selectors SEL1A-SEL1D to the banks B0-B3 and supplies the selected data to the arithmetic unit 1A. (6) Then, return to (3) above and repeat steps (3) to (5). When the load signals LDA-LDD from the outside are turned on, the procedure returns to (1) and the same operation is repeated.

[0009]

As described above, according to the conventional method, the counter for supplying the address to the memory bank and the two sets of selectors are required independently according to the number of arithmetic units or memory banks. And Therefore, there is a problem that the amount of circuits increases, the cost of the device increases, and the number of parts increases and reliability decreases.

An object of the present invention is to provide a low-cost and highly reliable parallel processing device by reducing the circuit amount.

[0011]

FIG. 1 shows a block diagram of the principle of the present invention. 1 is a plurality of N data processing units, 10
Is an N number of first storage means operating independently of each other having a common address, and 2i is a number of N data processing units for designating the addresses of the N number of first storage means 10. Address data to be serially input corresponding to 1, 20 has a storage unit of N stages including an input stage and a final stage, and address data 2i
Is input to the input stage and shifted toward the final stage, and the output of the storage unit of each stage is supplied as an address signal to each of the corresponding N first storage units (10). , 30 processes the data read from each of the N first storage units 10 based on the address signal from each storage unit of the second storage unit 20, to process the N data corresponding to the address. It is a first selection means for outputting to one of the parts 1.

[0012]

According to the present invention, in a device for performing parallel processing by a plurality of N data processing units 1, the N first storage means 10 have common addresses and operate independently. As the address data 2i, data designating the addresses of the N first storage means 10 are serially input corresponding to the N data processing units 1, and the second storage means 20 has an input stage and a final stage. The storage unit has N stages of storage, and the address data 2i is input to the input stage to shift toward the final stage, and the output of the storage unit of each stage is used as an address signal for the corresponding N first
Of the first storage means 10 and the first selection means 30 is read from each of the N first storage means 10 based on the address signal from each storage portion of the second storage means 20. The output data is output to one of the N data processing units 1 corresponding to the address. Therefore, the N first storage means 10 are operated in parallel by the individual addresses of the N data processing units 1 which are given by the address data 2i and are shifted in the second storage means 20. By reading the data and the first selecting means 30 sorts the read data to the corresponding N data processing units 1, the N data processing units 1 can perform parallel processing.

[0013]

FIG. 2 is a block diagram of a parallel processing circuit showing an embodiment of the present invention. Throughout the drawings, the same reference numerals indicate the same or similar components.

The arithmetic units 1A-1D are, for example, multipliers, adders, dividers, load / store units (or interface circuits that output data to an external circuit) that operate independently of each other.

Memory (or a group of registers)
10b is composed of banks B0-B3. Bank B0-
B3 is assigned a common physical address,
At the same time, it is a memory that can be read and written in parallel.

The selection signal SEL consists of 2 bits, and 1
Decimal values 0, 1, 2, 3 are cyclically repeated every clock cycle. The load address signal LADR is a physical address common to each bank, which is input from the outside (for example, a bus control circuit that controls a bus that couples the components of the vector computer). When it has a storage capacity, it is composed of 8 bits. When the vector computer starts the processing of a predetermined unit,
The start address of the area in which the data supplied to the computing units 1A-1D is stored is serially input for each period of one clock cycle.

The ENA-END signal is externally input corresponding to the arithmetic units 1A-1D, and is incremented (Ia
-Id) is given. Banks B0 to B3 are accessed at the same address (for example, a), and the address is advanced to bank B0.
When the access is started again (referred to as address updating), the address is updated by the increment (Ia-Id) corresponding to the arithmetic units 1A-1D and the access is continued. EN
The A-END signal is composed of 2 bits, for example, and
-Id can take values from 0 to 3.

The registers REG0 to REG3 are arithmetic units, respectively.
Holds the memory address where the data to be supplied to 1A-1D is stored. It is configured as a shift register that shifts data in the direction from register REG0 to register REG3. The outputs of registers REG0-REG3 are connected to banks B0-B3, respectively, and the addresses stored in registers REG0-REG3 are transferred to banks B0-B3. Supply to.

The selector SEL4 outputs an SE signal (OR circuit OR
When the logical sum of the load signals LDA-LDD by (1) is ON, the load address signal LADR (address signal corresponding to the arithmetic units 1A-1D, for example, a-d) is selectively output and supplied to the register REG0. When updating the address when the SE signal is off, the output of the adder ADD described later is selectively output and supplied to the register REG0.

When the address is updated, the adder ADD uses ENA
Update the address by adding the increment (Ia-Id) given by the -END signal to the contents of register REG3. The selector SEL5 selects and outputs one of the ENA-END signals corresponding to the values 0-3 of the selection signal SEL.

The selectors SEL2A-SEL2D select one set of data read from the banks B0-B3, respectively, according to the value of the selection signal SEL, and the arithmetic units 1A-1D respectively.
Supply to. That is, in FIG. 6, the selection signal SEL is the value (0) enclosed by a circle attached to the input of the selectors SEL2A-SEL2D.
When -3) is taken, that input is selected and supplied to the computing units 1A-1D. For example, the selector SEL2A uses the selection signal SEL
Are 0, 1, 2, 3 and banks B0, B1, B2, in that order
The data read from B3 is selected and supplied to the arithmetic unit 1A.

FIG. 3 is a timing chart of the parallel processing circuit according to the embodiment of the present invention. (1) The selection signal SEL is 0 for each clock cycle,
The values 1, 2 and 3 are cyclically repeated. (2) Address data a on the load address signal LADR
-D is input with the load signals LDA-LDD.
The address data a to d indicate the start address of the memory area in which the data to be supplied to the arithmetic units 1A to 1D are stored. (3) SE signal (load signal LDA by OR circuit OR
When the logical sum of LDD) is turned on, the address data a on the load address signal LADR is
It is set in the register REG0 at the falling edge of the clock CLK when A is on. At the same time, the bank B0 is accessed by using the content a in the register REG0 as an address. (4) The read data is selected by the selector SEL3A according to the value of the SEL signal (the SEL value is 0 at this time) and supplied to the computing unit 1A. That is, as indicated by 0 / a in the figure, the data stored in the address a of the bank B0 is read and selected by the selector SEL3A. (5) Next, when the load signal LDB is on, the contents a of the register REG0 are registered at the falling edge of the clock CLK.
Shifted to REG1 and load address signal LAD
The address data b on R is set in the register REG0. At the same time, the bank B1 is accessed using the content a of the register REG1 as an address, and the bank B0 is accessed using the content b of the register REG0 as an address. (6) The read data of 1 / a and 0 / b are selected by the selectors SEL3A and SEL3B, respectively, according to the value of the SEL signal, and are supplied to the arithmetic units 1B and 1A. (7) Next, the addresses c and d are sequentially set from the load address signal LADR to the register REG0, and similarly, the shift operation, the bank access, the read data selection, and the supply to the arithmetic unit are performed. .. (8) When the address data a is shifted to the register REG3, the adder ADD adds the Ia of the ENA signal selected by the selector SEL5 to the address data a. Since the SE signal is off, the selector SEL4 selects and outputs the output of the adder ADD. The contents of the registers REG0-REG2 are respectively shifted to the registers REG1-REG3, and at the same time, the value of a + Ia is set to the register REG0. (9) Bank B0 is accessed with a + Ia set in register REG0 as an address. (10) The read data is selected by the selector SEL3A according to the value of the SEL signal (the SEL value is 0 at this time) and supplied to the computing unit 1A. That is, 0 / a + in the figure
As indicated by Ia, the data stored in the address a + Ia of the bank B0 is read and selected by the selector SEL3A. At the same time, the same operation is performed for the addresses d, c, b in the registers REG1, REG2, REG3. (11) Next, similarly, the address b + Ib is set to the register RE.
It is set to G0, and the same operation is repeated until the SE signal turns on next.

The data supplied to the arithmetic units 1A-1D do not have to be divided and arranged in areas A-D as shown in FIG. 5, and may be overlapped with each other. Also, the increment Ia
-Id may be a different value for the arithmetic units 1A-1D, or may be a value that changes for each update after sequentially accessing banks B0-B3 for the same arithmetic unit. Good.

As described above, the registers REG0-REG3 supply addresses to the banks B0-B3 while shifting the address data corresponding to the arithmetic units 1A-1D, which are serially input from the outside. , Data is sequentially read from a common address in each of the banks B0 to B3. Selectors SEL3A-SEL3D select the read data and supply them to the corresponding computing units 1A-1D. Therefore, the banks B0-B3 operate simultaneously, and each of the arithmetic units 1A-1D independently operates in parallel, so that the data stored in the memory 10b can be processed in an arrangement unique to a vector computer or the like. .. Regarding the circuit amount, the present invention uses the counters CNTA-CNTD of the conventional example as the shift register REG0.
By replacing with -REG3, the circuit amount is reduced, and by eliminating the need for four selectors SEL1A-SEL1D for inputting 4 sets of 8 bits of address, which are required in the conventional example, the arithmetic units 1A-1D In addition, the circuit volume of the circuits shown, excluding banks B0-B3, could be cut in half.

[0025]

As described above, according to the present invention,
Each of the N first storage means 10 operates in parallel, and N
By operating the data processing units 1 independently and in parallel, it is possible to process the data stored in the N first storage units 10 in the arrangement unique to the vector computer or the like. Further, according to the circuit configuration of the present invention, the circuit amount can be reduced, the cost of the parallel processing device can be reduced, and the reliability thereof can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram of a parallel processing circuit showing an embodiment of the present invention.

FIG. 3 is a timing diagram of the parallel processing circuit according to the embodiment of the present invention.

FIG. 4 is a block diagram of a main part of a vector calculation device.

FIG. 5 is an explanatory diagram of a technical background of the present invention.

FIG. 6 is a block diagram of a parallel processing circuit showing a conventional example.

FIG. 7 is a timing diagram of a parallel processing circuit of a conventional example.

[Explanation of symbols]

 1 N data processing units 10 N first storage means 20 second storage means 30 first selection means 2i address signal 10b memory ADD adder B0-B3 bank OR OR circuit REG0-REG3 register SEL3A- SEL3D, SEL4, SEL5 selector

Claims (3)

[Claims] 1. A device for performing parallel processing by a plurality of N data processing units (1), the N first storage means (10) having mutually common addresses and operating independently. And address data (2i) for serially inputting data designating addresses of the N first storage means 10 corresponding to the N data processing units 1, and an input stage and a final stage. The memory unit has N stages, the address data (2i) is input to the input stage and shifted toward the final stage, and the output of the memory unit of each stage is used as an address signal to correspond to the N first corresponding units. Second storage means (20) for supplying to each of the storage means (10) of the
The data read from each of the N first storage means (10) on the basis of the address signal from each storage section of the storage means (20) is processed by the N data processing corresponding to the address. A parallel processing device comprising: a first selecting means (30) for outputting to one of the units (1). 2. N sets of external address signals (4i) externally input corresponding to the N data processing units (1), and a storage unit at a final stage of the second storage unit (20). Selecting means (50) for adding a predetermined data (51) to the address data, the N sets of address data input by the external address signal (4i) and the output data of the adding means (50) 2. The parallel processing apparatus according to claim 1, further comprising a second selecting means (40) for outputting the address signal (2i). 3. An increment signal (6i) externally input corresponding to the N number of data processing units (1), and the second storage means (20) from among the increment signals (6i). The N data processing units (1) corresponding to the address data in the storage unit at the final stage of
Select the increment signal corresponding to the above-mentioned predetermined data (51)
3. The parallel processing apparatus according to claim 2, further comprising a third selecting means (60) for outputting as.