JPS62118436A - Adder - Google Patents

Abstract

PURPOSE:To shorten the adding time by executing a prescribed pretreatment to the bit of the remainder of long digits in the binary addition in which two complements of 2 having the number of the different digit are displayed. CONSTITUTION:Xn-, X show the augend and Yj-, Y show the addend (i>j). A bit Xs is found out in which the propagation of the carry outputted from a (j) bit full adder by the positive and the negative of an addend Yn as the pretreatment in Xi-, Xj+1 is stopped. With the bit Xs as the border, the augend is divided into two parts Xi-Xs+1 and Xs-Xj+1. Concerning Xi-Xs+1, the normal rotation output is outputted and concerning Xs-Xj+1, the inverting output is outputted. Next, when the carry is executed by the selector, the result obtained by the pretreatment is outputted, and when the carry is not executed, by outputting the Xi-Xj+1 as it is, the adding result is obtained. Thus, the adding time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an adder for binary numbers expressed in two's complement numbers having different numbers of digits.

[Conventional technology]

Conventionally, in an adder, even if two binary numbers have different numbers of digits, the number of full adders is adjusted to the longer number of digits because there is propagation from the lower bits to the carry. In other words, the addend Yn of the number of digits i (%=Oj1, -, i) the summand of the number of digits Xn (s = 0.1. ”・,
/ ) (i>'J), one adder is required as shown in FIG. The bits in parentheses represent the extension of the sign bit in two's complement representation.

5iE3i-t...S, S indicates the addition result.

[Problem that the invention seeks to solve]

In the conventional adder described above, even though the number of bits of the addand and the summand are different, the number of full adders is matched to the number of digits of the larger one, and the extra (j-j) bits are )
Also, since the carry needs to be propagated in the same way as in general addition, there is a drawback that the application time is the same as that required for addition of equal bit lengths.

[Failure to solve the problem]

The adder of the present invention has two binary numbers X expressed as two's complement numbers having different numbers of digits (%= 0.1.2..., i
).

Y% (ru 0.1.2...,)°) (however, t>
)''), which is an adder for X1Xi-t...Xl-j
Starting from the bottom pit Xi-no, when Ys is a positive number, the bit X# where "@0" appears first is detected, and when Ys is a negative number, the bit xI where "1" appears first. , means for directly outputting Y% as the addition result for the bits Xi... As for Xl, Xl-1, . . .

In the present invention, among the bits from the (j+1)th pit to the i-th bit of the binary number
Focusing on the fact that carry propagation stops at bit X# where 01 appears, from Xa+* to Xi, Y% is used as the addition result, and from Xj to Xa, it is inverted or normal depending on whether there is a carry from the lower bit. By using this as the addition result, the number of full adders and the addition time are reduced.

FIG. 2 is a flowchart showing the processing flow of the adder of the present invention. First, depending on the sign of the addend Ys, when it is positive, the bit Xs where @0'' appears first is searched for from the +1 bit of the summand Xn toward the higher bits. Executes addition below the bit and determines whether there is a carry.This can be done without actually performing addition.
A carry lookahead function that determines the presence or absence of carry is sufficient. Next, if there is no carry after Xl, the summand
s,..., Xj+*) is inverted and Xt,...
Xl+1 is rotated in the normal direction and output as the addition result. When Yn is negative, XJF is the bit in which @1" appears first, and the carry is the same as @Om and 11" is read as absent, which is the same as when Y% is positive. can be processed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of an adder according to the present invention.

η,...l X is the summand, Y/-..., Y is the addend (i>)°). Xi,..., Xi+
At t, as preprocessing, we find the bit (XJ) where the propagation of the carry output from the j-th full adder stops depending on the sign of the addend Ys, and divide the summand into two parts Xi, ・..., Xl+
1 and x#I..., Xj+*, and when there is a carry from the jth bit, xi,..., Xz+s are rotated forward, x#,..., X/ are inverted and output. prepare for. That is, for Xi=Xl+1, a normal output is output, and for Xa...Xl+1, an inverted output is output. Next, when there is a carry by the selector, the result obtained in the preprocessing is output, and when there is no carry, the Xi
... Obtain the addition result by outputting Xi's as is.

Figure 3 shows the 9-bit summand XQ, X9 and the 3-bit summand
An example of an addition circuit for addends YO to Y2 is shown. A Manchester single-chain carry propagation circuit is used to add the lower three bits. As can be seen from this circuit, the time from when the addend and summand are determined until the carry is output from the third bit full adder is almost equal to the time required for the preprocessing described above. Therefore, after the carry is output, the output of the upper bits from the 4th bit can be obtained by one process (select), and the speed is significantly increased compared to the conventional method.

〔Effect of the invention〕

As explained above, in the addition of two binary numbers with different numbers of digits, the present invention performs preprocessing on the remaining bits of the long number of digits, and uses a carry signal from the lower bits to add one binary number. An addition result corresponding to the remaining bits can be obtained through processing, which has the effect of significantly shortening the addition time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the adding circuit of the present invention, FIG. 2 is a flowchart of processing of the adding circuit of the present invention, and FIG. 3 is a circuit diagram showing an embodiment of the adding circuit of the present invention. FIG. 4 is a configuration diagram of a conventional example.

Claims (1)

[Claims] Two binary numbers X expressed as two's complement numbers with different numbers of digits
n (n=0, 1, 2, ..., i), Y_n (n=0, 1,
2,...,j) (where i>j),
iX_i_−_1…X_i_−_j lower bit X_i
Starting from ____j, if Y_n is a positive number, first “0”
means for detecting the bit X_s where "1" appears first when Y_n is a negative number, and the bit X_s where "0" or "1" appears first.
Bits from the most significant bit of s X_i...X_s_-
For _1, there is a means for outputting X_n as it is as an addition result, and a means for outputting X_s to the lower bits X_sX_s_-_1...X_j
The adder has means for inverting or normal rotating X_n and outputting it depending on whether there is a carry or not due to the addition result of the j-th bit and below.