SU1608647A1 - Device for dividing golden proportion parallel codes by two - Google Patents

Abstract

The invention relates to computing and can be used to divide the golden ratio codes in specialized computing devices. The purpose of the invention is to reduce hardware costs. The device contains N one-bit binary adders 9-16, N-bit information inputs 1-8 and N-bit information outputs 17-24, input 25 logic zero. 1 il.

Description

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The invention relates to computing and can be used to divide the golden ratio codes in specialized computing devices.

The purpose of the invention is to reduce hardware costs,

The drawing shows a functional diagram of an eight-bit device for dividing the golden ratio into two parallel codes,

The device contains information inputs 1-8 for supplying the golden ratio to the device of the eight-bit parallel code, single-charge binary adders 9-16 for generating the result of the operation, information outputs 17-24 for outputting the private bits, | input 25 logical zero. The adder 9 corresponds to the highest bit of the device. The golden proportion code is the representation of any real number in the form

No. D C; oi,

where

(x; - i- degree of the number of gold

proportions.

The essence and the physical possibility of dividing into two parallel codes the golden ratio lies in eating. . . . -,

In the code of the golden ratio between the weights of bits there is the following relationship

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With a single value of i-ro bit, it is scanned to lower bits. If a unit is in the 1-1) -th bit and a unit is scanned into the i-ro bit, we get the superposition of two units in one bit. In this case, in (il) -M bit of the result of dividing the parallel code there will be a single value for two, With the arrival of a single value (i-2) -ro bit, if there was a unit sweep from the previous bit, in (1-2) th digit of the result there will be a single value otherwise units from (i-2) -ro bit to low bit

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Thus, the golden ratio is divided into two parallel p-bits of the code.

The device works as follows.

We divide into two the parallel code of the golden proportion 10010110, the first information input of the adder 9 from the information input 1 of the device receives a single signal, the second and third inputs receive zero signals, therefore the information output 17 (transfer output) of the device generates a zero signal, and The output of the cyMtvb adder 9 is set to a single signal, which is fed to the second information input of the adder 10 and to the third information input of the adder 11, At the first information input of the adder 10 from the information input ode device 2 receives a zero signal on the carry input of the adder 10 receives a logic zero signal. Thus, at the information output 18 (transfer output) of the device, a zero signal is generated, and at the sum output - one

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A significant signal that arrives at the second information input of the adder 11 and at the transfer input of the adder 12. At the first information input of the adder 11, a zero signal comes from the information input 3 of the device. Thus, at the information output 19 a single-level signal is generated, and the output of the sum is a zero signal that goes to the second input of the adder 12 and to the transfer input of the adder 13. To the first information input of the adder 12 comes from the information input 4 of the device a single signal. Thus, a unit level signal is generated at the information output 20 of the device, and a zero signal is output at the sum output, which is fed to the second input of the adder 13 and to the transfer input of the adder 14.

At the first information input of the adder 13 from the information input 5 of the device receives a zero signal. Due to the presence of zero signals at all inputs of the adder 13, the information output 21 (transfer output) and at the output, the sum, a zero signal is generated, which is fed to the second information input of the adder 14 and to the transfer input of the adder

15. The first information input of the adder 14 from the information input 6 of the device receives a single signal NSL, which sets the information output 22 of the device to the zero state, and the output of the sum to the single state.

A single signal from the output of the sum of the summator 14 is fed to the input of the transfer of the adder 16 and to the second input of the adder 15, to the first input of which from the information input 7 of the device receives a single signal. Consequently, a single signal is generated at the information output 23 (1 transfer output) of the device, and a zero signal is output at the sum output. The zero signal from the output of the sum of the adder 15 is fed to the BT input of the adder 16, to the first B1, from which the zero С1: drive comes from the information input 8 of the device, resulting in the information from the C1; zero signal. Thus, at the output of the device, 00110010 was installed.

Claims (1)

The invention The device for dividing into two parallel codes the golden ratio, containing n single-digit binary adders, is characterized by the fact that, in order to reduce hardware costs, the transfer output i-rc of the single-digit binary adder (where i, 2, .. ,, n) is connected to the information output. The 1st bit of the device, the information input of the i-ro bit of the device is connected to the first information: the input of the i-ro one-digit binary adder, the input of the logical zero of the device is connected to the second information input and the transfer input of the first one-bit binary totalizer and the transfer input the second one-bit adder, the output of the sum of the (21 - 1) single-bit binary adder is connected to the second information inputs of the 21st and (21 + 1) -th one-bit binary adders, the output of the sum of the 21st one-bit adder is connected to transfer inputs of (21 + 1) -th and (21 + 2) -th one-bit adders.