SU1174920A1 - Associative adding device - Google Patents

Abstract

An ASSOCIATIVE SUMMATING DEVICE containing an associative storage unit, a permanent storage unit, the first and second groups of elements And, the first and second groups of delay elements, the address inputs of the permanent storage unit connected to the outputs of the corresponding elements And the first group, the first inputs of which are connected to the first synchronization input of the device, the first bit output of the associative storage unit is connected to the output of the device's sum, and the remaining discharge outputs are connected to the inputs The corresponding delay elements of the first group, the outputs of the elements of the second group are connected to the corresponding polling inputs of the associative memory block, the first inputs of the elements of the second group are connected to the second synchronization input of the device, the bit outputs of the permanent memory of the block, except the low-level output, are connected with inputs of the corresponding delay elements of the second group, characterized in that, in order to reduce hardware costs, the device contains the first and second converters binary About the code is a compressed code, the inputs of the first converter (L is a binary code, the compressed code is connected - with the inputs of the device's components, and the outputs are connected to the second inputs of the corresponding AND elements of the first group, the inputs of the second converter of the binary code to the compressed code are connected respectively to the low-order output constant; 4th storage unit, with outputs CO ND delay elements of the first group and with outputs of delay elements of the second group, and the outputs are connected to the second inputs of the corresponding elements AND Ora group.

Description

one

The invention relates to the field of computing and can be used in devices for processing arrays of numbers.

The aim of the invention is to reduce the hardware costs in an associative summing device.

Figure 1 presents the structural diagram of the associative summing device; Fig. 2 illustrates the spreading of information in constant and associative storage blocks for the case of the summation of seven operands.

The device contains a permanent storage unit 1, associative storage unit 2, converter 3 and 4 of binary code into compressed code, groups of elements I and 6, groups of elements 7 and 8 of delay, information inputs 9, inputs 10 and P of synchronization and output 12 amounts.

The device works as follows.

The inputs 9 receive single-digit bits of all the terms, starting with the lower bits. Converter 3 converts the binary code arriving at its inputs into a compressed code, which, through elements 5, enters the address input of storage unit 1 during a clock pulse at input 10. The word read from block 1 is part of the associative attribute for the associative memory block 2. The second part of the feature is, all but the first bit of the code read from block 2. Both parts of the feature are sent to the binary code converter into the compressed code 4 via delay elements 7 and 8, and the least significant bit, read from block 1, goes to the converter, - the user 4 without delay. The sign 4 formed at the output of the converter is additionally synchronized by the pulse at the input 11 with the help of the elements of AND 6. Such a fucking eliminates the influence of the imperfection of the elements 7 and 8 of the delay. ki At output 12, the next amount of the sum is formed. The total number of tactical sum calculation is equal to

n

m

where n is the size of the terms; H is the number of terms.

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Let it be necessary to sum up the following seven components: 010110; 101011; 011011; 111111; 101110; 110011; lOlOiO. The sections to be processed and the input of the converter 3 are 0111010; 1111111; 1001100; 0111101; 1011010; 0101111.

At the output of the transducer 3, processed sections are of the form 0001111; 1111111; 0000111; 0011111; 00011 and; 0011111.

During the first clock pulse applied to the synchronization input 10, the address input of the unit 1 is supplied from the output of the converter 3 and the lower bits of the terms, i.e. address 00011P ..

At the specified address from block 1, the word OOP is read in the same cycle, the first bit of which without delay is fed to the first input of the converter 4, and the rest through the delay elements 7 to the corresponding inputs of the same converter. Since nothing is read in the first clock cycle from block 2, by the arrival of the first pulse on the synchronization input 1I, all the inputs of the converter

0 4 served zeros.

The formed characteristic from the output of the converter 4 codes - OOOOOOOOO, with the arrival of the clock pulse at the input 1. enters the indicative inputs

5 of block 2. Consequently, in the first clock cycle from block 2, the word 0000 is read, the first bit of which O is the least significant bit of the required amount.

During the second pulse, applied to the synchronization input 10, the second bit of the summand is sent to the input of address 1 from the output of the converter 3, i.e. address 1111111. At the specified address from block 1

5 the word 1111 is read. The word 1011000 is formed at the input of the converter 4, respectively, at its output 0000111, which arrives at the input of the pulse 11 to the sign inputs of block 2, from which the word OOP is found, the first bit of which 1 is the second bit required amounts.

During the third pulse, applied to the synchronization input 10, the third processed slice 0000111 is fed to the input of the block 1 address from the output of the converter 3.

At the specified address from block 1, word 1001 is read. At the input of converter 4, the word 1I11001 is formed, respectively, at its output 0011111, which, when a pulse arrives at input 11, goes to the sign input of block 2, from which word 0111 is read

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bit 1 of which is the third bit of the required amount.

Similarly, the proposed device continues to work until the tenth digit amount is received. The amount code for this is 100-100110. In the eighth and ninth clock cycles, zero codes arrive at the input of the converter 3.

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Claims (1)

ASSOCIATIVE SUMMING DEVICE containing an associative storage unit, a permanent storage unit, the first and second groups of elements And, the first and second corpse? pi delay elements, and the address inputs of the permanent storage unit are connected to the outputs of the corresponding elements of the first group, the first inputs of which are connected to the first input of the device synchronization, the first bit output of the associative storage unit is connected to the output of the sum of the device, and the remaining dirty outputs are connected to the inputs of the corresponding elements delays of the first group, outputs of the elements AND of the second group are connected to the corresponding inputs of the poll of the associative storage unit, the first inputs of elements of the second group are connected to the second synchronization input of the device, the bit outputs of the permanent storage unit, in addition to the low-order output, are connected to the inputs of the corresponding delay elements of the second group, characterized in that, in order to reduce hardware costs, the device contains the first and second binary converters code δ is a compressed code, and the inputs of the first binary code converter, the compressed code is connected to the inputs of the terms of the device, and the outputs are connected to the second inputs of the corresponding of their elements And the first group, the inputs of the second binary code converter into the compressed code are connected respectively to the output of the least significant bit of the permanent storage unit, to the outputs of the delay elements of the first group and to the outputs of the delay elements of the second group, and the outputs are connected to the second inputs of the corresponding elements of the And second group. SU „„ 1174920